CN116106629B - Frequency response testing method for power supply impedance - Google Patents
Frequency response testing method for power supply impedance Download PDFInfo
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- CN116106629B CN116106629B CN202310362710.8A CN202310362710A CN116106629B CN 116106629 B CN116106629 B CN 116106629B CN 202310362710 A CN202310362710 A CN 202310362710A CN 116106629 B CN116106629 B CN 116106629B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
Abstract
The application belongs to the technical field of microelectronics, and particularly discloses a frequency response testing method of power supply impedance, which is applied to a chip containing an amplifier and comprises the following steps: enabling an amplifier for testing in the chip to be in a working state; inputting a first signal with the frequency f1 to the input end of the amplifier to be tested; inputting an analog power supply interference signal to an input end of the amplifier for testing; measuring a signal to be measured of an output end of an amplifier inputting a first signal f1, and obtaining a frequency response curve of an output signal taking the first signal f1 as a center frequency; and qualitatively judging the relative power supply impedance of the amplifier according to the frequency response curve. The method has the advantage that the trend of the actual impedance of the power supply end along with the frequency can be qualitatively judged through observing the envelope curve of the frequency response curve.
Description
Technical Field
The application relates to the technical field of microelectronics, in particular to a frequency response test method of power supply impedance.
Background
In an integrated chip, in order to reduce power supply ports, or to rationally layout the power supply network within the chip, each active device 1 (e.g., an amplifier) within the chip is typically connected to a power supply network 3 of a substrate (or PCB board) through a pin 2 (BUMP), and then to an external power supply 4 through a port of the substrate, as shown in fig. 1. If the impedance of the power port (i.e. at the pin 2) of the active device 1 is too large, a large power ripple will be generated under a small current signal, so that the impedance frequency response (i.e. the relation between the impedance and the frequency) of the power port of the active device 1 needs to be tested and verified when the quality of the chip is checked.
However, at present, a method for clearly describing the change of the power supply impedance with the frequency has not yet appeared. Because, in many cases, the working power supply end of the electronic component is generally only connected with direct current, and an SMA port is not usually provided, so that impedance test cannot be performed by using standard instruments such as a network analyzer.
If the signal such as ripple on the port is measured directly at the power supply end by the probe 5 as shown in fig. 1, the accuracy of the test may be affected by the excessive parasitic inductance of the probe 5 (and possibly even greater than the parasitic inductance between the pin 2 and the substrate). Moreover, testing with probes also faces the problem of disassembling chips in the field of integrated chips. Because the active device 1 is already integrated inside the chip, the probe needs to be measured at the position closest to the power supply terminal of the active device 1 if the above method is to be used. This results in destructive testing, increasing the cost and complexity of the test.
Disclosure of Invention
In order to solve the above-mentioned drawbacks, the present application proposes a frequency response testing method of power impedance, applied to a chip including an amplifier, comprising:
enabling an amplifier for testing in the chip to be in a working state;
inputting a first signal with the frequency f1 to the input end of the amplifier to be tested;
inputting an analog power supply interference signal to an input end of the amplifier for testing;
measuring a signal to be measured of an output end of an amplifier inputting a first signal f1, and obtaining a frequency response curve of an output signal taking the first signal f1 as a center frequency;
and qualitatively determining a relative power supply impedance of the amplifier according to the frequency response curve, wherein the relative power supply impedance indicates the power supply impedance of the amplifier relative to the output signal power.
In the above method, the step of inputting the analog power supply interference signal to the power supply terminal of the amplifier to be tested includes:
and inputting a double-tone signal with a second signal and a third signal to a power supply end of the amplifier to be tested, wherein the frequency f2 of the second signal and the frequency f3 of the third signal fall outside a test frequency band at two sides of the first signal f1, and the difference value of the second signal and the third signal is used for simulating the power supply interference signal.
In the above method, the first signal f1 and the binaural signal are connected through the input terminal of the same amplifier.
In the above method, the first signal f1 is input to one amplifier, and the binaural signal is input to the other amplifier.
In the above method, the first signal f1 is input through a signal source.
In the above method, the diphone signal is input through a network analyzer.
In the method, the power supply end of the amplifier is provided with the decoupling capacitor for filtering out the secondary and more harmonic wave and the higher-order intermodulation signal with the frequency larger than the second harmonic wave.
In the method, the signal to be tested is tested by using a spectrometer and the frequency response curve is recorded.
In the method, the chip comprises a chip integrated with a single-stage amplifier or a multi-stage amplifier or the chip is a radio frequency transceiver chip.
In the above method, when the frequency response curve of the output signal with the first signal f1 as the center frequency is obtained, the frequency difference f3-f2 between the second signal and the third signal is swept from zero to be output.
In the above method, the frequency response curve is a frequency-voltage relationship curve or a frequency-power relationship curve.
Compared with the prior art, the method and the device have the advantages that the first signal is input to the input end of the amplifier to be tested and the interference signal is input to the power end of the amplifier to be tested to artificially generate the predictable output signal at the output end of the amplifier to be tested, and then the change of the impedance of the power end of the amplifier to be tested relative to the frequency is qualitatively deduced according to the response amplitude of the frequency response curve of the output signal, so that qualitative guidance can be provided for subsequently adjusting the parasitic capacitance of the power end.
Drawings
FIG. 1 is a schematic diagram of the connection of an integrated on-chip power supply network;
FIG. 2 is a schematic equivalent circuit diagram of an amplifier connected on the same power network inside an integrated chip in an embodiment of the present application;
FIG. 3a is a test circuit diagram of measuring the frequency response of the power supply impedance of an active device according to an embodiment of the present application;
FIG. 3b is an impedance equivalent diagram of the J point in FIG. 3 a;
fig. 4a is a power spectrum image of the output end of the first amplifier 21 actually measured in the circuit diagram shown in fig. 3 a;
FIG. 4b is a simulation diagram of the power supply impedance magnitude in the circuit diagram shown in FIG. 3 a;
FIG. 5 is a flow chart of measuring the frequency response of the power supply impedance of an active device according to an embodiment of the present application;
fig. 6 is another test circuit diagram for measuring the frequency response of the power supply impedance of an active device according to an embodiment of the present application.
Detailed Description
Further advantages and effects of the present application will be readily apparent to those skilled in the art from the present disclosure, by describing embodiments of the present application with specific examples. While the description of the present application will be presented in conjunction with the preferred embodiments, it is not intended that the invention be limited to this embodiment. Rather, the invention has been described in connection with specific embodiments, and is intended to cover various alternatives or modifications, which may be extended by the claims based on this application. The following description contains many specific details in order to provide a thorough understanding of the present application. The present application may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the focus of the application. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
It should be noted that in this specification, like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in the following figures, defaults to the same definition.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
In order to solve the technical problems set forth in the background art, the inventors have conducted intensive studies, and the entire analytical study procedure is explained below.
With respect to the circuit configuration of the background art, the inventors have conducted equivalent processing of the circuit, and fig. 2 is a schematic equivalent circuit diagram of an amplifier connected to the same power supply network inside an integrated chip. The integrated chip can be a chip integrated with a single-stage amplifier and a multi-stage amplifier, and also can be a radio frequency transceiver chip.
In fig. 2, the first amplifier of fig. 1 is retained as the amplifier under test, and amplifier 21 is the subject of investigation in the following description, illustrating the relationship of its power supply terminal impedance to its output terminal frequency response curve. The other amplifiers in fig. 1 are modified in fig. 2 to be small-signal ac equivalent circuits (those skilled in the art will appreciate that in an ac small-signal operational model, the amplifiers may be equivalently RC parallel circuits).
Furthermore, as an amplifier integrated inside the chip, it is connected to the power supply V (i.e., the power supply network 3) through pins (BUMP), and thus, in a small-signal ac equivalent circuit, the pins (BUMP) of the power supply terminal of the amplifier may be equivalent to the inductance L connected across the power supply V and the power supply terminal of the amplifier. Thus, in the circuit diagram shown in fig. 2, the first amplifier 21, the inductance L, and the decoupling capacitor C0 at the power supply terminal constitute a first circuit unit 22 (corresponding to the first active device 1 in fig. 1); the equivalent RC parallel circuit of the amplifier, the inductance L and the decoupling capacitance C0 of the power supply terminal constitute a second circuit unit 23 (corresponding to the second active device 1 in fig. 1) and a third circuit unit 24 (corresponding to the third active device 1 in fig. 1).
The cause of generation and deterioration of the power supply ripple will be described below based on the circuit diagram shown in fig. 2.
In the first circuit unit 22, the impedance at the power supply terminal J is typically capacitive, i.e. the magnitude of the impedance at the power supply terminal J is related to the frequency of the signal, due to the presence of undesired parasitic inductance or capacitance in the circuit. If the impedance at the power supply terminal J is too large, a small current on the power supply network will generate a relatively large power supply ripple at the power supply terminal J of the first amplifier 21. Further, through the power supply network 3, the power supply ripple may be coupled to the power supply terminals of other devices, which may also cause interference to other devices.
If the power supply disturbance signal (power supply ripple) is simulated by the two-tone signal (two signals with frequencies f2 and f3, respectively), the decoupling capacitor C0 at the power supply terminal J of the first amplifier 21 can filter out the harmonic waves of the two-tone signal and the higher order intermodulation amount greater than the second harmonic frequency, but cannot filter out the first order difference frequency signal with low frequency (frequency: f3-f 2). I.e. the first order difference frequency signal f3-f2 will be mixed as an interference signal into the first amplifier 21, i.e. the difference frequency of the two-tone signal can be used to simulate the mains ripple.
When an input signal (frequency f 1) is input to the input terminal of the first amplifier 21, the first-order difference signal f3-f2 and the input signal f1 are mixed by the first amplifier 21, and each signal component obtained at the output terminal includes the intermodulation signal f1± (f 3-f 2). The intermodulation signal falls within the operating bandwidth of the first amplifier 21 and cannot be filtered out by means of filtering. That is, the two-tone signals (f 2 and f 3) for simulating the power supply ripple are coupled to the power supply terminal J of the first amplifier 21 through the power supply network, and finally form a disturbance at the output terminal of the first amplifier 21. Then, taking the above-mentioned two-tone signal as an example, for the first amplifier 21, the decoupling capacitor C0 can filter out the harmonics of the second order and above and the higher-order intermodulation amount greater than the second harmonic frequency; the intermodulation signals of higher order third order and above, which are close to the fundamental wave frequency, pass through the output end to the antenna and do not pass through the power supply end, so that the second order intermodulation amount f2-f1, which is the most affected, is calculated by the following formula:
wherein I (f 3-f 2) is the current of the second-order intermodulation signal generated by the first-order difference frequency signal f3-f2 passing through the first amplifier 21, and Z (ω) is the impedance of the power supply terminal of the first amplifier 21.
The power supply ripple V (ω) shown in the above formula (1) affects not only the power supply of the first amplifier 21, but also the power supplies of the second circuit unit 23 and the third circuit unit 24 connected to the power supply network 3 are affected by the ripple as shown in the formula (1).
Similarly, each of the other circuit units also generates ripple, which affects the ripple of the entire power network. If the ripple amplitude is too large on the power supply network 3, the linearity of the amplifiers such as the amplifier is affected, and the linearity mainly comprises the third-order intermodulation distortion and the adjacent channel leakage ratio, so that adverse effects such as signal distortion and the like are caused.
As can be seen from equation (1), two factors affecting the ripple of the power supply are current and impedance, respectively. The magnitude of the current value depends on the input signal, i.e., I (f 3-f 2) in equation (1) cannot be artificially changed, so that the interference of the power supply ripple can be reduced only by artificially adjusting Z (ω) to be small. Then, in order to be able to adjust Z (ω), it is first necessary to know what the current Z (ω) is.
In order to truly reflect the relation between the impedance of the power supply terminal of the amplifier and the frequency ω, the present application proposes a test circuit diagram as shown in fig. 3a, for measuring the frequency response of the power supply impedance of the amplifier.
As previously described, the ripple at the power supply terminal of an amplifier is affected by other devices connected to the same power supply network. Shown in fig. 3a is a test circuit for the first amplifier 21. The first amplifier 21 is an element in an integrated chip, and an input terminal, an output terminal and a power supply terminal of the first amplifier 21 are all connected to pins of the integrated chip. The network analyzer 31, the direct current source 32, the signal source 33 and the spectrometer 34 can be connected with the first amplifier 21 through pins of the chip without damaging the package of the integrated chip.
Wherein the dc source 32 provides a dc voltage source for the entire circuit; the signal source 33 outputs a single-tone signal with frequency f1 for simulating real signal input; the spectrometer 34 measures the power spectrum of the output signal at the output of the first amplifier 21, based on p=i 2 The power calculation formula of R shows that the power and the impedance also have the corresponding relation as shown in formula (1), and the change of the power supply impedance with the frequency can be qualitatively reflected by the power. That is, it can pass through the spectrumThe magnitude of the power measured by the meter 34 varies with the frequency of the signal to indicate whether the power supply impedance has increased or decreased as the frequency varies.
The network analyzer 31 is configured to provide the second amplifier 22 with a binaural signal having a second signal and a third signal, wherein the second signal has a frequency f2 and the third signal has a frequency f3. The difference frequency of the second signal and the third signal is used to simulate the interfering signal of the first amplifier 21. Specifically, after passing through the second amplifier 22, the dual tone signal generates a step-difference signal f3-f2 at its power supply terminal, which is an interference signal that can be coupled to the power supply terminal J of the first amplifier 21 through a common power supply network. This is an unexpected signal, but as described above, the difference frequency signal f3-f2 cannot be filtered out, so when there is an input signal with frequency f1 at the input of the first amplifier 21, the first amplifier 21 mixes the two signals, and there will be an unfiltered intermodulation component f1± (f 3-f 2) at the output. This is also an interference signal, but it shows the frequency response characteristic of the interference signal (first order difference signal) coupled in from the power supply terminal J to some extent. By combining the formula (1), the relation between the power supply end impedance Z (omega) and the frequency can be qualitatively deduced from the envelope shape of the intermodulation component f1+/(f 3-f 2). That is, the fluctuation of the envelope corresponds to the magnitude of the power source terminal impedance Z (ω), and the higher the envelope, the larger the power source terminal impedance Z (ω) and the lower the envelope, the smaller the power source terminal impedance Z (ω).
The spectrum analyzer 34, in addition to the single-tone signal of frequency f1 and its harmonics, also includes intermodulation components f1± (f 3-f 2) of the single-tone signal of frequency f1 and the variable interference signal of frequency f3-f2, in the signal power spectrum measured at the output of the first amplifier 21.
Fig. 4a shows the measured waveform (waveform within the operating bandwidth) of a portion of the signal at this output. Fig. 4b shows a simulation of the power supply side impedance amplitude.
Fig. 4a is a power spectrum image of the output of the first amplifier 21 actually measured in the circuit diagram shown in fig. 3 a. The middle spike (peak P) is a single tone signal (frequency f 1), and the second signal and the third signal (i.e., the two tone signal) are on both sides of the single tone signal, and the intermodulation component (frequency f1± (f 3-f 2)) of the single tone signal. As is clear from an examination of the envelope in the figure, the power supply impedance of the first amplifier 21 increases with a change in frequency. Subsequently, when adjusting the power supply impedance of the amplifier, the adjustment can be performed according to the envelope. For example, the power supply impedance may be adjusted such that the envelope magnitude of the P-point location in the graph decreases.
Fig. 4b is a power supply terminal impedance magnitude simulation diagram of the first amplifier 21 and the second amplifier 22 in the circuit diagram shown in fig. 3 a. Wherein Zin1 and Zin2 are the power supply terminal impedance magnitudes of 2.5v and 1.8v of the first amplifier 21. After the P points of fig. 4a and fig. 4b are aligned, the magnitudes of the measured graph and the simulated graph at the same frequency point always correspond to each other for comparison, that is, the positions of the peaks and the troughs in fig. 4a are close to the frequencies of the positions of the peaks and the troughs in fig. 4 b. Thus, the waveform of fig. 4b can be deduced from the waveform of fig. 4a, i.e. the change of the impedance curve of the power supply side of the amplifier can be deduced from the frequency response curve of the output side of the amplifier.
It is worth noting that by observing the envelope shown in fig. 4a, it is possible to correspond to whether the impedance value of the power supply impedance at each frequency point is large or small, but a specific value of the impedance cannot be intuitively observed. That is, with the present embodiment, it is possible to qualitatively know whether the power supply impedance is relatively large or small, but the true value of the impedance cannot be quantitatively known.
The specific test method is described further below on the basis of fig. 3 a. Fig. 5 shows a flow chart for measuring the frequency response of the power supply impedance (relative impedance) of the active device.
S51, the enabling end of the chip is opened through a control signal of the chip, so that an amplifier in the chip is in a working state. For example, both the first amplifier 21 and the second amplifier 22 shown in fig. 3a start to operate.
S52, inputting a single-tone signal with frequency f1 to the input terminal of the amplifier under test, i.e. the first amplifier 21. In some embodiments, the single tone signal with frequency f1 may be directly input to the input of the first amplifier 21 through the signal source 33. Wherein the frequency of the tone signal may be selected to be within the operating bandwidth.
S53, inputting a diphone signal to the input end of the amplifier for testing. In some embodiments, the test amplifier is the second amplifier 22 of fig. 3a, and after mixing the duplex signal by the second amplifier 22, a variable interference signal (power supply ripple) with a frequency f3-f2 (generated by the duplex signal) is generated at the power supply terminal. The variable interference signal is coupled to the power supply terminal of the first amplifier 21 through a power supply network, forming a power supply ripple at the power supply terminal of the first amplifier 21. In other embodiments, the test amplifier may also be the first amplifier 21 in fig. 5, which will be described later, and the duplex signal is mixed by the first amplifier 21 itself, and the power supply ripple is directly generated at the power supply terminal of the first amplifier 21 (i.e., the power supply terminal of the first amplifier).
In particular implementations, the binaural signal may be provided by the network analyzer 31. The variable interference signal with the frequency f3-f2 can be obtained from the difference frequency signal of the two-tone signals f2 and f3, and the frequency of the intermodulation signal and the harmonic wave generated by the frequencies f2 and f3 do not fall within the above-mentioned communication bandwidth fb, while the variable interference signal f3-f2 is limited within the above-mentioned communication bandwidth fb.
S54, measuring a frequency response curve of an output end of the amplifier to be measured.
First, the network analyzer 31 is started, and a variable interference signal is input frequency by frequency point, wherein the interference signal satisfies the following conditions:
where fb is the communication bandwidth; f1 is the frequency of the input signal of the first amplifier 21, and is also the center frequency of fb; f2 and f3 are the frequencies of the input signals of the second amplifier 22.
Specifically, the input of the variable interference signal on a point-by-point basis includes increasing gradually to fb from f3-f2 equal to 0. I.e. to scan for the ripple that will be generated by the variable interference signal over the entire communication bandwidth fb. Of course, only a part of the frequencies (frequency difference f3-f 2) may be scanned according to the actual test requirements.
While sweeping the frequency, the output frequency-power curve of the first amplifier 21 is observed on the spectrometer 34. The power level of each frequency can be seen clearly, and the magnitude of the amplitude on the frequency-power curve can be used to indicate the magnitude of the power supply terminal impedance, based on the premise that the current of the output signal is constant. But as previously mentioned, the relative magnitude of the power supply terminal impedance is indicated rather than the actual value.
Further, to facilitate viewing the envelope of the frequency-power curve, the maximum envelope of the frequency-power curve may be fixed using the max hold function of spectrometer 34, thereby preserving the scan results.
Finally, the relation between the impedance of the power supply terminal of the first amplifier 21 and the frequency can be analyzed point by point according to the maximum envelope curve of the stored frequency-power curve, and based on the envelope curve, it is determined how to adjust the inductance and capacitance (including parasitic inductance and induced inductance and capacitance) of the power supply terminal of the first amplifier 21 in the subsequent work, so as to improve the power supply ripple resistance of the integrated chip (especially the amplifier therein).
In connection with the previous description of fig. 4a and 4b, it will be appreciated by those skilled in the art that the qualitative determination based on the saved frequency response curve is the relative power supply impedance of the power supply terminal of the first amplifier 21, i.e. the power supply impedance of the amplifier is relative to the magnitude of the output signal power at the same frequency point, and not the actual value of the power supply impedance.
It should be noted that, although the above embodiment uses a spectrometer to measure the output power of the signal, those skilled in the art can also use other meters to measure the voltage amplitude of the output signal at the output end, and the two test methods have the same effect, so that the relative magnitude of the impedance of the power supply end can be qualitatively determined.
The reliability of the impedance of the power supply terminal of the first amplifier 21 is indicated by measuring the frequency-power curve of the output terminal of the first amplifier 21, which will be described below by a circuit analysis of the first amplifier 21 and the second amplifier 22.
Taking the first amplifier 21 and the second amplifier 22 as common source transistors as an example, based on the measurement circuit shown in fig. 3a, the source drain current Ids of the second amplifier 22 is as follows:
where μ is mobility, cox is gate oxide capacitance, W is gate width, L is gate length, VT is threshold voltage, v (f 3) +v (f 2) is Vgs, i.e., increasing the voltage on the gate. A isAmplitude value at B is +.>Amplitude value at C isAmplitude values at. The first line in equation (2) is expanded in taylor series, and the same-class terms are combined to obtain the sum of the components shown in the second line. Since the components of the high frequency part are filtered out by the decoupling capacitor C0, the current leaking from the second amplifier 22 to the first amplifier 21 only comprises the component +.>。
Since the supply ripple on the first amplifier 21 is formed by the transimpedance ZJ between the second amplifier 22 to the first amplifier 21, as shown in fig. 3 b. In the impedance equivalent diagram of the point J in fig. 3a, zloft is the parasitic reactance of the first amplifier 21 except for the transimpedance ZJ; zrig is the parasitic reactance of the second amplifier 22 except for the transimpedance ZJ, and therefore the impedance seen at point J is as follows:
therefore, the power supply ripple of the second amplifier 22 leaked to the first amplifier 21 is as follows:
the power supply ripple will be transferred through the power supply network, thereby affecting the output of the first amplifier 21, considering the channel length modulation effect of the first amplifier 21, the output current of the first amplifier 21 is as follows:
wherein, the liquid crystal display device comprises a liquid crystal display device,VDD is the supply voltage for the channel length modulation factor.
The components through the first amplifier 21 can be determined from the communication bandwidth fb as:it is decomposed into:
formula (6)
Where ZL (ω) is the load impedance of the first amplifier 21 and A isAmplitude value at B isAmplitude value at C is +.>Amplitude values at. For parasitic inductance and capacitance, the impedance corresponding to different frequencies is different, so the frequency response in the frequency spectrum is different, and the output power of the first amplifier 21 is:
wherein onlyAnd->In the test range, other harmonics and higher order intermodulation products are not in the test range. In combination with the frequency-power curve shown in fig. 4a, in +.>On both sidesFrequency band (wherein->The frequency response of the range of 0-fb) can be used to describe the relative impedance value of the power supply terminal, which has guiding significance for the circuit design inside the integrated chip, especially the design of the power supply terminal.
The above embodiments illustrate how the power supply terminal impedance can be qualitatively measured when other amplifiers in the same power supply network have an effect on the power supply ripple. Fig. 6 shows a circuit diagram of measuring the impedance of the power supply terminals without the influence of other amplifiers in the same power supply network on the supply ripple.
As shown in the figure, the dc source 32, the signal source 33 and the spectrometer 34 are arranged in the same manner as shown in fig. 3a, and the functions thereof are the same; only the network analyzer 31 for generating the interference signal (variable interference signal with frequencies f2 and f 3) instead inputs the signal to the input of the first amplifier 21, i.e. the input of the first amplifier 21 is superimposed with both the single tone signal and the variable interference signal. That is, the variable interference signal is used to directly simulate the power supply ripple in the present embodiment. In this case, the frequency-power response curve with center frequency f1 and bandwidth fb is observed at the output by means of spectrometer 34, which achieves the same effect as in the embodiment shown in fig. 2.
Taking a common source transistor as an example of the first amplifier 21, the configuration of the voltage at the output terminal of the first amplifier 21 is analyzed to illustrate that measuring the power or the voltage at the output terminal can reflect the relative magnitude of the impedance of the power supply terminal, so that the design and the debugging of each power supply terminal inside the integrated chip can be guided.
First, the calculation formula of the source drain current Ids of the common source transistor is as follows:
where μ is mobility, cox is gate oxide capacitance, W is gate width, L is gate length, VT is threshold voltage, v (f 3) +v (f 2) +v (f 1) is Vgs, i.e., increasing the voltage on the gate. Performing series expansion on the formula (8), and combining the similar items to obtain the following steps:
formula (9)
Wherein A isAmplitude value at B is +.>Amplitude values at. In the formula (9) of the present invention,the current generated for the fundamental wave (single tone signal),currents generated for the third-order intermodulation signals of the fundamental wave and the variable interference signal. In addition, for simplicity of the formula, other intermodulation signals and variable interference signals (frequencies f2, f 3) outside the operating frequency band and harmonic components thereof and harmonic components of f1 are omitted in the formula (3).
The power Pout at the output of the first amplifier 21 is according to equation (9):
formula (10)
Wherein, the liquid crystal display device comprises a liquid crystal display device,ZL (ω) is the load impedance. As can be seen from equation (4), the frequency-power curve contains the fundamental component and also containsIs a frequency component of (a) a frequency component of (b). Based on->Is a frequency component varying in the range 0-fb, thus, at +.>The frequency-power curve of the frequency band can be used to describe the relative value of the impedance on the power supply, that is, the magnitude of the impedance of the power supply end can be described by the formula (4).
It should be noted that numerous specific details are provided in the description provided herein. However, it is understood that embodiments of the present application may be practiced without some or all of these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, in the above description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and arranged in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
Claims (11)
1. A method for testing the frequency response of a power supply impedance, which is applied to a chip comprising an amplifier, comprising:
enabling an amplifier for testing in the chip to be in a working state;
inputting a first signal with the frequency f1 to the input end of the amplifier to be tested;
inputting an analog power supply interference signal to an input end of the amplifier for testing;
measuring a signal to be measured of an output end of an amplifier inputting a first signal f1, and obtaining a frequency response curve of an output signal taking the first signal f1 as a center frequency;
and qualitatively judging the relative power supply impedance of the amplifier according to the frequency response curve.
2. The method of claim 1, wherein the step of inputting an analog power supply disturbance signal to a power supply terminal of the amplifier under test comprises:
and inputting a double-tone signal with a second signal and a third signal to a power supply end of the amplifier to be tested, wherein the frequency f2 of the second signal and the frequency f3 of the third signal fall outside a test frequency band at two sides of the first signal f1, and the difference value of the second signal and the third signal is used for simulating the power supply interference signal.
3. The method of claim 2, wherein the first signal f1 and the binaural signal are coupled in through an input of the same amplifier.
4. The method of claim 2, wherein the first signal f1 is input to one amplifier and the binaural signal is input to another amplifier.
5. A method according to any one of claims 1-3, characterized in that the first signal f1 is input by means of a signal source.
6. A method according to any one of claims 2-3, wherein the diphone signal is input by a network analyzer.
7. The method of claim 1, wherein the power supply terminal of the amplifier is provided with a decoupling capacitor for filtering out harmonics of the second and more times and higher order intermodulation signals having frequencies greater than the second harmonic.
8. The method of claim 1, wherein the signal under test is tested using a spectrometer and the frequency response curve is recorded.
9. The method of claim 7, wherein the chip comprises a chip integrated with a single-stage amplifier or a multi-stage amplifier or the chip is a radio frequency transceiver chip.
10. A method as claimed in any one of claims 2-3, characterized in that the frequency difference f3-f2 of the two-tone signal is swept from zero when the frequency response curve of the output signal centered on the first signal f1 is acquired.
11. The method of claim 9, wherein the frequency response curve is a frequency versus voltage curve or a frequency versus power curve.
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