CN116094524A - Fully synthesizable time domain analog to digital converter - Google Patents

Fully synthesizable time domain analog to digital converter Download PDF

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CN116094524A
CN116094524A CN202310136235.2A CN202310136235A CN116094524A CN 116094524 A CN116094524 A CN 116094524A CN 202310136235 A CN202310136235 A CN 202310136235A CN 116094524 A CN116094524 A CN 116094524A
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time
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voltage
digital converter
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金晶
黄裕炜
过悦康
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Shanghai Jiaotong University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/38—Circuit design at the mixed level of analogue and digital signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

A fully synthesizable time domain analog to digital converter comprising: the sampling hold circuit, the voltage time conversion circuit and the time digital conversion circuit are connected in sequence, wherein: the sampling hold circuit converts the continuous-time voltage signal into a discrete-time voltage signal and outputs the discrete-time voltage signal to the voltage-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering the capacitor unit and outputs the START signal and the STOP signal to the time-to-digital converter; the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, and realizes conversion of an analog voltage signal into the digital signal. The invention builds a fully-integrated sampling hold circuit, a voltage-time conversion circuit and a time-digital conversion circuit through the basic digital logic unit, and forms the ADC, and uses the HDLs language to complete the description of the ADC, and utilizes the digital circuit design tool to conveniently complete the design flows of simulation, synthesis, layout, wiring and the like, thereby simplifying the design of the ADC.

Description

Fully synthesizable time domain analog to digital converter
Technical Field
The invention relates to the field of analog-to-digital converters, in particular to a fully synthesizable time domain analog-to-digital converter (ADC).
Background
The traditional ADC frame adopts the design thought and the design flow of an analog circuit, and under the condition that the CMOS devices are continuously miniaturized nowadays, the problems of increasingly complex circuit design, circuit verification and layout are faced. The analog circuit is digitalized, and the analog circuit built by the basic digital logic unit can automatically and conveniently complete the design processes of simulation, synthesis, layout, wiring and the like by using the design tool of the digital circuit, so that the design process of the analog circuit is greatly simplified, the design period is shortened, and the analog circuit is more suitable for the background of continuous and advanced technology at present. In addition, the ever decreasing supply voltage to achieve smaller power consumption also presents challenges to the design of conventional ADCs, such as: precision, etc., making it more difficult for conventional ADCs to meet increasingly stringent performance specifications. The processing of the time domain signal benefits from the advanced process and the drop in supply voltage. The time domain signal is represented as an analog signal by the time difference between two digital events, such as the time interval between rising edges. The time domain ADC may take the time signal as a transition, first converting the analog voltage signal into the time signal by a voltage-to-time converter (VTC), and then converting the time signal into a digital signal in a time-to-digital converter (TDC).
Disclosure of Invention
Aiming at the complex flow of continuous simulation, layout and wiring and the like of the existing analog-digital conversion circuit, the invention provides a fully-synthesizable time domain analog-digital converter, a fully-synthesizable sample-hold circuit is built through a basic digital logic unit, a voltage-time conversion circuit and a time-digital conversion circuit form an ADC, the ADC is completely described by using an HDLs language, and the design flow of simulation, synthesis, layout and wiring and the like is conveniently completed by using a digital circuit design tool, so that the design of the ADC is simplified.
The invention is realized by the following technical scheme:
the invention relates to a fully synthesizable time domain analog-to-digital converter comprising: the sampling hold circuit, the voltage time conversion circuit and the time digital conversion circuit are connected in sequence, wherein: the sampling hold circuit converts the continuous-time voltage signal into a discrete-time voltage signal and outputs the discrete-time voltage signal to the voltage-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering the capacitor unit and outputs the START signal and the STOP signal to the time-to-digital converter; the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, and realizes conversion of an analog voltage signal into the digital signal.
The sample-and-hold circuit is composed of two identical sample-and-hold sub-circuits, each comprising: sampling capacitance unit, shrink capacitance unit, first transmission gate and second transmission gate, wherein: two ends of the first transmission gate are respectively connected with the input signal and the sampling capacitance unit, and two ends of the second transmission gate are respectively connected with the sampling capacitance unit and the shrinkage capacitance unit.
The voltage time conversion circuit includes: a clocked comparator, two inverter arrays, two nor gates, two buffers, an and gate, and an or gate, wherein: the clock control comparator compares discrete time voltage signals output by the sampling hold circuit and outputs a comparison result, namely a sign signal to the time digital converter, the output ends of the first inverter array and the second inverter array are respectively connected with one input end of a corresponding NOR gate, the other input end of the first inverter array and the second inverter array receives an inverted clock signal, the output ends of two NOR gates and the output end of the corresponding sampling hold circuit are correspondingly connected with the first buffer and the second buffer, the logic or result output by the two buffers is used as a START signal, and the logic and result is used as a STOP signal.
Preferably, the control signal sum, which is adjusted as needed, is input to the inverter array sum, respectively.
The time-to-digital converter adopts a vernier type delay chain structure, and comprises: two delay chains which are arranged in parallel and are formed by serially connecting buffers, and a multistage clocking comparator and an encoder which are arranged between the two delay chains, wherein: the first delay chain and the second delay chain respectively receive a START signal and a STOP signal, the clock-controlled comparator respectively compares the speed of rising edge signals at corresponding positions in the two delay chains and outputs a temperature code, the non-inverting input end of the clock-controlled comparator is connected with the node of the first delay chain, the inverting input end of the clock-controlled comparator is connected with the node of the second delay chain, and the encoder converts the temperature code into a binary digital signal according to a symbol signal from the voltage-time conversion circuit.
Drawings
FIG. 1 is a circuit block diagram of the present invention;
FIG. 2 is a schematic diagram of a sample-and-hold circuit and a voltage-to-time conversion circuit according to the present invention;
FIG. 3 is a timing diagram of the voltage to time conversion circuit according to the present invention;
FIG. 4 is a schematic diagram showing a detailed structure of a charging path of the voltage-to-time conversion circuit according to the present invention;
FIG. 5 is a schematic diagram of a two-input NAND gate design capacitor according to the present invention;
FIG. 6 is a schematic diagram of a time to digital conversion circuit according to the present invention;
FIG. 7 is a schematic diagram of a delay chain signal transmission in a time-to-digital conversion circuit according to the present invention;
FIG. 8 is a schematic diagram of a manner of extending buffer latency;
fig. 9 is a schematic diagram of a comprehensively clocked comparator circuit.
Detailed Description
As shown in fig. 1, this embodiment relates to a fully synthesizable time domain analog-to-digital converter, which includes: the sampling hold circuit, the voltage time conversion circuit and the time digital conversion circuit are connected in sequence, wherein: the sampling hold circuit converts the continuous-time voltage signal into a discrete-time voltage signal as the input of the voltage-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering the capacitor unit and outputs the START signal and the STOP signal to the time-to-digital converter; the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, and realizes conversion of an analog voltage signal into the digital signal.
As shown in fig. 2, the sample-and-hold circuit includes: sampling capacitor unit C 1P And C 1N Shrink capacitor unit C 2P And C 2N Transmission gate S 1P 、S 1N 、S 2P And S is 2N Wherein: positive input terminal, first transmission gate S 1P Two ends of the sampling capacitor unit C are respectively connected with the normal phase input signal VINP and the sampling capacitor unit 1P Connection, second transmission gate S 2P Respectively with the sampling capacitance unit C at both ends 1P And a shrink capacitance unit C 2P And (5) connection. Sampling capacitor unit C 1P Sampling the normal phase input signal VINP and comparing with the shrink capacitance unit C 2P And the charge sharing is carried out to realize shrinkage sampling, and the input range of the whole circuit can be enlarged by shrinkage sampling. The connection mode and circuit principle of the inverting input terminal circuit are consistent with those of the non-inverting input terminal circuit.
The two sampling capacitance units and the two shrinkage capacitance units are realized by using a NAND gate with one input end grounded and the output end suspended, and the gate capacitances of the POMS and the NMOS are used as capacitances, as shown in figure 5.
The four transmission gates are controlled by clock signals to be turned on and turned off.
As shown in fig. 2, the voltage-to-time conversion circuit includes: a clocked comparator CMP, two inverter arrays inv_arrap_p AND inv_arrap_n, two NOR gates nor_p AND nor_n, two buffers buf_p AND buf_n, one AND gate AND one OR gate OR, wherein: the clocked comparator CMP compares the discrete-time voltage signal V output by the sample-and-hold circuit XP And V XN And outputs the comparison result as an encoder control signal SIGN of the time-to-digital converter; the output terminals of the first and second inverter arrays are respectively connected to one input terminal of the corresponding NOR gate, and the other input terminal thereof receives the inverted clock signal
Figure BDA0004085707920000031
The outputs of the two NOR gates nor_p and nor_n and the outputs of the corresponding sample-and-hold circuits are correspondingly connected to the first and second buffers buf_p and buf_n, the logical or result of the outputs of the two buffers being the START signal and the logical and result being the STOP signal.
The clock comparator CMP is controlled by the clock signal CLK, and when the clock signal CLK is high, the voltage of the sample-and-hold circuit is set to V XP And V XN The output sign signal is compared as a control signal for the encoder ENC in the time-to-digital converter, determining the sign of the output.
The pull-up path of the nor gate is two PMOS transistors forming a cascade structure, and is used as a charging path to charge the sampling capacitor unit and the shrinkage capacitor unit, so that a better constant current effect can be achieved, as shown in fig. 4. FIG. 4 shows a NOR gate at the non-inverting input circuit, the output of which is connected to V XP ，V XP The two PMOS tubes above form a cascades structure, which can be connected with V during charging XP Is a sampling capacitance unit C of (1) 1P Shrink capacitor unit C 2P Providing a more constant charging current. The inverting input circuit is the same.
As shown in fig. 4, the whole inverter ARRAY inv_array_p is composed of a certain number of inverters, the outputs of the inverters are all connected to the input end of the PMOS transistor of the NOR gate nor_p close to VDD, the inputs are independent, and the control signal ctrl_p is a multi-bit signal, so that the input of each inverter can be controlled independently. The inverting input circuit is the same.
As shown in fig. 6, the time-to-digital converter adopts a vernier type delay chain structure, which comprises: two delay chains buf1_1, buf1_4, buf2_1, buf2_4, a multi-stage clocked comparator CMP1, CMP4, and an encoder ENC arranged in parallel and composed of buffers in series, wherein: the first delay chain and the second delay chain respectively receive a START signal and a STOP signal, the clock-controlled comparator respectively compares the speed of rising edge signals at corresponding positions in the two delay chains and outputs a temperature code, the non-inverting input end of the clock-controlled comparator is connected with the node of the first delay chain, the inverting input end of the clock-controlled comparator is connected with the node of the second delay chain, and the encoder ENC converts the temperature code into a binary digital signal according to a symbol signal from the voltage-to-time converter.
As shown in fig. 2, the first switch S is in a sampling state when CLK is low 1P /S 1N Is communicated with a second switch S 2P /S 2N Disconnected by sampling capacitor unit C 1P /C 1N Sampling VINP/VINN, and simultaneously conducting the pull-down network of two NOR gates to enable the capacitor unit C to be contracted 2P /C 2N Fully discharging; when (when)When CLK is high, the first switch S 1P /S 1N Open, second switch S 2P /S 2N Communication, sampling capacitance unit C 1P /C 1N Charge on and shrink capacitance unit C 2P /C 2N Sharing, so that V XP /V XN The voltage of the node rises rapidly to V XP0 /V XN0 Realizing shrinkage sampling; the pull-up network of the two NOR gates is conducted, at V XP0 /V XN0 Based on the voltage, the capacitor unit C is connected with a constant current 1P /C 1N And C 2P /C 2N Charging to make node V XP /V XN The voltage of (2) continues to rise linearly. The outputs of the two nor gates are passed through the subsequent buffers buf_p/buf_n to produce the more ideal rising edge signal, AND then through AND OR gates OR to extract the fast rising edge signal as START signal AND the slow rising edge signal as STOP signal as input to the time-to-digital comparator. The timing diagram of the voltage-to-time converter is shown in FIG. 3, V TP /V TN Is the ideal rising edge signal obtained after the buffer. The START and STOP signals are delayed step by step in the first delay chain and the second delay chain, respectively. And judging the speed between rising edges of corresponding nodes in the two delay chains by using a clocked comparator, and outputting 1 by the clocked comparator when the rising edge signal output by the buffer in the first delay chain is faster than the rising edge signal output by the corresponding buffer in the second delay chain, otherwise outputting 0. A schematic diagram of delay chain signaling in a time-to-digital comparator is shown in fig. 7. In the first delay chain, the delay of each buffer is t d1 In the second delay chain, the delay of each buffer is t d2 . If the time difference between the START and STOP signals is within the input range of the time-to-digital comparator, due to t d1 ＞t d2 The delayed signal of STOP will lead the delayed signal of START. Assuming that the delay signal of STOP just precedes the delay signal of START after the delay through n buffers, the measured value t=nx (T d1 -t d2 ) The first n outputs of the clocked comparator set are 1 and the subsequent output is 0, resulting in a temperature code. At the same time, can be obtained, the time-to-digital conversionResolution T of the device LSB At t d1 -t d2 . The encoder ENC judges the sign of the output signal according to the sign signal, and encodes the temperature code into a corresponding binary code.
The complementary transmission gate, NAND gate, NOR gate, etc. are implemented by, but not limited to, CMOS.
As shown in FIG. 4, the inverters in the inverter array have a partial input of 0, an open NMOS transistor and a closed NMOS transistor, and the other partial input of 1, an open NMOS transistor and a closed PMOS transistor, and form a comparison circuit, which is the same as the principle of resistor voltage division, and thus generates a voltage V B ，0＜V B < VDD. The gate voltage of PM1 is not directly low 0 but V B (V B > 0) is controlled to ensure that both PM1 and PM2 are in a saturation region in the charging process, and the cascades current source formed by the cascades current source has larger output impedance so as to achieve a better constant charging current effect. In addition, the voltage V can be regulated by CTRL_P in the case of PVT variations B The charging current is controlled to cope with the change of PVT. It should be noted that the voltage V B Should not be higher than the threshold voltage of the NM1 tube, avoiding discharging while charging. The inverting input circuit is the same.
In the time-to-digital converter, in the first delay chain, the delay of each buffer is t d1 In the second delay chain, the delay of each buffer is t d2 There is a need of t d1 ＞t d2 . T may be achieved by bypassing an additional buffer d1 ＞t d2 . As shown in fig. 8, an output-suspended buffer is bypassed at the output node of each buffer in the first delay chain. The bypass buffer will increase the output capacitance of the previous stage buffer, thereby increasing the delay. In this way, the size of all buffers in the time-to-digital converter can be the same.
As shown in fig. 9, the clocked comparator is implemented by a dynamic circuit in this embodiment, and includes: the two NAND3 gates, the two inverters and the latch are connected in sequence, when CLK is at a low level, the comparator is in a reset state, the output nodes of the two NAND3 gates are precharged to 1, two outputs of the latch are both 0, when CLK is at a high level, the comparator is in an evaluation state, and a truth table of the comparator is as follows:
Figure BDA0004085707920000051
the input stage of the NAND3 gate changes the voltage of the output node according to VINP and VINN: when VINP is 1 and vinn is 0, the input stage of the NAND3 gate discharges the pout_nand3 node to 0 through positive feedback, the nout_nand3 node remains 1, after passing through the inverter, the output Q of the latch is 1 and qn is 0; conversely, Q is 0, and QN is 1; when VINP and VINN are both 0 or 1, the clocked comparator can maintain the original output, ensure the encoder ENC finishes encoding, and output the corresponding digital signal. In the structures shown in fig. 2 and 6, the output terminals of all clocked comparators are Q and QN in fig. 9, and are not suspended.
The foregoing embodiments may be partially modified in numerous ways by those skilled in the art without departing from the principles and spirit of the invention, the scope of which is defined in the claims and not by the foregoing embodiments, and all such implementations are within the scope of the invention.

Claims (9)

1. A fully synthesizable time domain analog to digital converter comprising: the sampling hold circuit, the voltage time conversion circuit and the time digital conversion circuit are connected in sequence, wherein: the sampling hold circuit converts the continuous-time voltage signal into a discrete-time voltage signal and outputs the discrete-time voltage signal to the voltage-time converter; the voltage-to-time converter generates a START signal and a STOP signal by charging and buffering the capacitor unit and outputs the START signal and the STOP signal to the time-to-digital converter; the time-to-digital converter outputs a digital signal according to the START signal and the STOP signal, and realizes conversion of an analog voltage signal into the digital signal.
2. The fully synthesizable time-domain analog-to-digital converter of claim 1 wherein said sample-and-hold circuit is comprised of two identical sample-and-hold sub-circuits, each comprising: sampling capacitance unit, shrink capacitance unit, first transmission gate and second transmission gate, wherein: two ends of the first transmission gate are respectively connected with the input signal and the sampling capacitance unit, and two ends of the second transmission gate are respectively connected with the sampling capacitance unit and the shrinkage capacitance unit.
3. The fully synthesizable time domain analog-to-digital converter of claim 2 wherein the two sampling capacitor units and the two shrink capacitor units are implemented using a nand gate with one input terminal grounded and a floating output terminal, and using the gate capacitances of POMS and NMOS as the capacitances.
4. The fully synthesizable time domain analog to digital converter of claim 1 wherein said voltage to time conversion circuit comprises: a clocked comparator, two inverter arrays, two nor gates, two buffers, an and gate, and an or gate, wherein: the clock control comparator compares discrete time voltage signals output by the sampling hold circuit and outputs a comparison result, namely a sign signal to the time digital converter, the output ends of the first inverter array and the second inverter array are respectively connected with one input end of a corresponding NOR gate, the other input end of the first inverter array and the second inverter array receives an inverted clock signal, the output ends of two NOR gates and the output end of the corresponding sampling hold circuit are correspondingly connected with the first buffer and the second buffer, the logic or result output by the two buffers is used as a START signal, and the logic and result is used as a STOP signal.
5. The fully synthesizable time domain analog to digital converter of claim 4 wherein the control signals adjusted as needed are input to the two inverter arrays, respectively.
6. The fully-synthesizable time-domain analog-to-digital converter of claim 4 wherein the clocked comparator is clocked by the clock signal, and compares the output of the sample-and-hold circuit when the clock signal is high, the output sign signal is used as a control signal for the encoder ENC in the time-to-digital converter to determine the sign of the output, i.e., the sign signal.
7. The fully-synthesizable time-domain analog-to-digital converter of claim 4 wherein the pull-up path of the nor gate is two PMOS transistors forming a cascades structure, as a charging path, for charging the sampling capacitor unit and the shrink capacitor unit.
8. The fully-synthesizable time-domain analog-to-digital converter of claim 4 wherein the entire array of inverters comprises inverters, the output of each inverter being connected to the input of the PMOS transistor of the corresponding nor gate near VDD, the control signal ctrl_p or ctrl_n being a multi-bit signal for individual control of the input of each inverter.
9. The fully synthesizable time domain analog-to-digital converter of claim 1 wherein said time-to-digital converter employs a vernier delay chain structure comprising: two delay chains which are arranged in parallel and are formed by serially connecting buffers, and a multistage clocking comparator and an encoder which are arranged between the two delay chains, wherein: the first delay chain and the second delay chain respectively receive a START signal and a STOP signal, the clock-controlled comparator respectively compares the speed of rising edge signals at corresponding positions in the two delay chains and outputs a temperature code, the non-inverting input end of the clock-controlled comparator is connected with the node of the first delay chain, the inverting input end of the clock-controlled comparator is connected with the node of the second delay chain, and the encoder converts the temperature code into a binary digital signal according to a symbol signal from the voltage-to-time converter.
CN202310136235.2A 2023-02-20 2023-02-20 Fully synthesizable time domain analog to digital converter Pending CN116094524A (en)

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