CN116093746A

CN116093746A - VCSEL chip and preparation method thereof

Info

Publication number: CN116093746A
Application number: CN202111323399.3A
Authority: CN
Inventors: 郭铭浩; 周圣凯; 赖威廷; 王立; 李念宜
Original assignee: Zhejiang Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co ltd
Priority date: 2021-11-08
Filing date: 2021-11-08
Publication date: 2023-05-09

Abstract

Disclosed are a VCSEL chip and a method for manufacturing the same, wherein the VCSEL chip includes: a plurality of VCSEL light emitting cells electrically isolated from each other and a plurality of light modulating elements integrally provided to the plurality of VCSEL light emitting cells at a wafer level. Each of the VCSEL light emitting units includes a light emitting body, a positive electrode and a negative electrode electrically connected to the light emitting body, wherein the light emitting body sequentially includes, from bottom to top: a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer, and an N-type electrical contact layer, the confinement layer having a confinement aperture corresponding to the active region. The plurality of light modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is 120 ° or more. In this way, the VCSEL chip can regulate the whole divergence angle through the self structural design of the VCSEL chip so as to enlarge the scanning domain of the VCSEL chip.

Description

VCSEL chip and preparation method thereof

Technical Field

The present application relates to the field of semiconductor lasers, and more particularly to VCSEL chips and methods of making the same.

Background

A VCSEL (Vertical-Cavity Surface Emitting Laser) refers to a semiconductor Laser that forms a resonator in a Vertical direction of a substrate and emits Laser light in the Vertical direction. The VCSEL chip has the characteristics of small temperature drift, low threshold value, high optical fiber coupling efficiency, easy integration and encapsulation and the like, and is widely applied to the fields of intelligent transportation, health care, biological detection, military security and the like.

In the actual industry, VCSEL chips are often used as projection light sources to perform depth measurement of a measured object for three-dimensional modeling, depth mapping, and the like. In some application scenarios, a wide-angle scan is also required to be performed on a measured object to perform large-view modeling on the measured object. For example, when the VCSEL chip is applied as a projection light source of the vehicle-mounted lidar, the application scenario requires that the VCSEL chip has a larger scanning area to collect road condition information more comprehensively to assist the vehicle in implementing functional mechanisms such as route planning and roadblock avoidance. Whereas the conventional VCSEL chip typically has a scan field within 90 °, i.e. it can scan only a relatively narrow region of the object under test.

To overcome this technical difficulty, in a vehicle-mounted lidar, a rotation motor is generally configured for a VCSEL chip to rotate the VCSEL chip by the rotation motor, in such a way that a scanning range is enlarged. However, this solution has a number of drawbacks.

First, the rotational accuracy of the VCSEL chip depends on the structural stability between it and the rotary motor, and the control accuracy of the rotary motor. That is, if the control accuracy of the rotation motor is not good, or if the matching relationship between the VCSEL chip and the rotation motor is changed, this affects the scanning effect of the VCSEL chip.

Secondly, under the action of the rotary motor, the relative position relationship between the VCSEL chip and the measured object is adjusted, and although the scanning domain of the VCSEL chip can be expanded by the mode, the information processing difficulty of the follow-up three-dimensional modeling can be increased due to the fact that the relative position relationship between the VCSEL chip and the measured object is adjusted.

Therefore, an optimized solution is needed to expand the scan domain of the VCSEL chip.

Disclosure of Invention

One advantage of the present application is that it provides a VCSEL chip and a method for manufacturing the same, where the VCSEL chip can regulate its overall divergence angle by its own structural design to expand the scan field of the VCSEL chip, that is, the VCSEL chip according to the embodiments of the present application can realize expansion of its own scan field without an external driver.

Another advantage of the present application is to provide a VCSEL chip and a method of fabricating the same, wherein the VCSEL chip enables the VCSEL chip to be adapted to high-speed circuits by isomerising its own structure.

To achieve at least one of the above or other advantages and objects, according to one aspect of the present application, there is provided a VCSEL chip including:

A plurality of VCSEL light emitting cells electrically isolated from each other, each of the VCSEL light emitting cells comprising a light emitting body, a positive electrode and a negative electrode electrically connected to the light emitting body, wherein the light emitting body comprises, in order from bottom to top: a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer, and an N-type electrical contact layer, the confinement layer having a confinement aperture corresponding to the active region; and

and a plurality of light modulation elements integrally provided to the plurality of VCSEL light emitting units at a wafer level, wherein the plurality of light modulation elements have a preset structural configuration and cooperate with each other so that an overall divergence angle of the VCSEL chips is 120 ° or more.

In the VCSEL chip of the present application, the plurality of light modulation elements have a preset structural configuration and cooperate with each other such that the overall divergence angle of the VCSEL chip is equal to 180 °.

In the VCSEL chip of the present application, the plurality of light modulation elements includes at least one concave lens and at least one convex lens.

In the VCSEL chip of the present application, at least part of the concave lens is disposed on the VCSEL light emitting unit located in an edge region of the VCSEL chip.

In the VCSEL chip of the present application, at least part of the convex lens is disposed on the VCSEL light emitting unit located in a middle region of the VCSEL chip.

In the VCSEL chip of the present application, at least a part of the optical center of the light modulation element is located on the optical axis set by the light emitting body corresponding thereto.

In the VCSEL chip of the present application, at least a part of the optical centers of the light modulation elements deviate from the optical axes set by the light emitting bodies corresponding thereto.

In the VCSEL chip of the present application, at least part of the convex lenses have different curvatures.

In the VCSEL chip of the present application, the substrate layer is made of a P-type semiconductor material.

According to another aspect of the present application, there is provided a method for fabricating a VCSEL chip, comprising:

forming a structure to be processed, wherein the structure to be processed sequentially comprises a substrate structure, a P-type electric contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electric contact structure and a layer to be processed from bottom to top;

processing the layer to be processed through an etching process to form a plurality of light modulation elements above the N-type electric contact structure so as to obtain a chip semi-finished product;

forming a plurality of negative electrodes electrically connected to the N-type electrical contact structure;

removing at least a portion of the chip semi-finished product to form a plurality of sub-structural units electrically isolated from each other, each of the sub-structural units including a P-type electrical contact layer, a P-DBR layer, an active region, an N-DBR layer, and an N-type electrical contact layer from bottom to top;

Processing the plurality of sub-structure units to form a confinement layer having a confinement hole above the active region to form a plurality of light-emitting bodies; and

forming a plurality of positive electrodes electrically connected to the plurality of light emitting bodies, respectively.

In the method for manufacturing a VCSEL chip of the present application, the layer to be processed is processed by an etching process to form a plurality of light modulation elements over the N-type electrical contact structure to obtain a chip semi-finished product, comprising: applying an etchable layer on the layer to be processed; shaping the etchable material through a mask into a template having a preset shape and size, wherein the preset shape and size of the template is consistent with the shape and size of the light modulating element; and removing at least a portion of the template and the layer to be processed by an etching process, wherein the layer to be processed that is retained has a shape and size that is consistent with the template to form the plurality of light modulation elements.

In the method for manufacturing a VCSEL chip of the present application, processing the plurality of sub-structural units to form a confinement layer having a confinement hole over the active region includes: forming a protective layer covering the negative electrode; oxidizing the plurality of substructure units; and exposing the negative electrode.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features, and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings, and the appended claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the invention, taken in conjunction with the accompanying drawings, wherein:

fig. 1 illustrates a schematic diagram of a VCSEL chip according to an embodiment of the present application.

Fig. 2 illustrates a schematic diagram of a single VCSEL light emitting unit of a VCSEL chip according to an embodiment of the present application.

Fig. 3 illustrates a flow chart of a method of fabricating a VCSEL chip according to an embodiment of the present application.

Fig. 4A illustrates one of schematic diagrams of a fabrication process of a VCSEL chip according to an embodiment of the present application.

Fig. 4B illustrates a second schematic diagram of a process for fabricating a VCSEL chip according to an embodiment of the present application.

Fig. 4C illustrates a third schematic diagram of a fabrication process of a VCSEL chip according to an embodiment of the present application.

Detailed Description

The terms and words used in the following description and claims are not limited to literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. It will be apparent to those skilled in the art, therefore, that the following description of the various embodiments of the present application is provided for the purpose of illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.

Although ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, or groups thereof.

Summary of the application

As described above, a VCSEL (Vertical-Cavity Surface Emitting Laser) refers to a semiconductor Laser that forms a resonator in a Vertical direction of a substrate and emits Laser light in the Vertical direction. With the development of VCSEL technology, VCSEL chips are widely applied to the fields of intelligent transportation, health care, biological detection, military security and the like.

In addition, if the real-time monitoring of the surrounding environment is to be realized, the rotating mechanism needs to keep high-frequency rotation and is easy to wear, which has high requirements on the performance of the rotating mechanism, and on the other hand, the working performance of the rotating mechanism is hard to keep stable.

In addition, the laser projection range (i.e., scan field) of the VCSEL light source is enlarged by matching the VCSEL light source with the driving device, which is disadvantageous for miniaturization of the entire apparatus, for example, a large size of the existing lidar apparatus is core because the rotating mechanism occupies a relatively large volume.

Aiming at the technical problems, the technical conception of the application is as follows: the whole divergence angle of the VCSEL chip is regulated and controlled through the self structural design, so that the scanning domain of the VCSEL chip is enlarged, namely, the VCSEL chip according to the embodiment of the application can expand the scanning domain of the VCSEL chip (namely, the laser projection range is expanded) on the premise that an external driver is not needed. Specifically, by configuring light modulation element arrays with different light modulation performances on the emergent paths of a plurality of VCSEL light emitting units of the VCSEL chip, the whole divergence angle of the VCSEL chip is regulated and controlled through the light modulation element arrays, and the scanning domain or the laser projection range of the VCSEL chip is expanded.

Based on this, according to one aspect of the present application, the present application proposes a VCSEL chip comprising: a plurality of VCSEL light emitting cells electrically isolated from each other and a plurality of light modulating elements integrally provided to the plurality of VCSEL light emitting cells at a wafer level. Each of the VCSEL light emitting units includes a light emitting body, a positive electrode and a negative electrode electrically connected to the light emitting body, wherein the light emitting body sequentially includes, from bottom to top: a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer, and an N-type electrical contact layer, the confinement layer having a confinement aperture corresponding to the active region. The plurality of light modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is 120 ° or more.

According to another aspect of the present application, there is provided a method for fabricating a VCSEL chip, comprising: forming a structure to be processed, wherein the structure to be processed sequentially comprises a substrate structure, a P-type electric contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electric contact structure and a layer to be processed from bottom to top; processing the layer to be processed through an etching process to form a plurality of light modulation elements above the N-type electric contact structure so as to obtain a chip semi-finished product; forming a plurality of negative electrodes electrically connected to the N-type electrical contact structure; removing at least a portion of the chip semi-finished product to form a plurality of sub-structural units electrically isolated from each other, each of the sub-structural units including a P-type electrical contact layer, a P-DBR layer, an active region, an N-DBR layer, and an N-type electrical contact layer from bottom to top; processing the plurality of sub-structure units to form a confinement layer having a confinement hole above the active region to form a plurality of light-emitting bodies; and forming a plurality of positive electrodes electrically connected to the plurality of light emitting bodies, respectively.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

Schematic VCSEL chip

As shown in fig. 1 to 2, a VCSEL chip according to an embodiment of the present application is illustrated, wherein the VCSEL chip includes a plurality of VCSEL light emitting cells 10 electrically isolated from each other, and a plurality of light modulation elements 20 integrally provided to the plurality of VCSEL light emitting cells 10 at a wafer level. The plurality of light modulation elements 20 are disposed on the laser emission paths of at least some of the VCSEL light emitting units 10 in the plurality of VCSEL light emitting units 10, so that the light modulation elements 20 can modulate the laser emitted by the VCSEL light emitting units 10 to adjust the light emission characteristics (for example, the laser emission direction and the wavelength of the laser) of the VCSEL light emitting units 10, and the overall divergence angle of the VCSEL chip can be increased by the mutual matching between the plurality of light modulation elements 20, so as to expand the scanning area of the VCSEL chip.

For example, when the laser light generated from the VCSEL light emitting unit 10 is emitted from the top side thereof, the light modulation element 20 is disposed on top of the VCSEL light emitting unit 10 such that the laser light generated from the VCSEL light emitting unit 10 is modulated by the light modulation element 20 after being emitted from the top side of the VCSEL light emitting unit 10. When the laser light generated from the VCSEL light emitting unit 10 is emitted from the bottom side thereof, the light modulation element 20 is disposed at the bottom of the VCSEL light emitting unit 10 such that the laser light generated from the VCSEL light emitting unit 10 is modulated by the light modulation element 20 after being emitted from the bottom side of the VCSEL light emitting unit 10.

Specifically, in the present embodiment, each of the VCSEL light emitting units 10 includes a light emitting body 11, a positive electrode 13 and a negative electrode 12 electrically connected to the light emitting body 11, and the light emitting body 11 corresponding to the positive electrode 13 and the negative electrode 12 may be turned on by turning on the positive electrode 13 and the negative electrode 12. In practical applications, all the light-emitting bodies 11 or part of the light-emitting bodies 11 may be selectively lighted according to practical requirements, that is, all or part of the area of the VCSEL chip may be lighted, so that the VCSEL chip is adapted to different application scenarios. For example, when the detected object needs to be subjected to wide-angle scanning or omnibearing irradiation, the whole VCSEL chip can be lightened by conducting all the luminous bodies 11, and when only the detected object needs to be subjected to specific area scanning or concentrated irradiation, the local area of the VCSEL chip can be lightened by conducting part of the luminous bodies 11, so that the requirements of different scenes on the scanning area of the VCSEL chip can be met, and the energy consumption can be reduced by the way of lightening the local area of the VCSEL chip, and the influence on the performance of the VCSEL chip caused by the temperature rise caused by high power is reduced.

It is worth mentioning that the VCSEL chip enables the VCSEL chip to be adapted to high-speed circuits by isomerising its light emitting body 11. Specifically, in the embodiment of the present application, the light emitting body 11 includes, in order from bottom to top: a substrate layer 111, a P-type electrical contact layer 112, a P-DBR layer 113, an active region 114, a confinement layer 115, an N-DBR layer 116, and an N-type electrical contact layer 117. The light-emitting body 11 may be externally connected with other components, so that the VCSEL chip and the other components together form a circuit system. In one specific example of the present application, the substrate layer 111 is adapted to be connected to an N-type field effect transistor structure to improve the operating efficiency of the circuitry.

Those skilled in the art will appreciate that the N-type field effect transistor switch has a relatively low on-resistance, a relatively small size, and a fast switching speed, as compared to the P-type field effect transistor switch, and is suitable for use in high-speed circuits. However, in conventional VCSEL chips. The substrate layer 111 is directly connected to the N-type electrical contact layer 117 and the N-DBR layer 116, and when the substrate layer 111 and the fet structure are turned on, parasitic devices (e.g., parasitic resistances) easily affect the operation performance (e.g., operation efficiency) of the fet switching circuit. In this specific example, the substrate layer 111 is made of a P-type semiconductor material (i.e., the substrate layer 111 is a P-type substrate layer 111) to form an N-type field effect transistor switch with the N-type field effect transistor structure, and the P-type substrate layer 111 is directly connected to the P-type electrical contact layer 112 and the P-DBR layer 113, in such a manner that adverse effects of parasitic devices on the N-type field effect transistor switch circuit can be reduced.

It is worth mentioning that in order to achieve electrical isolation between the plurality of VCSEL light emitting cells 10, in one specific example of the present application, an isolation trench 102 may be provided between each two of the VCSEL light emitting cells 10. That is, the VCSEL chip has a plurality of isolation trenches 102 formed between every two of the VCSEL light emitting cells 10. Specifically, each of the isolation trenches 102 extends from the N-type electrical contact layer 117 through to the P-type electrical contact layer 112 to electrically isolate the plurality of VCSEL light emitting cells 10 from each other by the plurality of isolation trenches 102.

In other examples of the present application, electrical isolation between the plurality of VCSEL light emitting cells 10 may also be achieved in other ways, which is not limiting of the present application. In another specific example of the present application, the VCSEL chip further includes a plurality of isolation dielectric channels between each two of the VCSEL light emitting units 10 and doped to the light emitting body 11 of each of the VCSEL light emitting units 10 to electrically isolate the plurality of VCSEL light emitting units 10 from each other through the plurality of isolation dielectric channels.

In the embodiment of the application, the N-DBR layer is doped with N-type Al with high aluminum content _x Ga _1-x As (x=1 to 0) and N-doped Al with low aluminum content _x Ga _1-x Alternate layers of As (x=1 to 0) are formed. The P-DBR layer 113 is made of P-type doped high aluminumAmount of Al _x Ga _1-x As (x=1 to 0) and P-doped low aluminum content Al _x Ga _1-x Alternate layers of As (x=1 to 0) are formed. In some examples of the present application, the N-DBR layer 116 and the P-DBR layer 113 may be made of a material that does not even have aluminum content, i.e., does not include aluminum. It is worth mentioning that the material selection of the alternating layers depends on the operating wavelength of the laser light emitted by the VCSEL light emitting unit 10, and that the optical thickness of the alternating layers is equal to or approximately equal to 1/4 of the operating wavelength of the laser light.

The active region 114 is sandwiched between the N-DBR layer 116 and the P-DBR layer 113 to form a resonant cavity, wherein photons are repeatedly amplified by being reflected back and forth within the resonant cavity after being excited to form laser oscillation, thereby forming laser light. It will be appreciated by those of ordinary skill in the art that the emission direction of the laser light can be selectively controlled by configuring and designing the N-DBR layer 116 and the P-DBR layer 113, for example, in one specific example of the present application, the N-DBR layer 116 and the P-DBR layer 113 are configured such that, after the VCSEL light emitting unit 10 is turned on, the laser light generated by the active region 114 is emitted from the P-DBR layer 113, i.e., from the bottom side of the VCSEL light emitting unit 10, after being reflected multiple times within a resonant cavity formed between the N-DBR layer 116 and the P-DBR layer 113. In another specific example of the present application, the N-DBR layer 116 and the P-DBR layer 113 are configured such that, after the VCSEL light emitting unit 10 is turned on, laser light generated by the active region 114 is emitted from the N-DBR layer 116 after being reflected multiple times within a resonant cavity formed between the N-DBR layer 116 and the P-DBR layer 113, i.e., from the top side of the VCSEL light emitting unit 10.

The confinement layer 115 has a confinement hole 101 corresponding to the active region 114, and laser light generated by the active region 114 is emitted from the P-DBR layer 113 or the N-DBR layer 116 of the VCSEL light emitting unit 10 after being reflected multiple times in the resonant cavity and passing through the confinement hole 101.

In some examples of the present application, the confinement layer 115 may be implemented as an oxidation confinement layer formed over the active region 114 by an oxidation process. In implementations, the oxidation-limiting layer may be formed as a separate layer over the active region 114. Of course, in other embodiments, the oxidation-limiting layer may be formed above the active region 114 by oxidizing at least a portion of the lower region of the P-DBR layer 113, which is not limited in this application. In other examples of the present application, the confinement may be implemented in other forms, for example, as an ion confinement layer (not illustrated in the drawings) formed over the active region 114 by an ion implantation process, which is not limited in this application.

In the embodiment of the present application, the positive electrode 13 and the negative electrode 12 are electrically connected to the light emitting body 11, specifically, the positive electrode 13 and the negative electrode 12 are electrically connected to the P-type electric contact layer 112 and the N-type electric contact layer 117, respectively. The specific positions of the positive electrode 13 and the negative electrode 12 are not limited in the present application. In one specific example of the present application, the positive electrode 13 is located on a side surface of the P-type electrical contact layer 112, in another specific example of the present application, the positive electrode 13 is located on a lower surface of the substrate layer 111, in yet another specific example of the present application, the positive electrode 13 is located between the substrate layer 111 and the P-type electrical contact layer 112, and in other specific examples of the present application, the positive electrode 13 may be located at other positions. In one specific example of the present application, the negative electrode 12 is located on the upper surface of the N-type electrical contact layer 117. In other specific examples of the present application, the negative electrode 12 may be located elsewhere.

The shapes of the positive electrode 13 and the negative electrode 12 are not limited in this application, and in a specific example of this application, the laser light generated by the VCSEL light emitting unit 10 is emitted from the N-DBR layer 116, the shape of the cross section of the negative electrode 12 is annular, and the negative electrode 12 has the light emitting hole 103 corresponding to the limiting hole 101, so as to avoid that the negative electrode 12 affects the light emitting performance of the VCSEL light emitting unit 10. In another specific example of the present application, the shape of the cross section of the negative electrode 12 is a parallelogram, and the negative electrode 12 is made of a light-permeable material.

In this embodiment of the present application, not only different areas of the VCSEL chip may be lightened to adapt to different application scenarios, but also the overall divergence angle of the VCSEL chip may be adjusted to adapt to different application scenarios under the cooperation of the light modulation element 20. Specifically, the plurality of light modulation elements 20 have a predetermined structural configuration and cooperate with each other to regulate the overall divergence angle of the VCSEL chip. In view of quantification, in the embodiment of the present application, the overall divergence angle of the VCSEL chip is 120 ° or more, where the overall divergence angle of the VCSEL chip refers to an included angle formed by the outermost laser light among the laser lights emitted from the VCSEL chip. In a specific example of the present application, the overall divergence angle of the VCSEL chip may reach 180 °.

In one specific example of the present application, the plurality of light modulation elements 20 includes at least one modulation element (e.g., convex lens 21) for converging light rays and at least one modulation element (e.g., concave lens) for diverging light rays. The convex lens 21 can reduce the beam divergence angle of the laser light emitted from the VCSEL light emitting unit 10, and the concave lens can increase the beam divergence angle of the laser light emitted from the VCSEL light emitting unit 10. It should be understood that in other examples of the present application, the plurality of light modulation elements 20 may include only modulation elements for converging light rays (e.g., convex lenses 21) or only modulation elements for diverging light rays (e.g., concave lenses), which are not limited by the present application.

The overall divergence angle or scan field of the VCSEL chip can be modulated using the structure of the light modulating element 20 and the illuminated region of the VCSEL chip.

When the entire region of the VCSEL chip is lighted, the divergence angle of the light beam emitted from the VCSEL light emitting unit 10 can be relatively increased by providing the concave lens on at least part of the VCSEL light emitting unit 10 on the outermost side of the VCSEL chip, and thus, the overall divergence angle of the VCSEL chip can be increased. By providing the convex lens 21 on at least part of the VCSEL light emitting units 10 on the outermost side of the VCSEL chip, the beam divergence angle outgoing from the VCSEL light emitting units 10 can be relatively reduced, and thus, the overall divergence angle of the VCSEL chip can be reduced.

When a partial region of the VCSEL chip is lighted, the divergence angle of the light beam emitted from the VCSEL light emitting unit 10 can be relatively increased by providing the concave lens on at least part of the VCSEL light emitting unit 10 of the partial region of the VCSEL chip, and thus, the overall divergence angle of the VCSEL chip can be increased. By providing the convex lens 21 on at least part of the VCSEL light emitting unit 10 of the partial region of the VCSEL chip, the divergence angle of the beam of light emitted from the VCSEL light emitting unit 10 can be relatively reduced, and further, the overall divergence angle of the VCSEL chip can be reduced to perform concentrated irradiation of a specific region to a target to be measured.

Accordingly, in one specific example of the present application, at least part of the concave lens is disposed at the VCSEL light emitting unit 10 located at an edge region of the VCSEL chip, and at least part of the convex lens 21 is disposed at the VCSEL light emitting unit 10 located at a middle region of the VCSEL chip.

Further, the divergence angle or the scanning field of the laser light emitted from the single VCSEL light emitting unit 10 can be controlled by adjusting the curvature of the convex lens 21 and/or the concave lens, thereby controlling the overall divergence angle or the scanning field of the VCSEL chip.

In the embodiment of the present application, at least part of the convex lenses 21 (or the concave lenses) have different radii of curvature. The larger the curvature of the convex lens 21, the smaller the radius of curvature, and the stronger the ability to converge light rays. The larger the curvature of the concave lens, the smaller the curvature radius, and the stronger the capability of diverging light rays. The smaller the radius of curvature of the convex lens 21 corresponding to the VCSEL light emitting unit 10 on the outermost side of the VCSEL chip, the smaller the overall divergence angle of the VCSEL chip. The smaller the radius of curvature of the concave lens corresponding to the VCSEL light emitting unit 10 on the outermost side of the VCSEL chip, the larger the overall divergence angle of the VCSEL chip. Of course, the radii of curvature of all the convex lenses 21 or concave lenses disposed in the plurality of VCSEL light emitting units 10 may be the same, which is not limited to the present application.

In a specific example of the present application, the curvature of the concave lenses provided on the plurality of VCSEL light emitting units 10 sequentially increases in a direction extending outward from the center of the VCSEL chip. Accordingly, the divergence angles of the plurality of VCSEL light emitting units 10 sequentially increase in a direction extending outward from the center of the VCSEL chip, not only making the overall divergence angle of the VCSEL chip relatively large, but also making the laser light emitted from the plurality of VCSEL light emitting units 10 form a continuous scan field.

Further, the divergence angle of the laser light emitted from the single VCSEL light emitting unit 10 can be regulated by the relative positional relationship of the light modulation element 20 and the light emitting body 11 corresponding thereto, thereby regulating the overall divergence angle of the VCSEL chips.

When the light modulation element 20 is the convex lens 21 or the concave lens, the light modulation element 20 has a light center, and a propagation path of light passing through the light center is not changed. The light-emitting body 11 is provided with an optical axis, and a straight line where a longitudinal central axis of the active region 114 of the light-emitting body 11 is located may be set as the optical axis. The light modulation element 20 may be provided to the VCSEL light emitting unit 10 such that its optical center is located on the optical axis set by the light emitting body 11, or may be provided to the VCSEL light emitting unit 10 such that its optical center is offset from the optical axis set by the light emitting body 11.

In a specific example of the present application, at least a part of the optical centers of the convex lenses 21 of the plurality of light modulation elements 20 are located on the optical axis set by the light emitting body 11 corresponding thereto, and the other part of the optical centers of the convex lenses 21 are deviated from the optical axis set by the light emitting body 11 corresponding thereto. At least a part of the optical centers of the concave lenses of the plurality of light modulation elements 20 are positioned on the optical axis set by the light-emitting body 11 corresponding thereto, and the other part of the optical centers of the concave lenses are deviated from the optical axis set by the light-emitting body 11 corresponding thereto.

When the optical axis of the convex lens 21 (or the concave lens) is deviated from the optical axis set by the corresponding light-emitting body 11, the laser beam emitted from the light-emitting body 11 is modulated by the convex lens 21 (or the concave lens) and then the projection direction thereof is deviated in a direction in which the optical axis of the convex lens 21 (or the concave lens) is deviated from the optical axis of the light-emitting body 11.

Specifically, when the optical center of the convex lens 21 (or the concave lens) corresponding to the VCSEL light emitting unit 10 on the outermost side of the VCSEL chip is deviated outward, the overall divergence angle of the VCSEL chip is relatively increased as compared to the optical center of the convex lens 21 (or the concave lens) being located on the optical axis set by the light emitting body 11.

It should be understood that, in other examples of the present application, the optical centers of all the convex lenses 21 of the plurality of light modulation elements 20 may deviate from the optical axes set by the light emitting bodies 11 corresponding thereto. The optical centers of all the concave lenses of the plurality of light modulation elements 20 may be deviated from the optical axes set by the light emitting bodies 11 corresponding thereto, which is not limited to the present application.

When the optical center of the convex lens 21 corresponding to the VCSEL light emitting unit 10 at the outermost side of the VCSEL chip is shifted outward, the smaller the curvature of the convex lens 21, the more the direction of laser projection is shifted outward, and the larger the overall divergence angle of the VCSEL chip is. The overall divergence angle of the VCSEL chip can be adjusted according to the modulation rule generated by the light modulation element structure and the mutual cooperation of the relative positional relationship between the light modulation element 20 and the corresponding light emitting body 11.

It will be appreciated that the laser projection range of a VCSEL chip may be controlled relatively more stably by providing the light modulating element 20 on at least part of the VCSEL light emitting cells 10 of the VCSEL chip than by driving means (e.g. a rotary motor) to effect a relative rotation of the VCSEL chips to control the laser projection range of the VCSEL light source. Meanwhile, the whole divergence angle of the VCSEL chip is increased through the structure of the VCSEL chip, so that a scheme for expanding the laser projection range of the VCSEL light source can be simplified, and the application cost of the VCSEL light source is reduced.

In summary, a VCSEL chip according to an embodiment of the present application is illustrated, which increases its overall divergence angle by its own structural design to expand the scan field of the VCSEL chip.

Method for preparing schematic VCSEL chip

According to another aspect of the present application, there is also provided a method of manufacturing a VCSEL chip for manufacturing a VCSEL chip as described above. Referring to fig. 3 to 4C of the drawings of the specification, a method of fabricating a VCSEL chip according to an embodiment of the present application is illustrated. As shown in fig. 4, the method for preparing the VCSEL chip according to an embodiment of the present application includes: s110, forming a structure to be processed, wherein the structure to be processed sequentially comprises a substrate structure, a P-type electric contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electric contact structure and a layer to be processed from bottom to top; s120, processing the layer to be processed through an etching process to form a plurality of light modulation elements above the N-type electric contact structure so as to obtain a chip semi-finished product; s130, forming a plurality of negative electrodes electrically connected to the N-type electric contact structure; s140, removing at least one part of the chip semi-finished product to form a plurality of mutually electrically isolated sub-structural units, wherein each sub-structural unit comprises a P-type electric contact layer, a P-DBR layer, an active region, an N-DBR layer and an N-type electric contact layer from bottom to top; s150, processing the plurality of sub-structural units to form a limiting layer with limiting holes above the active region to form a plurality of light-emitting bodies; and S160, forming a plurality of positive electrodes respectively electrically connected to the plurality of light-emitting bodies.

Fig. 4A to 4C illustrate schematic diagrams of a process of fabricating the VCSEL chip according to an embodiment of the present application. As shown in fig. 4A, in step S110, a structure to be processed 100 is formed. Specifically, the base structure 110, the P-type electrical contact structure 120, the P-DBR structure 130, the active region structure 140, the N-DBR structure 160, the N-type electrical contact structure 170, and the layer to be processed 180 are formed by a semiconductor growth process.

In one such specific example of the present application, the base structure 110 is made of a P-type semiconductor material, adapted to be connected with an N-type field effect transistor structure, such that the resulting VCSEL chip is adapted for high-speed electricalAnd (5) a road. The material of the layer to be processed 180 is selected from one of the following materials: gaN, alN, al _X Ga _1-X As(x＝0～1)、lnP、Al _X Ga _1-X AsSb(x＝0～1)、AlInAs、InGaAsP。

In step S120, the layer to be processed 180 is processed through an etching process to form a plurality of light modulation elements 20 over the N-type electrical contact structure 170, so as to obtain a chip semi-finished product 200. Specifically, first, an etchable layer is applied on the layer to be processed 180, wherein a material of the etchable layer may be a photoresist layer. Next, the etchable layer is exposed through a mask having a preset pattern to remove a corresponding portion of the etchable layer based on the preset pattern, wherein the remaining etchable layer forms a template 800 having a preset shape and size, wherein the preset shape and size of the template 800 is identical to those of the light modulation element 20. Then, the template 800 and at least a portion of the to-be-processed layer 180 are removed by an etching process, wherein the to-be-processed layer 180 that is left has a shape and size consistent with those of the template 800 to form the plurality of light modulation elements 20, wherein the plurality of light modulation elements 20 include convex lenses 21 and concave lenses.

That is, step S120 includes: applying an etchable layer on the layer to be processed 180; shaping the etchable material through a mask into a template 800 having a preset shape and size, wherein the preset shape and size of the template 800 is consistent with the shape and size of the light modulating element 20; and removing at least a portion of the template 800 and the to-be-processed layer 180 through an etching process, wherein the to-be-processed layer 180 that is left has a shape and size consistent with those of the template 800 to form the plurality of light modulation elements 20.

Specifically, a portion of the template 800 and the layer to be processed 180 may be removed through a dry etching process or a wet etching process. Accordingly, the remaining layer to be processed 180 has a shape and size conforming to the template 800 to form the light modulation element 20. During etching, in order to ensure that the finally remaining layer to be processed 180 has a shape and size consistent with the template 800, the etching speed and the etched area should be precisely controlled.

It should be noted that, during the process of removing a portion of the to-be-processed layer 180 by an etching process, at least a portion of the P-type electrical contact structure 120 is exposed, so as to form an electrical connection region where electrical connection can be achieved. Accordingly, the structure of the structure to be processed 100 processed through the etching process forms the chip semi-finished product 200, wherein the chip semi-finished product 200 includes the base structure 110, the P-type electrical contact structure 120, the P-DBR structure 130, the active region structure 140, the N-DBR structure 160, the N-type electrical contact structure 170, and the optical modulation element 20 from bottom to top.

It should be noted that the divergence angle of the whole VCSEL chip finally formed can be controlled by designing the structure and the position of the light modulation element 20. For example, in one specific example of the present application, at least one concave lens is disposed at a region of the chip semi-finished product 200 near the outer edge to expand the overall divergence angle of the finally formed VCSEL chip, and at least one convex lens 21 is disposed at a partial region of the chip semi-finished product 200 to reduce the overall divergence angle of the VCSEL chip when the partial region is lit.

In step S130, a plurality of negative electrodes 12 electrically connected to the N-type electrical contact structure 170 are formed. Specifically, the plurality of negative electrodes 12 electrically connected to the N-type electric contact structure 170 are formed through an electroplating process, wherein the plurality of negative electrodes 12 are formed at the electric connection region of the N-type electric contact structure 170 of the chip semi-finished product 200. It should be understood that the plurality of negative electrodes 12 may be formed on the chip semi-finished product 200 by other processes, which is not limited in this application.

Preferably, in order to ensure the light emitting performance of the VCSEL chip, the negative electrode 12 of the N-type electrical contact structure 170 is ring-shaped, and the negative electrode 12 has a light emitting hole 103 corresponding to the active region structure 140. The negative electrode 12 is formed around the light modulation element 20, and accordingly, the light modulation element 20 corresponds to the light exit hole 103 of the negative electrode 12 to adjust the overall divergence angle of the VCSEL chip, expanding the scan field (i.e., laser projection range) of the VCSEL chip.

In step S140, at least a portion of the chip semi-finished product 200 is removed to form a plurality of sub-structure units 300 electrically isolated from each other, each of the sub-structure units 300 including the P-type electric contact layer 112, the P-DBR layer 113, the active region 114, the N-DBR layer 116, and the N-type electric contact layer 117 from bottom to top. Specifically, at least a portion of the chip semi-finished product 200 is removed by an etching process to form a plurality of sub-structure units 300 spaced apart from each other. The isolation trenches 102 are formed at the spaced regions between every two sub-structural units 300 such that electrical isolation is achieved between the plurality of sub-structural units 300.

In step S150, the plurality of sub-structure units 300 are processed to form a confinement layer 115 having a confinement hole 101 above the active region 114. Specifically, the limiting layer 115 may be formed through an oxidation process, and first, in order to protect the negative electrode 12, a protective layer 900 covering the negative electrode 12 is required to be formed before oxidizing the sub-structural unit 300; next, oxidizing the plurality of sub-structure units 300, wherein after the sub-structure units 300 are oxidized, a portion of the N-DBR layer 116 is oxidized to form the confinement layer 115 above the active region 114, and wherein the plurality of sub-structure units 300 after the formation of the confinement layer 115 form a plurality of light emitting bodies 11 with the substrate structure, and the confinement holes 101 correspond to the light emitting holes 103; then, the negative electrode 12 is exposed, and in particular, the negative electrode 12 may be exposed by removing at least a portion of the protective layer 900 covering the negative electrode 12. That is, step S160 includes: forming a protective layer 900 covering the negative electrode 12; oxidizing the plurality of sub-structural units 300; and exposing the negative electrode 12.

It should be noted that the confinement layer 115 may be formed by other processes, for example, an ion confinement layer above the active region 114 may be formed by an ion implantation process, which is not limited in this application.

Accordingly, the plurality of sub-structure units 300 after forming the confinement layer 115 form a plurality of light emitting bodies 11 with the substrate structure, each of the light emitting bodies 11 including a substrate layer 111, the P-type electric contact layer 112, the P-DBR layer 113, the active region 114, the confinement layer 115, the N-DBR layer 116, and the N-type electric contact layer 117 from bottom to top.

In step S160, a plurality of positive electrodes 13 electrically connected to the plurality of light emitting bodies 11, respectively, are formed. Specifically, a plurality of positive electrodes 13 electrically connected to the plurality of light emitting bodies 11, respectively, are formed through an electroplating process, and the positive electrodes 13 are electrically connected to the P-type electrical contact layer 112. The plurality of positive electrodes 13 may be formed by other processes, which are not limited to the present application.

In summary, a method for fabricating a VCSEL chip according to an embodiment of the present application is illustrated, which adjusts and controls the overall divergence angle of the VCSEL chip by designing the junction of the VCSEL chip to expand the scan field of the VCSEL chip.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not intended to be limited to the details disclosed herein as such.

Claims

1. A VCSEL chip, comprising:

2. The VCSEL chip of claim 1, wherein the plurality of light modulating elements have a preset structural configuration and cooperate such that the overall divergence angle of the VCSEL chip is equal to 180 °.

3. The VCSEL chip of claim 2, wherein the plurality of light modulating elements comprises at least one concave lens and at least one convex lens.

4. A VCSEL chip as claimed in claim 3, wherein at least part of the concave lens is provided to the VCSEL light emitting cells located at an edge region of the VCSEL chip.

5. The VCSEL chip of claim 4, wherein at least a portion of the convex lens is disposed on the VCSEL light emitting cell in a middle region of the VCSEL chip.

6. A VCSEL chip as claimed in claim 3, wherein at least part of the optical centers of the light modulating elements lie on the optical axis set by the light-emitting body to which they correspond.

7. A VCSEL chip as claimed in claim 3, wherein at least part of the optical centers of the light modulating elements deviate from the optical axes set by the light emitting bodies to which they correspond.

8. A VCSEL chip as claimed in claim 6 or 7, wherein at least part of the convex lenses have different curvatures.

9. The VCSEL chip of claim 1, wherein the substrate layer is made of a P-type semiconductor material.

10. A method of fabricating a VCSEL chip, comprising:

11. The method of fabricating a VCSEL chip as claimed in claim 10, wherein the layer to be processed is treated by an etching process to form a plurality of light modulating elements over the N-type electrical contact structure to obtain a chip semi-finished product, comprising:

Applying an etchable layer on the layer to be processed;

shaping the etchable material through a mask into a template having a preset shape and size, wherein the preset shape and size of the template is consistent with the shape and size of the light modulating element; and

and removing at least a portion of the template and the layer to be processed by an etching process, wherein the retained layer to be processed has a shape and size consistent with the template to form the plurality of light modulation elements.

12. The method of fabricating a VCSEL chip as claimed in claim 10, wherein processing the plurality of sub-structural units to form a confinement layer with a confinement hole over the active region comprises:

forming a protective layer covering the negative electrode;

oxidizing the plurality of substructure units; and

exposing the negative electrode.