CN115579731A

CN115579731A - VCSEL chip and preparation method thereof

Info

Publication number: CN115579731A
Application number: CN202110688016.6A
Authority: CN
Inventors: 郭铭浩; 周圣凯; 王立; 李念宜
Original assignee: Zhejiang Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co ltd
Priority date: 2021-06-21
Filing date: 2021-06-21
Publication date: 2023-01-06

Abstract

A VCSEL chip and a method of fabricating the same are disclosed. The VCSEL chip includes: a plurality of VCSEL light emitting units electrically isolated from each other, wherein each VCSEL light emitting unit includes at least one light emitting body and a positive and a negative connection terminal for conducting the light emitting body; and a plurality of light modulation elements integrally arranged on a laser emission path of at least some of the plurality of VCSEL light emitting units at a wafer level, wherein the plurality of light modulation elements have a predetermined structural configuration and cooperate with each other such that an overall divergence angle of the VCSEL chip is greater than or equal to 120 °, and the overall divergence angle of the VCSEL chip refers to an angle formed by outermost laser light among laser light emitted by the VCSEL chip with respect to a center of the VCSEL chip. The VCSEL chip relatively increases the overall divergence angle thereof through its own structure to enlarge the laser projection range of the VCSEL chip.

Description

VCSEL chip and preparation method thereof

Technical Field

The present application relates to the field of semiconductor lasers, and more particularly to VCSEL chips and methods of fabricating the same.

Background

A VCSEL (Vertical-Cavity Surface-Emitting Laser) refers to a semiconductor Laser that forms a resonant Cavity in the Vertical direction of a substrate and emits Laser light in the Vertical direction. With the development of the VCSEL technology, VCSEL lasers are widely applied to the fields of intelligent transportation, health and medical treatment, biological detection, military security and the like.

In the actual industry, VCSEL lasers are often used as projection light sources to perform depth measurement on measured objects for three-dimensional modeling, depth mapping, and the like. In some application scenarios, the measured target needs to be scanned in a wide angle to perform large-view modeling on the measured target. For example, when the VCSEL chip is applied as a projection light source of a vehicle-mounted laser radar, the VCSEL chip is required to have a larger scanning domain to collect road condition information more comprehensively to assist a vehicle in implementing functional mechanisms such as route planning and road block avoidance. The conventional VCSEL chip usually has a scanning range within 90 °, that is, it can scan only a relatively narrow region of the target to be measured.

In order to overcome this technical problem, in the vehicle-mounted laser radar, a rotating motor is generally provided for the VCSEL chip to rotate the VCSEL chip by the rotating motor, so as to expand the scanning range. However, this solution has a number of drawbacks.

First, the rotation accuracy of the VCSEL chip depends on the structural stability with the rotary motor, and the control accuracy of the rotary motor. That is, if the control precision of the rotation motor is not good, or the matching relationship between the VCSEL chip and the rotation motor is changed, this will affect the scanning effect of the VCSEL chip.

Secondly, under the action of the rotating motor, the relative position relationship between the VCSEL chip and the measured object is adjusted, and although the scanning domain of the VCSEL chip can be expanded by the method, the information processing difficulty of the subsequent three-dimensional modeling is increased due to the adjustment of the relative position relationship between the VCSEL chip and the measured object.

Therefore, an optimized solution is needed to expand the scan domain of the VCSEL chip.

Disclosure of Invention

An advantage of the present application is to provide a VCSEL chip and a method for manufacturing the VCSEL chip, in which the VCSEL chip increases its overall divergence angle through its own structural design to expand a scanning domain of the VCSEL chip, that is, the VCSEL chip according to an embodiment of the present application can realize expansion of its own scanning domain (that is, expansion of a laser projection range) without an external driver.

To achieve at least one of the above advantages or other advantages and objects, according to one aspect of the present application, there is provided a VCSEL chip including:

a plurality of VCSEL light emitting units electrically isolated from each other, wherein each VCSEL light emitting unit includes at least one light emitting body and a positive and a negative connection terminal for conducting the light emitting body; and

the light modulation elements are integrally arranged on the laser emitting paths of at least part of the VCSEL light emitting units in the VCSEL light emitting units at a wafer level, wherein the light modulation elements have preset structural configurations and are matched with each other so that the integral divergence angle of the VCSEL chip is larger than or equal to 120 degrees, and the integral divergence angle of the VCSEL chip refers to an included angle formed by the outermost laser in the laser emitted by the VCSEL chip.

In the VCSEL chip according to the present application, the plurality of light modulation elements have a predetermined structural configuration and cooperate with each other such that the overall divergence angle of the VCSEL chip is equal to 180 °.

In the VCSEL chip according to the present application, the plurality of light modulation elements include concave lenses and convex lenses.

In the VCSEL chip according to the present application, a portion of the convex lenses and the light emitting bodies corresponding thereto are arranged in a centered manner.

In the VCSEL chip according to the present application, another portion of the convex lens is disposed eccentrically to the light emitting body opposite thereto.

In the VCSEL chip according to the present application, a portion of the concave lens and the light-emitting body corresponding thereto are arranged in a centered manner.

In the VCSEL chip according to the present application, another portion of the concave lens is disposed eccentrically from the light emitting body corresponding thereto.

In the VCSEL chip according to the present application, at least a part of the convex lenses have different radii of curvature.

In the VCSEL chip according to the present application, the light emitting body includes, in order from bottom to top: the semiconductor device comprises a substrate layer, an N-type electric contact layer, an N-DBR layer, an active region, a limiting layer, a P-DBR layer and a P-type electric contact layer, wherein the limiting layer is provided with a limiting hole corresponding to the active region, the positive electricity connecting end is electrically connected to the P-type electric contact layer, and the negative electricity connecting end is electrically connected to the N-type electric contact layer.

In the VCSEL chip according to the present application, the substrate layer is made of a non-conductive material.

In the VCSEL chip according to the present application, the substrate layers of the light emitting hosts of the plurality of VCSEL light emitting units are connected to each other to have a unitary structure.

In the VCSEL chip according to the present application, the positive connection terminal has a ring structure and forms a light exit hole corresponding to the limiting hole, wherein the light modulation element is integrally formed in the light exit hole, in such a manner that the light modulation element is integrally disposed on a wafer level on a laser emission path of at least some of the VCSEL light emitting units among the plurality of VCSEL light emitting units.

According to another aspect of the present application, there is provided a method of manufacturing a VCSEL chip, including:

forming a semiconductor structure, wherein the semiconductor structure sequentially comprises a substrate layer structure, an N-type electric contact layer structure, an N-DBR layer structure, an active region structure, a P-DBR layer structure, a P-type electric contact layer structure and a layer structure to be processed from bottom to top;

processing the layer structure to be processed by using an etching process to form a plurality of light modulation elements above the P-type electric contact layer structure so as to obtain a chip semi-finished product;

forming a plurality of positive electrical connection terminals electrically connected to the P-type electrical contact layer structure of the chip semi-finished product;

removing at least a part of the chip semi-finished product to form a plurality of mutually separated substructure units, wherein each substructure unit comprises an N-type electric contact layer, an N-DBR layer, an active region, a limiting layer, a P-DBR layer and a P-type electric contact layer from bottom to top;

processing the plurality of substructure units to form a confinement layer with a confinement hole above the active region, wherein the plurality of substructure units and the substrate layer structure after forming the confinement layer form a plurality of light emitting bodies, each of the light emitting bodies including, from bottom to top, the substrate layer, the N-type electrical contact layer, the N-DBR layer, the active region, the confinement layer, the P-DBR layer, and the P-type electrical contact layer; and

forming a plurality of negative electrical connection terminals electrically connected to the plurality of light emitting bodies, respectively.

In the method for manufacturing a VCSEL chip according to the present application, the layer structure to be processed is processed using an etching process to form a plurality of light modulation elements over the P-type electrical contact layer structure to obtain a chip semi-finished product, including: applying an etchable layer on the structure to be processed; shaping the etchable material through a mask into a template having a predetermined shape and size, wherein the predetermined shape and size of the template conforms to the shape and size of the light modulation elements; and removing at least a portion of the template and the structure to be processed by an etching process, wherein the structure to be processed that is retained has a shape and size that conforms to the template to form the plurality of light modulation elements.

In a method of fabricating a VCSEL chip according to the present application, processing the plurality of sub-structure units through an oxidation process to form an oxidized confinement layer having a confinement hole over the active region includes: forming a protective layer covering the plurality of positive electrical connection terminals; oxidizing the plurality of sub-building blocks; and exposing the positive electrical connection terminal.

Further objects and advantages of the present application will become apparent from an understanding of the ensuing description and drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the invention, taken in conjunction with the accompanying drawings of which:

fig. 1 illustrates a schematic diagram of a plurality of light emitting units configured with light modulation elements according to an embodiment of the present application.

Fig. 2 illustrates a schematic diagram of the VCSEL chip according to an embodiment of the present application.

Fig. 3 illustrates a light emission schematic diagram of the VCSEL chip according to an embodiment of the present application.

Fig. 4 illustrates a schematic structural diagram of one VCSEL light emitting unit of the VCSEL chip according to an embodiment of the present application.

Fig. 5 illustrates a schematic structural diagram of another VCSEL light emitting unit of the VCSEL chip according to an embodiment of the present application.

Fig. 6A illustrates one of schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the present application.

Fig. 6B illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the present application.

Fig. 6C illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the present application.

Fig. 6D illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the application.

Fig. 6E illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the application.

Fig. 6F illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the application.

Fig. 6G illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the application.

Fig. 6H illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the present application.

Fig. 6I illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the present application.

Fig. 6J illustrates one of the schematic diagrams of the VCSEL chip adjusting its laser exit path according to an embodiment of the application.

Fig. 7 illustrates a flow chart of a method of fabricating a VCSEL chip in accordance with an embodiment of the present application.

Fig. 8A illustrates one of the schematic diagrams of a fabrication process of a VCSEL chip according to an embodiment of the present application.

Fig. 8B illustrates a second schematic diagram of a fabrication process of a VCSEL chip in accordance with an embodiment of the present application.

Fig. 8C illustrates a third schematic diagram of a fabrication process of a VCSEL chip in accordance with an embodiment of the present application.

Fig. 8D illustrates four schematic views of a fabrication process of a VCSEL chip according to an embodiment of the present application.

Fig. 8E illustrates five of the schematic diagrams of the fabrication process of the VCSEL chip according to an embodiment of the present application.

Detailed Description

The terms and words used in the following specification and claims are not limited to the literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. Accordingly, it will be apparent to those skilled in the art that the following descriptions of the various embodiments of the present application are provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It is understood that the terms "a" and "an" should be interpreted as meaning "at least one" or "one or more," i.e., that a quantity of one element may be one in one embodiment, while a quantity of another element may be plural in other embodiments, and the terms "a" and "an" should not be interpreted as limiting the quantity.

While ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used only to distinguish one element from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the teachings of the inventive concepts. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, numbers, steps, operations, components, elements, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, elements, or groups thereof.

Summary of the application

As described above, a VCSEL (Vertical-Cavity Surface-Emitting Laser) refers to a semiconductor Laser that forms a resonant Cavity in the Vertical direction of a substrate and emits Laser light in the Vertical direction. With the development of the VCSEL technology, VCSEL lasers are widely applied to the fields of intelligent transportation, health and medical treatment, biological detection, military security and the like.

In the actual industry, VCSEL lasers are often used as projection light sources to perform depth measurement on an object to be measured for three-dimensional modeling, depth mapping, and the like. In some application scenarios, the measured object needs to be scanned in a wide angle to perform large-view modeling on the measured object. For example, when the VCSEL chip is applied as a projection light source of a vehicle-mounted laser radar, the VCSEL chip is required to have a larger scanning domain to more comprehensively collect road condition information to assist a vehicle in implementing functional mechanisms such as route planning and obstacle avoidance. The conventional VCSEL chip usually has a scanning range within 90 °, that is, it can scan only a relatively narrow region of the target to be measured.

In order to overcome this technical problem, in the vehicle-mounted laser radar, a rotating motor is generally provided for the VCSEL chip to rotate the VCSEL chip by the rotating motor, so that the scanning range is enlarged. However, this solution has a number of drawbacks.

Secondly, under the action of the rotating motor, the relative position relationship between the VCSEL chip and the measured object is adjusted, and although the scanning domain of the VCSEL chip can be expanded in this way, the information processing difficulty of the subsequent three-dimensional modeling is increased due to the adjustment of the relative position relationship between the VCSEL chip and the measured object.

In addition, if the real-time monitoring of the surrounding environment is to be realized, the rotating mechanism needs to keep high-frequency rotation and is easy to wear, so that on one hand, the requirement on the performance of the rotating mechanism is high, and on the other hand, the working performance of the rotating mechanism is difficult to keep stable.

In addition, the laser projection range (i.e. the scanning range) of the VCSEL light source is expanded by the VCSEL light source cooperating with the driving device, which is not favorable for the miniaturization of the whole device, for example, the core reason of the large size of the existing lidar device is that the rotating mechanism occupies a relatively large volume.

Aiming at the technical problems, the technical idea of the application is as follows: the integral divergence angle of the VCSEL chip is increased through the structural design of the VCSEL chip, so that the scanning domain of the VCSEL chip is expanded, namely, the VCSEL chip according to the embodiment of the application can realize expansion of the scanning domain of the VCSEL chip (namely expansion of the laser projection range) on the premise of not needing an external driver. Specifically, by configuring an array of light modulation elements with different light modulation properties on the exit path of a plurality of VCSEL light emitting units of a VCSEL chip, the overall divergence angle of the VCSEL chip is expanded by the array of light modulation elements, that is, the scanning area or the laser projection range thereof is expanded.

Based on this, according to an aspect of the present application, the present application proposes a VCSEL chip, which includes: a plurality of VCSEL light emitting units electrically isolated from each other, wherein each VCSEL light emitting unit includes at least one light emitting body and a positive and a negative connection terminal for conducting the light emitting body; and a plurality of light modulation elements integrally arranged on the laser emitting paths of at least some of the plurality of VCSEL light emitting units at a wafer level, wherein the plurality of light modulation elements have a predetermined structural configuration and cooperate with each other such that the overall divergence angle of the VCSEL chip is greater than or equal to 120 °, and the overall divergence angle of the VCSEL chip refers to an included angle formed by the outermost laser in the laser emitted by the VCSEL chip.

Based on this, according to another aspect of the present application, there is provided a method of manufacturing a VCSEL chip, including: forming a semiconductor structure, wherein the semiconductor structure sequentially comprises a substrate layer structure, an N-type electric contact layer structure, an N-DBR layer structure, an active region structure, a P-DBR layer structure, a P-type electric contact layer structure and a layer structure to be processed from bottom to top; processing the layer structure to be processed by using an etching process to form a plurality of light modulation elements above the P-type electric contact layer structure so as to obtain a chip semi-finished product; forming a plurality of positive electrical connection terminals electrically connected to the P-type electrical contact layer structure of the chip semi-finished product; removing at least a part of the chip semi-finished product to form a plurality of mutually separated substructure units, wherein each substructure unit comprises an N-type electric contact layer, an N-DBR layer, an active region, a limiting layer, a P-DBR layer and a P-type electric contact layer from bottom to top; processing the plurality of substructure units to form a confinement layer with a confinement hole above the active region, wherein the plurality of substructure units and the substrate layer structure after forming the confinement layer form a plurality of light emitting bodies, each of the light emitting bodies including, from bottom to top, the substrate layer, the N-type electrical contact layer, the N-DBR layer, the active region, the confinement layer, the P-DBR layer, and the P-type electrical contact layer; and forming a plurality of negative electrical connection terminals electrically connected to the plurality of light emitting bodies, respectively.

Here, the VCSEL light-emitting unit may refer to one VCSEL light-emitting point (i.e., the VCSEL light-emitting unit includes one light-emitting body) or a light-emitting region formed by a plurality of VCSEL light-emitting points (i.e., the VCSEL light-emitting unit includes two or more light-emitting bodies, and the two or more light-emitting bodies form one light-emitting region). In a specific implementation, the plurality of light emitting points may be wired by a multilayer wiring structure.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described with reference to the accompanying drawings.

Illustrative VCSEL chip

As shown in fig. 1 to 3, a VCSEL chip according to an embodiment of the present application is illustrated, wherein the VCSEL chip includes a plurality of VCSEL light emitting units 10 electrically isolated from each other and a plurality of light modulation elements 20 disposed on laser light exit paths of at least some of the VCSEL light emitting units 10 among the plurality of VCSEL light emitting units 10. That is, the VCSEL chip configures the corresponding light modulation element 20 for at least some VCSEL light emitting units 10 of the plurality of VCSEL light emitting units 10 to modulate the laser light emitted from the at least some VCSEL light emitting units 10.

As shown in fig. 1 to 5, each of the VCSEL light-emitting units 10 includes at least one light-emitting body 11 and positive and

negative connection terminals

12 and 13 for connecting the light-emitting body 11. In the embodiment of the present application, the light emitting body 11 includes, in order from bottom to top, a substrate layer 111, an N-type electrical contact layer 112, an N-DBR layer 113, an active region 114, a confinement layer 115, a P-DBR layer 116, and a P-type electrical contact layer 117, wherein the confinement layer 115 has a confinement hole 101 corresponding to the active region 114.

It is worth mentioning that, in one specific example of the present application, the substrate layers 111 of the light emitting hosts 11 of the plurality of VCSEL light emitting units 10 are connected to each other to have a unitary structure. Accordingly, the substrate layer 111 is made of a non-conductive material, so that, although the substrate layers 111 of every two VCSEL light-emitting units 10 are connected to each other, electrical isolation between the plurality of VCSEL light-emitting units 10 can be achieved.

It should be understood that, in other examples of the present application, the substrate layers 111 of the light emitting bodies 11 of the plurality of VCSEL light emitting units 10 may also be disposed at intervals from each other, and this is not a limitation of the present application.

In the embodiment of the present application, the N-DBR layer 113 is made of N-type doped Al with high Al content _x Ga _1-x As (x = 1-0) and N-doped Al with low aluminum content _x Ga _1-x Alternating layers of As (x = 1-0), wherein the Al is N-doped with high aluminum content _x Ga _1-x As and N-doped low aluminum content Al _x Ga _1-x As has different refractive indices to form an N-type Distributed Bragg Reflector (N-Distributed Bragg Reflector). The P-DBR layer 116 is formed of alternating layers of P-doped high aluminum content AlGaAs and P-doped low aluminum content AlGaAs, wherein the P-doped high aluminum content AlGaAs and the P-doped low aluminum content AlGaAs have different refractive indices to form a P-Distributed Bragg Reflector (P-DBR). In some examples of the present application, the N-DBR layer 113 and the P-DBR layer 116 may be made of materials that do not even have an aluminum content, i.e., do not contain aluminum. It is worth mentioning that the material selection of the alternating layers depends on the operating wavelength of the laser light emitted from the VCSEL light emitting unit 10, and the optical thickness of the alternating layers is equal to or approximately equal to 1/4 of the operating wavelength of the laser light.

The active region 114 includes quantum wells (of course, in other examples of the application, the active region 114 may include quantum dots), which may be made of aliningaas (e.g., alInGaAs, alGaAs, and InGaAs), inGaAsP (e.g., inGaAsP, gaAs, inGaAs, gaAsP, and GaP), gaAsSb (e.g., gaAsSb, gaAs, and GaSb), inGaAsN (e.g., inGaAsN, gaAs, inGaAs, gaAsN, and GaN), or alinasp (e.g., alinasp, alInGaAs, alGaAs, inGaAs, ingasp, gaAs, inGaAs, gaAsP, and GaP). Of course, in the embodiment of the present application, the active region 114 may also be made of other compositions for forming a quantum well layer.

The active region 114 is sandwiched between the N-DBR layer 113 and the P-DBR layer 116 to form a resonant cavity, wherein photons are repeatedly amplified by being reflected back and forth in the resonant cavity after being excited to form laser oscillation, thereby forming laser light. Those skilled in the art will appreciate that the emission direction of the laser light can be selectively controlled by the configuration and design of the N-DBR layer 113 and the P-DBR layer 116, for example, the emission from the N-DBR layer 113 or the emission from the P-DBR layer 116.

In some specific examples of the present application, the N-DBR layer 113 and the P-DBR layer 116 are configured such that: after the VCSEL light emitting unit 10 is turned on, the laser light generated from the active region 114 is reflected multiple times in the resonant cavity formed between the N-DBR layer 113 and the P-DBR layer 116, and then exits from the P-DBR layer 116 of the VCSEL light emitting unit 10.

In other specific examples of the present application, the N-DBR layer 113 and the P-DBR layer 116 are configured such that: after the VCSEL light emitting unit 10 is turned on, laser light generated from the active region 114 is reflected multiple times in a resonant cavity formed between the N-DBR layer 113 and the P-DBR layer 116, and then exits from the N-DBR layer 113 of the VCSEL light emitting unit 10. Accordingly, the substrate layer 111 is relatively thin to ensure the performance of the laser emitted from the VCSEL light emitting unit 10.

Further, the confinement layer 115 has a confinement hole 101 corresponding to the active region 114, and laser light generated by the active region 114 passes through the confinement hole 101 after being reflected multiple times in the resonant cavity, and then exits from the P-DBR layer 116 of the VCSEL light emitting unit 10.

In some examples of the present application, the confinement layer 115 may be implemented as an oxidized confinement layer 115 formed over the active region 114 by an oxidation process. In a specific implementation, the oxide confinement layer 115 may be formed as a separate layer over the active region 114. Of course, in other embodiments, the oxidized confinement layer 115 may also be formed above the active region 114 by oxidizing at least a portion of the lower region of the P-DBR layer 116, which is not limited in this application. In other examples, the confinement layer 115 may be implemented in other forms, for example, an ion confinement layer 115 (not shown) formed above the active region 114 by an ion implantation process, which is not limited by the present disclosure.

The positive electrical connection terminal 12 and the negative electrical connection terminal 13 are electrically connected to the light emitting body 11. In a specific example of the present application, the positive and

negative connection terminals

12 and 13 of the VCSEL light emitting unit 10 are formed on the P-type electrical contact layer 117 and the N-type electrical contact layer 112 of the light emitting body 11, respectively.

It should be understood that the positive electrical connection terminal 12 and the negative electrical connection terminal 13 may be formed at other positions of the light emitting body 11. For example, the positive connection terminal 12 and the negative connection terminal 13 are disposed on the same plane, which is not intended to limit the present application.

Further, in a specific example of the present application, the positive connection terminal 12 has a ring-shaped structure and forms a light exit hole 103 corresponding to the limiting hole 101. That is, the laser light emitted from the light emitting body 11 passes through the light exit hole 103 formed by the ring structure of the positive electrode connecting terminal 12 and is then emitted.

During operation, an operating voltage/current is applied to the positive electrical connection terminal 12 and the negative electrical connection terminal 13 of the light emitting body 11 to generate a current in the semiconductor structure. After being turned on, the current is restricted from flowing by the confinement layer 115 formed above the active region 114, which is finally introduced into the middle region of the semiconductor structure, so that laser light is generated in the middle region of the active region 114. More specifically, as shown in fig. 1 and 2, in the embodiment of the present application, the peripheral region of the confinement layer 115 formed above the active region 114 forms a confinement region, wherein the confinement region has a higher resistivity to confine carriers to flow into the middle region of the semiconductor, and the refractive index of the confinement region is lower to confine photons laterally, the carrier and optical lateral confinement increases the density of carriers and photons in the active region 114, and improves the efficiency of generating light in the active region 114, and the confinement holes 101 define the aperture of the light exit hole 103 of the light emitting body 11.

It will be appreciated that, upon application of an operating voltage/current to the positive and negative

electrical connection terminals

12 and 13 of the light emitting body 11, the active region 114 is excited to generate laser light and the laser light is emitted from the upper surface of the P-DBR layer 116 after being reflected and oscillated between the P-DBR layer 116 and the N-DBR layer 113. Accordingly, as shown in fig. 1 to 3, in the present example, the optical modulation element 20 is integrally disposed on the wafer level on the laser emission path of at least some of the VCSEL light emitting units 10 in the plurality of VCSEL light emitting units 10, and therefore, the optical modulation element 20 can modulate the laser emitted from the VCSEL light emitting units 10 to control the laser projection direction of the VCSEL chips, and thus, the overall divergence angle of the VCSEL chips.

It should be noted that, in order to achieve electrical isolation between the VCSEL light-emitting units 10, in the embodiment of the present application, an isolation groove 102 may be disposed between every two VCSEL light-emitting units 10. That is, the VCSEL chip has a plurality of isolation trenches 102 formed between every two VCSEL light emitting units 10. Specifically, each isolation trench 102 extends downward from the P-type electrical contact layer 117 to the substrate layer 111, so as to electrically isolate the VCSEL emission units 10 from each other through the isolation trenches 102.

As described above, in the embodiment of the present application, the plurality of light modulation elements 20 are disposed on the laser emission paths of at least some of the plurality of VCSEL light emitting units 10 to increase the overall divergence angle of the VCSEL chip by modulating the laser light emitted from the at least some VCSEL light emitting units 10. In view of quantification, in the embodiment of the present application, the overall divergence angle of the VCSEL chip is greater than or equal to 120 °, where the overall divergence angle of the VCSEL chip refers to an included angle formed by the outermost laser light of the laser light emitted by the VCSEL chip, as shown in fig. 3.

Specifically, the overall divergence angle of the VCSEL chip can be controlled by designing the distribution position of the plurality of light modulation elements 20 and the structure thereof. The plurality of light modulation elements 20 have a predetermined structural configuration and cooperate with each other such that the overall divergence angle of the VCSEL chip is 120 ° or greater. In a specific example, by the cooperation of the plurality of light modulation elements 20, the overall divergence angle of the VCSEL chip reaches 180 °.

More specifically, as shown in fig. 1 and 2, in one specific example of the present application, the plurality of light modulation elements 20 include a light modulation structure (e.g., a convex lens 21) for converging light rays and a light modulation structure (e.g., a concave lens 22) for diverging light rays. The convex lens 21 can reduce a beam divergence angle of the laser light emitted from the VCSEL light emitting unit 10, and the concave lens 22 can increase the beam divergence angle of the laser light emitted from the VCSEL light emitting unit 10. It should be understood that, in other examples of the present application, the plurality of light modulation elements 20 may also include other types of modulation elements capable of modulating the emission angle of the laser light emitted from the VCSEL light emitting unit 10, which is not limited in this application. It should also be understood that the plurality of light modulation elements 20 may also include only light modulation structures for converging light rays (e.g., convex lenses 21) or only light modulation structures for diverging light rays (e.g., concave lenses 22), and the application is not limited thereto.

Accordingly, the overall divergence angle or scan field of the VCSEL chip can be controlled by adjusting the dimming characteristics (e.g., converging light, diverging light) of the light modulation element 20 and the distribution positions of the light modulation elements 20 having different dimming characteristics.

The divergence angle of the light beams emitted from the VCSEL light emitting units 10 can be relatively increased by disposing the concave lenses 22 on at least a portion of the VCSEL light emitting units 10 on the outermost sides of the VCSEL chips, thereby increasing the overall divergence angle of the VCSEL chips. The divergence angle of the light beam emitted from the VCSEL light emitting unit 10 can be relatively reduced by disposing the convex lens 21 on at least a part of the VCSEL light emitting unit 10 on the outermost side of the VCSEL chip, and thus, the overall divergence angle of the VCSEL chip can be reduced.

In a specific example of the present application, the convex lens 21 is disposed on the VCSEL light emitting unit 10 in the middle region of the VCSEL chip, and the concave lens 22 is disposed on the VCSEL light emitting unit 10 in the peripheral region of the VCSEL chip. The scanning domains of the laser emitted from different regions of the VCSEL chip are different, and the integral divergence angle or the scanning domain of the VCSEL chip is changed along with the change of the scanning domains of the laser emitted from different regions.

Further, the divergence angle or the scanning range of the laser light emitted from the individual VCSEL light emitting units 10 can be controlled by adjusting the curvature of the convex lens 21 and/or the concave lens 22, so as to control the overall divergence angle or the scanning range of the VCSEL chip.

In the embodiment of the present application, at least some of the convex lenses 21 (or, the concave lenses 22) have different radii of curvature. The greater the curvature of the convex lens 21, the smaller the radius of curvature, and the stronger the ability to converge light, as shown in fig. 6G and 6H. The larger the curvature of the concave lens 22, the smaller the radius of curvature, and the stronger the ability to diverge the light. The smaller the curvature radius of the convex lens 21 corresponding to the VCSEL light emitting unit 10 at the outermost side of the VCSEL chip is, the smaller the overall divergence angle of the VCSEL chip is. The smaller the curvature radius of the concave lens 22 corresponding to the VCSEL light emitting unit 10 on the outermost side of the VCSEL chip is, the larger the overall divergence angle of the VCSEL chip is. Of course, the curvature radius of all the convex lenses 21 or the concave lenses 22 disposed on the plurality of VCSEL light-emitting units 10 may be the same, and this is not a limitation of the present application.

In a specific example of the present application, the curvatures of the concave lenses 22 provided on the plurality of VCSEL light emitting units 10 increase in sequence in a direction extending outward from the center of the VCSEL chip. Accordingly, in a direction extending outward from the center of the VCSEL chip, the divergence angles of the VCSEL light emitting units 10 are sequentially increased, so that not only is the overall divergence angle of the VCSEL chip relatively large, but also the laser light emitted from the VCSEL light emitting units 10 forms a continuous scanning field.

Further, the divergence angle of laser light emitted from a single VCSEL light emitting unit 10 can be controlled by the relative positional relationship between the light modulation element 20 and the light emitting body 11 corresponding thereto, thereby controlling the overall divergence angle of the VCSEL chip.

In a specific example of the present application, a part of the convex lenses 21 of the plurality of light modulation elements 20 and the light emitting bodies 11 corresponding thereto are disposed in a centered manner, and another part of the convex lenses 21 and the light emitting bodies 11 opposite thereto are disposed eccentrically. A part of the concave lenses 22 of the plurality of light modulation elements 20 is provided in a centered manner with respect to the light emitting bodies 11 corresponding thereto, and the other part of the concave lenses 22 is provided in an off-center manner with respect to the light emitting bodies 11 corresponding thereto.

Specifically, the convex lens 21 and the concave lens 22 each have an optical center through which the propagation path of light rays does not change. An extension line of the central axis of the active region 114 forms the central axis of the light emitting body 11. When the optical center of the convex lens 21 (or the concave lens 22) is on the straight line of the central axis of the light-emitting body 11, it is considered that the optical center of the convex lens 21 (or the concave lens 22) is aligned with the center of the light-emitting body 11, that is, the convex lens 21 (or the concave lens 22) and the light-emitting body 11 are arranged in a centering manner. When the optical center of the convex lens 21 (or the concave lens 22) is not on the straight line of the central axis of the light-emitting body 11, it is considered that the optical center of the convex lens 21 (or the concave lens 22) is not aligned with the center of the light-emitting body 11, that is, the convex lens 21 (or the concave lens 22) is disposed eccentrically to the light-emitting body 11.

As shown in fig. 6A to 6F, when the convex lens 21 (or the concave lens 22) is disposed eccentrically from the light emitting body 11, the projection direction of the laser light emitted from the light emitting body 11 modulated by the convex lens 21 (or the concave lens 22) is shifted in a direction in which the optical center of the convex lens 21 (or the concave lens 22) is shifted from the central axis of the light emitting body 11.

Specifically, when the optical center of the convex lens 21 (or the concave lens 22) corresponding to the VCSEL light-emitting unit 10 at the outermost side of the VCSEL chip is shifted outward, the laser projection direction is shifted outward and the overall divergence angle of the VCSEL chip is relatively increased compared to when the convex lens 21 (or the concave lens 22) is disposed centered with respect to the light-emitting body 11.

It should be understood that in other examples of the present application, the convex lenses 21 of the plurality of light modulation elements 20 and the light emitting bodies 11 corresponding thereto may be all arranged in a centered manner or all arranged in an off-centered manner. The concave lens 22 and the corresponding light-emitting body 11 may be all arranged in a centered manner or all arranged in a decentered manner. And is not intended to limit the scope of the present application.

It is worth mentioning that the divergence angle or scanning range of the VCSEL chip can also be controlled in combination with the structure of the light modulation element 20 (e.g., lens type, lens curvature) and the relative positional relationship of the light modulation element 20 and the light emitting body 11 corresponding thereto.

As shown in fig. 6I and 6J, when the optical center of the convex lens 21 corresponding to the VCSEL light-emitting unit 10 on the outermost side of the VCSEL chip is shifted outward, the smaller the curvature of the convex lens 21, the more outward the direction of laser light projection is shifted, and the larger the overall divergence angle of the VCSEL chip is. The overall divergence angle of the VCSEL chip can be adjusted according to the structure of the light modulation element 20 and the modulation rule of the light modulation element 20 and the corresponding light emitting body 11 to the laser light.

It should be understood that the laser projection range of the VCSEL chip can be controlled relatively more stably by disposing the light modulation element 20 on at least a portion of the VCSEL light emitting cells 10 of the VCSEL chip, as compared to controlling the laser projection range of the VCSEL light source by driving means (e.g., a rotary motor) to achieve relative rotation of the VCSEL chip. Meanwhile, the overall divergence angle of the VCSEL chip is increased through the structure of the VCSEL chip, so that the scheme of expanding the laser projection range of the VCSEL light source can be simplified, and the application cost of the VCSEL light source is reduced.

It is worth mentioning that, in a specific example, the plurality of light modulation elements 20 may be formed above at least some of the VCSEL light emitting units 10 through a packaging process to be disposed on the laser emission path of at least some of the VCSEL light emitting units 10 in the plurality of VCSEL light emitting units 10. In the embodiment of the present application, the light modulation element 20 may be made of a semiconductor material or a polymer, and preferably, the light modulation element 20 is integrally formed in the light exit hole 103 of the VCSEL light emitting unit 10 through a semiconductor process (e.g., a non-metal vapor deposition process and/or a metal vapor deposition process), in such a way that the light modulation element 20 is integrally disposed on the wafer level on the laser exit path of at least some of the VCSEL light emitting units 10 in the plurality of VCSEL light emitting units 10. Moreover, the wafer-level integration process can enable relatively high positioning accuracy between the light modulation element 20 and the VCSEL light emitting unit 10, so that the light modulation element 20 can relatively precisely control the laser projection angle. It should be understood that the light modulation element 20 may be made of other materials, and is not limited in this application. It should also be understood that the light modulation element 20 may also be integrally formed in the light exit hole 103 of the VCSEL light emitting unit 10 by other processes, which are not limited by the present application.

In summary, based on the VCSEL chip according to the embodiment of the present disclosure, the VCSEL chip relatively increases the overall divergence angle of the VCSEL chip through its own structural design to enlarge the scanning area of the VCSEL chip, that is, the VCSEL chip according to the embodiment of the present disclosure can realize expansion of its own scanning area (that is, expansion of the laser projection range) without an external driver. The VCSEL chip can control the overall divergence angle of the VCSEL chip relatively stably by disposing the light modulation element 20 on at least a portion of the VCSEL light emitting unit 10. And the VCSEL chip can control the overall divergence angle of the VCSEL chip by adjusting the distribution position and structure of the light modulation elements 20 provided to the VCSEL light emitting unit 10.

Preparation method of illustrative VCSEL chip

According to another aspect of the present application, there is also provided a method for manufacturing a VCSEL chip, which is used for manufacturing the VCSEL chip as described above. Referring to fig. 7 to 8E of the drawings accompanying the specification, a method of fabricating a VCSEL chip in accordance with an embodiment of the present application is illustrated. As shown in fig. 7, a method for manufacturing a VCSEL chip according to an embodiment of the present application includes: s110, forming a semiconductor structure, wherein the semiconductor structure sequentially comprises a substrate layer structure, an N-type electric contact layer structure, an N-DBR layer structure, an active region structure, a P-DBR layer structure, a P-type electric contact layer structure and a layer structure to be processed from bottom to top; s120, processing the layer structure to be processed by using an etching process to form a plurality of light modulation elements above the P-type electric contact layer structure so as to obtain a chip semi-finished product; s130, forming a plurality of positive electric connection ends electrically connected to the P-type electric contact layer structure of the chip semi-finished product; s140, removing at least a part of the chip semi-finished product to form a plurality of mutually separated substructure units, wherein each substructure unit comprises an N-type electric contact layer, an N-DBR layer, an active region, a limiting layer, a P-DBR layer and a P-type electric contact layer from bottom to top; s150, processing the plurality of substructure units to form a confinement layer with a confinement hole above the active region, wherein the plurality of substructure units and the substrate layer structure after forming the confinement layer form a plurality of light emitting bodies, each of which comprises, from bottom to top, the substrate layer, the N-type electrical contact layer, the N-DBR layer, the active region, the confinement layer, the P-DBR layer and the P-type electrical contact layer; and S160 forming a plurality of negative electric connection terminals electrically connected to the plurality of light emitting bodies, respectively.

Fig. 8A to 8E illustrate schematic views of a fabrication process of the VCSEL chip according to an embodiment of the present application. As shown in fig. 8A, in step S110, a semiconductor structure 100 is formed. Specifically, the substrate layer structure 110, the N-type electrical contact structure 120 stacked on the substrate layer structure 110, the N-DBR structure 130, the active region structure 140, the P-DBR structure 160, the P-type electrical contact structure 170, and the layer structure to be processed 180 are formed through a semiconductor growth process. In one specific example of the present application, the layer structure 180 to be processed is producedThe material is selected from one of the following: gaN, alN, al _X Ga _1-X As (x＝0～1)、lnP、Al _X Ga _1-X AsSb(x＝0～1)、AlInAs、InGaAsP。

As shown in fig. 8A and 8B, in step S120, the layer-to-be-processed structure 180 is processed using an etching process to form a plurality of light modulation elements 20, so as to obtain a chip semi-finished product 200. Specifically, first, an etchable layer 600 is applied on the structure to be processed 180, wherein the etchable layer may be made of a photoresist layer. Next, the etchable layer 600 is exposed through the mask 700 having a preset pattern through a mask to remove a corresponding portion of the etchable layer 600 based on the preset pattern, wherein the remaining etchable layer 600 forms a template 800 having a preset shape and size, wherein the preset shape and size of the template are in conformity with the shape and size of the light modulation element 20. Then, at least a portion of the template 800 and the structure to be processed 180 are removed by an etching process, wherein the remaining structure to be processed 180 has a shape and a size conforming to the template 800 to form the plurality of light modulation elements 20, wherein the plurality of light modulation elements 20 include convex lenses 21 and concave lenses 22.

That is, step S120 includes: applying an etchable layer 600 on the structure to be processed; shaping the etchable material through a mask 700 into a template 800 having a predetermined shape and size, wherein the predetermined shape and size of the template 800 conforms to the shape and size of the light modulation elements 20; and removing at least a portion of the template 800 and the structures to be processed 180 by an etching process, wherein the structures to be processed 180 that remain have a shape and size consistent with the template 800 to form the plurality of light modulation elements 20.

Specifically, the template 800 and a portion of the layer structure to be processed 180 may be removed through a dry etching process or a wet etching process. Accordingly, the remaining layer structure to be processed 180 has a shape and dimensions corresponding to the template 800 to form the light modulation element 20. During the etching process, in order to ensure that the layer structure 180 to be processed, which finally remains, has a shape and dimensions corresponding to the template 800, the etching rate and the etched area should be precisely controlled.

It should be noted that, during the process of removing a portion of the layer-to-be-processed structure 180 by an etching process, at least a portion of the P-type electrical contact layer structure 170 is exposed, so as to form an electrical connection region for electrical connection.

Correspondingly, the semiconductor structure 100 processed by the etching process forms the chip semi-finished product 200, wherein the chip semi-finished product 200 includes, from bottom to top, the substrate layer structure 110, the N-type electrical contact structure 120, the N-DBR structure 130, the active region structure 140, the P-DBR structure 160, the P-type electrical contact structure 170, and the optical modulation element 20.

As shown in fig. 8C, in step S130, a plurality of positive electrical connection terminals 12 electrically connected to the P-type electrical contact layer structure 170 of the chip semi-finished product 200 are formed. Specifically, the positive electrical connection terminal 12 electrically connected to the chip semi-finished product 200 is formed by an electroplating process, wherein the positive electrical connection terminal 12 is formed at an electrical connection region of the P-type electrical contact structure 170 of the chip semi-finished product 200. It should be understood that the positive electrical connection terminal 12 may be formed on the chip blank 200 by other processes, and the application is not limited thereto. It should also be understood that positive electrical connection terminal 12 may be formed at other locations on chip blank 200, and is not intended to be limiting.

Preferably, in order to ensure the light extraction performance of the VCSEL chip, the positive connection terminal 12 electrically connected to the P-type electrical contact structure 170 has a ring structure, and a light extraction hole 103 corresponding to the limiting hole is formed. The ring structure of the positive connection terminal 12 is formed on the periphery of the optical modulation element 20, that is, the optical modulation element 20 is formed in the light exit hole 103 of the VCSEL light emitting unit 10, in such a way that the plurality of optical modulation elements 20 are formed on the laser projection path of the plurality of VCSEL light emitting units 10. The light modulation element 20 is used to modulate the laser light projected by the VCSEL light emitting unit 10 to adjust the overall divergence angle of the VCSEL chip, thereby expanding the scanning area (i.e., the laser light projection range) of the VCSEL chip. It should be understood that the positive electrical connection end 12 may be provided as other types of electrical connection ends.

As shown in fig. 8C, in step S140, at least a portion of the chip semi-finished product 200 is removed to form a plurality of sub-structural units 300 separated from each other, wherein each of the sub-structural units 300 includes, from bottom to top, an N-type electric contact layer 112, an N-DBR layer 113, an active region 114, a P-DBR layer 116, and a P-type electric contact layer 117. Specifically, at least a portion of the chip semi-finished product 200 is removed by an etching process to form a plurality of sub-structural units 300 separated from each other. The separation region between every two substructure units 300 forms an isolation trench 102, so that electrical isolation is achieved between the plurality of substructure units 300.

It is worth mentioning that, in the present embodiment, during the process of removing at least a portion of the chip semi-finished product 200, the substrate layer structure 110 is not separated into a plurality of mutually independent portions. Accordingly, the substrate-layer structure 110 is made of a non-conductive material, so that, despite the substrate-layer structure 110 not being separated into a plurality of mutually independent sections, the plurality of substructure units 300, which are superimposed on the substrate-layer structure 110, can be electrically isolated from one another. That is, after one of the substructure units 300 stacked on the substrate layer structure 110 is turned on, the other substructure units 300 stacked on the substrate layer structure 110 are not turned on accordingly.

Of course, it should be understood that during the process of removing at least a portion of the chip semi-finished product 200, the substrate layer structure 110 may also be spaced apart into a plurality of portions that are independent of each other, that is, at least a portion of the chip semi-finished product 200 is removed to form a plurality of independent structures that are spaced apart from each other. Specifically, each of the independent structures includes, from bottom to top, a substrate layer 111, the N-type electrical contact layer 112, the N-DBR layer 113, the active region 114, the P-DBR layer 116, and the P-type electrical contact layer 117.

As shown in fig. 8D and 8E, in step S150, the plurality of sub-structure units 300 are processed to form a confinement layer 115 having a confinement hole 101 above the active region 114. Specifically, the limiting layer 115 may be formed by an oxidation process, and first, in order to protect the plurality of positive electrical connection terminals 12, a protective layer 900 covering the positive electrical connection terminals 12 is formed before the sub-structural unit 300 is oxidized. Next, the plurality of sub-structural units 300 are oxidized, and after the sub-structural units 300 are oxidized, a portion of the P-DBR layer 116 is oxidized to form the confinement layer 115 over the active region 114. The positive electrical connection end 12 is then exposed, and specifically, the positive electrical connection end 12 may be exposed by removing at least a portion of the protective layer 900 that encapsulates the positive electrical connection end 12. That is, step S150 includes: forming a protective layer 900 covering the plurality of positive electrical connection terminals 12; oxidizing the plurality of substructure units 300; and exposing the positive electrical connection end 12.

It is noted that the confinement layer 115 may be formed by other processes, for example, an ion confinement layer above the active region 114 may be formed by an ion implantation process, which is not limited in this application.

Accordingly, the plurality of substructure units 300 and the substrate layer structure 110 after forming the confinement layer 115 form a plurality of light emitting bodies 11, each of the light emitting bodies 11 including, from bottom to top, a substrate layer 111, the N-type electrical contact layer 112, the N-DBR layer 113, the active region 114, the confinement layer 115, the P-DBR layer 116, and the P-type electrical contact layer 117.

As shown in fig. 8E, in step S160, a plurality of negative electrical connection terminals 13 electrically connected to the plurality of light emitting bodies 11, respectively, are formed. Specifically, in the present embodiment, the negative connection terminal 13 electrically connected to the light emitting body 11 is formed through a plating process. In a specific example of the present application, the negative electrical connection terminal 13 is formed at a side surface of the light emitting body 11.

It should be noted that a single VCSEL light emitting unit 10 may be formed by a single light emitting body 11, the positive electrical connecting terminal 12 and the negative electrical connecting terminal 13 formed on the light emitting body 11, or may be formed by two or more light emitting bodies 11, the positive electrical connecting terminal 12 and the negative electrical connecting terminal 13 formed on the light emitting body 11. That is, each of the VCSEL light emitting units 10 includes at least one light emitting body 11.

In particular, when one VCSEL light emitting unit 10 includes two or more light emitting bodies 11, the positive connection terminals 12 may be formed by forming a first wiring structure on the semiconductor structure 100 in step S130, i.e., in the process of forming a plurality of positive connection terminals 12 electrically connected to the P-type electrical contact layer structure 117 of the chip semi-finished product 200. In step S160, in the process of forming a plurality of negative electrode connection terminals 13 electrically connected to the plurality of light-emitting bodies 11, respectively, the negative electrode connection terminals 13 may be formed by forming a second wiring structure on the light-emitting bodies 11, wherein the second wiring structure has a multi-layer structure.

That is, step S130 includes: forming a first wiring structure electrically connected to the chip semi-finished product; the step S150 includes: and forming a second wiring structure electrically connected to the chip semi-finished product, wherein the second wiring structure has a multilayer structure.

Further, the light emitting body 11, the positive connection terminal 12 and the negative connection terminal 13 form a plurality of VCSEL light emitting units 10 electrically isolated from each other, and the plurality of VCSEL light emitting units 10 and the plurality of light modulation elements 20 form the VCSEL chip, wherein the plurality of light modulation elements 20 are formed on a laser projection path of at least some of the VCSEL light emitting units 10 in the plurality of VCSEL light emitting units 10. The light modulation element 20 is used to modulate the laser light projected by the VCSEL light emitting unit 10 to adjust the overall divergence angle of the VCSEL chip, and to expand the scanning area (i.e., the laser light projection range) of the VCSEL chip.

In summary, a method for manufacturing a VCSEL chip based on an embodiment of the present application is illustrated, which relatively increases an overall divergence angle of the VCSEL chip by designing a structure of the VCSEL chip to expand a scanning area of the VCSEL chip.

The foregoing describes the general principles of the present application in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present application are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present application. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the foregoing disclosure is not intended to be exhaustive or to limit the disclosure to the precise details disclosed.

Claims

1. A VCSEL chip, comprising:

the light modulation elements are integrally arranged on the laser emitting paths of at least part of the VCSEL light emitting units in the VCSEL light emitting units at a wafer level, wherein the light modulation elements have a preset structural configuration and are matched with each other so that the integral divergence angle of the VCSEL chip is larger than or equal to 120 degrees, and the integral divergence angle of the VCSEL chip refers to the included angle formed by the outermost laser in the laser emitted by the VCSEL chip.

2. The VCSEL chip of claim 1, wherein the plurality of light modulation elements have a predetermined structural configuration and cooperate with one another such that an overall divergence angle of the VCSEL chip is equal to 180 °.

3. The VCSEL chip of claim 1, wherein the plurality of light modulating elements comprises concave and convex lenses.

4. The VCSEL chip of claim 3, wherein a portion of the convex lenses and the light emitting bodies corresponding thereto are centered.

5. The VCSEL chip of claim 4, wherein another portion of the convex lens is eccentrically disposed from the light emitting body opposite thereto.

6. The VCSEL chip of claim 5, wherein a portion of the concave lens and the light emitting body corresponding thereto are centered.

7. The VCSEL chip of claim 6, wherein another portion of the concave lenses are disposed off-center from the light emitting bodies corresponding thereto.

8. The VCSEL chip of claim 5, wherein radii of curvature of at least some of the convex lenses are different.

9. The VCSEL chip of claim 1, wherein the light emitting body comprises, in order from bottom to top: the semiconductor device comprises a substrate layer, an N-type electric contact layer, an N-DBR layer, an active region, a limiting layer, a P-DBR layer and a P-type electric contact layer, wherein the limiting layer is provided with a limiting hole corresponding to the active region, the positive electricity connecting end is electrically connected to the P-type electric contact layer, and the negative electricity connecting end is electrically connected to the N-type electric contact layer.

10. The VCSEL chip of claim 9, wherein the substrate layer is made of a non-conductive material.

11. The VCSEL chip of claim 10, wherein the substrate layers of the light emitting hosts of the plurality of VCSEL light emitting units are interconnected to have a unitary structure.

12. The VCSEL chip of claim 9, wherein the positive electrical connection terminal has a ring-shaped structure and forms an optical exit aperture corresponding to the limiting aperture, wherein the optical modulation element is integrally formed within the optical exit aperture in such a manner that the optical modulation element is wafer-level integrally disposed on a laser light exit path of at least some of the VCSEL light-emitting units in the plurality of VCSEL light-emitting units.

13. A method for fabricating a VCSEL chip, comprising:

and forming a plurality of negative electric connection terminals respectively electrically connected to the plurality of light-emitting bodies.

14. The method of claim 13, wherein the processing the layer structure to be processed using an etching process to form a plurality of light modulation elements over the P-type electrical contact layer structure to obtain a chip semi-finished product comprises:

applying an etchable layer on the structure to be processed;

shaping the etchable material through a mask into a template having a predetermined shape and size, wherein the predetermined shape and size of the template conforms to the shape and size of the light modulation elements; and

removing at least a portion of the template and the structure to be processed by an etching process, wherein the structure to be processed that is retained has a shape and dimensions that conform to the template to form the plurality of light modulating elements.

15. The method of claim 13, wherein processing the plurality of sub-structure units by an oxidation process to form an oxidized confinement layer with a confinement aperture over the active region comprises:

forming a protective layer covering the plurality of positive electrical connection terminals;

oxidizing the plurality of sub-structural units; and

exposing the positive electrical connection terminal.