CN116093158A - Trench gate super junction MOSFET and manufacturing method thereof - Google Patents

Trench gate super junction MOSFET and manufacturing method thereof Download PDF

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Publication number
CN116093158A
CN116093158A CN202111313685.1A CN202111313685A CN116093158A CN 116093158 A CN116093158 A CN 116093158A CN 202111313685 A CN202111313685 A CN 202111313685A CN 116093158 A CN116093158 A CN 116093158A
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type semiconductor
conductive type
region
semiconductor doped
trench
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曹荣荣
钟圣荣
钟子期
周东飞
葛景涛
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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Abstract

The invention discloses a trench gate super-junction MOSFET and a manufacturing method thereof, wherein the trench gate super-junction MOSFET comprises a metalized drain, a first conductive type semiconductor doped substrate, a first conductive type semiconductor doped drift region, a second conductive type semiconductor doped column region and the like; the metallized drain electrode is positioned on the back surface of the first conductive type semiconductor doped substrate; the super junction structure is positioned above the first conductive type semiconductor doped substrate; the second conductive type semiconductor body is positioned above the super junction structure; the metalized source electrode is positioned on the surface of the trench gate super junction MOSFET; the upper surface of the second conductivity type semiconductor body is provided with a second conductivity type semiconductor doped contact region. The invention avoids avalanche current passing through the parasitic BJT, so the parasitic BJT can not be started, thereby enhancing the UIS failure resistance of the super junction MOSFET device.

Description

Trench gate super junction MOSFET and manufacturing method thereof
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a trench gate super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a manufacturing method thereof.
Background
The MOSFET power device plays an important role in power conversion, especially in the high-frequency field due to the advantages of high switching speed, small loss, simple driving circuit and the like. Superjunction MOSFETs are one of the important power devices in the art. Referring to fig. 1, the super junction MOSFET includes, in order from bottom to top, a metalized drain 1, a first conductivity type semiconductor doped substrate 2, a first conductivity type semiconductor doped drift region 3, a second conductivity type semiconductor doped column region 4, a second conductivity type semiconductor body region 5, a first conductivity type semiconductor doped source region 6, a second conductivity type semiconductor doped contact region 9, a trench polysilicon gate 8, a gate oxide layer 7, and a metalized source 10. The first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
The basic principle of the super junction MOSFET is charge balance, and the core is that alternating P-type semiconductor columns and N-type semiconductor columns are introduced into a drift region of a traditional MOSFET power device, and adjacent P-type semiconductor columns are contacted with the N-type semiconductor columns to form PN junctions, so that a super junction structure is formed. The super junction MOSFET has low on-resistance and does not affect the switching speed, and compared with the traditional MOSFET, the super junction MOSFET can realize better compromise between the on-resistance and the breakdown voltage, so that the super junction MOSFET is widely applied.
Fig. 1 shows a schematic of the avalanche current path of the superjunction MOSFET. In unclamped inductive load applications, after avalanche breakdown of the superjunction MOSFET device, avalanche current will flow through the second conductivity type semiconductor body region 5 (P-type body region) under the first conductivity type semiconductor doped source region 6 (n+ source region) to the second conductivity type semiconductor doped contact region 9 (p+ source region ohmic contact region). Avalanche current flows through the parasitic BJT (Bipolar Junction Transistor ) and is generated at the base resistor R B Generating a forward voltage drop, when the voltage drop is larger than the forward conduction voltage of the P/N+ junction, the emitter of the parasitic BJT is forward biased and enters a forward amplification working area to amplify avalanche breakdown current, thereby causing a deviceIs burned out by heat.
As system performance continues to increase, reliability is critical to the system application of the power device. When an unclamped inductive load exists in the system loop, the energy stored in the inductor in the on state is released by the power device at the moment of switching off, and meanwhile, the high voltage and the high current applied to the power device are extremely easy to cause the device to fail.
Disclosure of Invention
The invention aims to overcome the defect that a MOSFET power device is easy to fail in an unclamped inductive load circuit in the prior art, and provides a trench gate super-junction MOSFET and a manufacturing method thereof.
The invention solves the technical problems by the following technical scheme:
the invention provides a trench gate super-junction MOSFET, which comprises a metalized drain, a first conductive type semiconductor doped substrate, a first conductive type semiconductor doped drift region, a second conductive type semiconductor doped column region, a second conductive type semiconductor body region, a first conductive type semiconductor doped source region, a second conductive type semiconductor doped contact region, a trench polysilicon gate first region, a trench polysilicon gate second region, a first gate oxide layer, a second gate oxide layer and a metalized source electrode;
the metalized drain is located on the back side of the first conductivity type semiconductor doped substrate,
the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift regions arranged on two sides of the second conductive type semiconductor doped column region form a super junction structure;
the super junction structure is positioned above the first conductive type semiconductor doped substrate;
the second conductive type semiconductor body is positioned above the super junction structure;
the side surface and the bottom of the first region of the groove polysilicon gate are surrounded by the first gate oxide layer, and the side surface and the bottom of the second region of the groove polysilicon gate are surrounded by the second gate oxide layer; the second conductive type semiconductor body region is divided into three parts by the first gate oxide layer and the second gate oxide layer; the lower surface of the first gate oxide layer is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region at one side thereof, the lower surface of the second gate oxide layer is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region at the other side thereof,
a first conductive type semiconductor doping source region is arranged in a region of the first conductive type semiconductor body region corresponding to the first conductive type semiconductor doping drift region;
the metalized source electrode is positioned on the surface of the trench gate super junction MOSFET;
the upper surface of the second conductivity type semiconductor body is provided with a second conductivity type semiconductor doped contact region.
Preferably, a first conductive type semiconductor doped buried layer is arranged in the first conductive type semiconductor doped drift region, and a second conductive type semiconductor doped buried layer is arranged in the second conductive type semiconductor doped column region;
the doping concentration of the first conductive type semiconductor doping buried layer is larger than the doping concentration of the first conductive type semiconductor doping drift region, and the doping concentration of the second conductive type semiconductor doping buried layer is larger than the doping concentration of the second conductive type semiconductor doping column region;
the upper surface of the first conductive type semiconductor doped buried layer is lower than the lower surface of the first gate oxide layer, the upper surface of the first conductive type semiconductor doped buried layer is lower than the lower surface of the second gate oxide layer, the upper surface of the second conductive type semiconductor doped buried layer is lower than the lower surface of the first gate oxide layer, and the upper surface of the second conductive type semiconductor doped buried layer is lower than the lower surface of the second gate oxide layer.
Preferably, the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor.
The invention also provides a manufacturing method of the trench gate super junction MOSFET, which comprises the following steps:
forming a first conductive type semiconductor doped substrate;
forming a super junction structure above the first conductive type semiconductor doped substrate, wherein the super junction structure comprises a second conductive type semiconductor doped column region and first conductive type semiconductor doped drift regions arranged on two sides of the second conductive type semiconductor doped column region;
forming a second conductive type semiconductor body region above the super junction structure;
etching the second conductive type semiconductor body region to form a first trench and a second trench, wherein the bottom of the first trench is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region at one side of the first trench, and the bottom of the second trench is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region at the other side of the second trench;
and manufacturing a first gate oxide layer in the first groove, manufacturing a second gate oxide layer in the second groove, manufacturing a first groove polysilicon gate region in the first groove, and manufacturing a second groove polysilicon gate region in the second groove.
Preferably, the manufacturing method further comprises the steps of:
forming a first conductive type semiconductor doped buried layer in the first conductive type semiconductor doped drift region, and forming a second conductive type semiconductor doped buried layer in the second conductive type semiconductor doped column region, wherein the doping concentration of the first conductive type semiconductor doped buried layer is greater than that of the first conductive type semiconductor doped drift region, and the doping concentration of the second conductive type semiconductor doped buried layer is greater than that of the second conductive type semiconductor doped column region; the upper surface of the first-conductivity-type semiconductor doped buried layer is lower than the bottom surface of the first trench, the upper surface of the first-conductivity-type semiconductor doped buried layer is lower than the bottom surface of the second trench, the upper surface of the second-conductivity-type semiconductor doped buried layer is lower than the bottom surface of the first trench, and the upper surface of the second-conductivity-type semiconductor doped buried layer is lower than the bottom surface of the second trench.
Preferably, the manufacturing method further comprises the steps of:
a first conductivity type semiconductor dopant source region is formed within the second conductivity type semiconductor body region corresponding to the first conductivity type semiconductor dopant drift region.
Preferably, the manufacturing method further comprises the steps of:
and forming a second conductive type semiconductor doped contact region above the second conductive type semiconductor body region.
Preferably, the manufacturing method further comprises the steps of:
and manufacturing and forming a metalized source electrode and a metalized drain electrode.
The invention has the positive progress effects that: the invention avoids avalanche current passing through the parasitic BJT, so the parasitic BJT can not be started, thereby enhancing the anti-UIS (Unclamped Inductive Switching, unclamped inductive switch) failure capability of the super junction MOSFET device.
Drawings
Fig. 1 is a schematic diagram of a prior art super junction MOSFET structure and avalanche current path.
Fig. 2 is a flow chart of a method of fabricating a trench gate superjunction MOSFET in accordance with a preferred embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a trench-gate superjunction MOSFET according to a preferred embodiment of the present invention.
Fig. 4 is a schematic diagram of an avalanche current path of a trench gate superjunction MOSFET in accordance with a preferred embodiment of the present invention.
Detailed Description
The invention is further illustrated by the following preferred embodiment, but is not thereby limited to the described embodiment.
Example 1
The embodiment provides a manufacturing method of a trench gate super junction MOSFET. Referring to fig. 2 and 3, the method for manufacturing the trench gate super junction MOSFET includes the following steps:
step S101, manufacturing and forming a first conductivity type semiconductor doped substrate. In this step, the first conductivity type semiconductor doped substrate 2 is formed.
Step S102, a super junction structure is formed above the first conductive type semiconductor doped substrate. The super junction structure includes a second conductivity type semiconductor doped column region 4 and first conductivity type semiconductor doped drift regions 3 disposed at both sides of the second conductivity type semiconductor doped column region.
Step S103, a first conductive type semiconductor doped buried layer is formed in the first conductive type semiconductor doped drift region, and a second conductive type semiconductor doped buried layer is formed in the second conductive type semiconductor doped column region. The doping concentration of the first-conductivity-type semiconductor doping buried layer 31 is greater than the doping concentration of the first-conductivity-type semiconductor doping drift region 3, and the doping concentration of the second-conductivity-type semiconductor doping buried layer 41 is greater than the doping concentration of the second-conductivity-type semiconductor doping column region 4. The upper surface of the first-conductivity-type semiconductor-doped buried layer 31 is lower than the bottom surface of the first trench 21, the upper surface of the first-conductivity-type semiconductor-doped buried layer 31 is lower than the bottom surface of the second trench 22, the upper surface of the second-conductivity-type semiconductor-doped buried layer 41 is lower than the bottom surface of the first trench 21, and the upper surface of the second-conductivity-type semiconductor-doped buried layer 41 is lower than the bottom surface of the second trench 22. In some alternative embodiments, the first trench 21 and the second trench 22 are formed in a subsequent step for fabricating a gate oxide layer and a trench polysilicon gate.
Step S104, a second conductive type semiconductor body region is formed above the super junction structure. In this step, a second conductivity type semiconductor body 5 is formed over the superjunction structure.
Step S105, etching the second conductivity type semiconductor body to form a first trench and a second trench. The bottom of the first trench 21 is in contact with the second-conductivity-type semiconductor-doped column region 4 and the first-conductivity-type semiconductor-doped drift region 3 on one side thereof, and the bottom of the second trench 22 is in contact with the second-conductivity-type semiconductor-doped column region 4 and the first-conductivity-type semiconductor-doped drift region 3 on the other side thereof. The first trench 21 and the second trench 22 divide the second conductivity type semiconductor body 5 into three parts.
Step S106, manufacturing a first gate oxide layer in the first groove, manufacturing a second gate oxide layer in the second groove, manufacturing a first region of the groove polysilicon gate in the first groove, and manufacturing a second region of the groove polysilicon gate in the second groove. In this step, a first gate oxide 71 is formed in the first trench 21, a second gate oxide 72 is formed in the second trench 22, a first region 81 of trench polysilicon gate is formed in the first trench 21, and a second region 82 of trench polysilicon gate is formed in the second trench 22.
Step S107, forming a first conductivity type semiconductor doping source region in the second conductivity type semiconductor body region corresponding to the first conductivity type semiconductor doping drift region. In this step, a first conductivity type semiconductor doping source region 6 is formed in the second conductivity type semiconductor body region 5 corresponding to the first conductivity type semiconductor doping drift region 3 on one side thereof, the first conductivity type semiconductor doping source region 6 being adjacent to the first trench 21; a first-conductivity-type semiconductor doping source region 6 is formed in the second-conductivity-type semiconductor body region 5 corresponding to the first-conductivity-type semiconductor doping drift region 3 on the other side, the first-conductivity-type semiconductor doping source region 6 being adjacent to the second trench 22.
And S108, manufacturing and forming a second conductive type semiconductor doped contact region above the second conductive type semiconductor body region. In this step, a second conductivity type semiconductor doped contact region 9 is formed over the second conductivity type semiconductor body 5.
Step S109, a metalized source electrode and a metalized drain electrode are manufactured and formed. In this step, a metalized source 10 and a metalized drain 1 are formed.
The first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor.
The present embodiment also provides a trench gate superjunction MOSFET, which is manufactured by using the manufacturing method of the trench gate superjunction MOSFET of the present embodiment, and the structure of which is shown in fig. 3. The trench gate superjunction MOSFET comprises a metalized drain 1, a first conductive type semiconductor doped substrate 2, a first conductive type semiconductor doped drift region 3, a second conductive type semiconductor doped column region 4, a second conductive type semiconductor body region 5, a first conductive type semiconductor doped source region 6, a second conductive type semiconductor doped contact region 9, a trench polysilicon gate first region 81, a trench polysilicon gate second region 82, a first gate oxide layer 71, a second gate oxide layer 72 and a metalized source 10; the metallized drain electrode 1 is positioned on the back surface of the first conductive type semiconductor doped substrate 2, the second conductive type semiconductor doped column region 4 and the first conductive type semiconductor doped drift regions 3 arranged on two sides of the second conductive type semiconductor doped column region 4 form a super junction structure; the super junction structure is positioned above the first conductive type semiconductor doped substrate 2; the second conductivity type semiconductor body 5 is located above the superjunction structure; the side and bottom of the trench polysilicon gate first region 81 are surrounded by the first gate oxide layer 71 and the side and bottom of the trench polysilicon gate second region 82 are surrounded by the second gate oxide layer 72; the second conductivity type semiconductor body 5 is divided into three parts by the first gate oxide layer 71, the second gate oxide layer 72; the lower surface of the first gate oxide layer 71 is in contact with the second conductivity type semiconductor doping and drifting region 4 and the first conductivity type semiconductor doping and drifting region 3 on one side thereof, the lower surface of the second gate oxide layer 72 is in contact with the second conductivity type semiconductor doping and drifting region 4 and the first conductivity type semiconductor doping and drifting region 3 on the other side, and the first conductivity type semiconductor doping source region 6 is arranged in a region of the first conductivity type semiconductor body region corresponding to the first conductivity type semiconductor doping and drifting region 3; the metalized source electrode 10 is positioned on the surface of the trench gate superjunction MOSFET; the upper surface of the second conductivity type semiconductor body 5 is provided with a second conductivity type semiconductor doped contact region 9.
A first-conductivity-type semiconductor doped buried layer 31 is arranged in the first-conductivity-type semiconductor doped drift region 3, and a second-conductivity-type semiconductor doped buried layer 41 is arranged in the second-conductivity-type semiconductor doped column region 4; the doping concentration of the first-conductivity-type semiconductor doping buried layer 31 is greater than the doping concentration of the first-conductivity-type semiconductor doping drift region 3, and the doping concentration of the second-conductivity-type semiconductor doping buried layer 41 is greater than the doping concentration of the second-conductivity-type semiconductor doping column region 4. The upper surface of the first-conductivity-type semiconductor-doped buried layer 31 is lower than the lower surface of the first gate oxide layer 71, the upper surface of the first-conductivity-type semiconductor-doped buried layer 31 is lower than the lower surface of the second gate oxide layer 72, the upper surface of the second-conductivity-type semiconductor-doped buried layer 41 is lower than the lower surface of the first gate oxide layer 71, and the upper surface of the second-conductivity-type semiconductor-doped buried layer 41 is lower than the lower surface of the second gate oxide layer 72. The first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
The working principle of the trench gate superjunction MOSFET of the present embodiment is: in the conduction mode, the electrode connection mode of the trench gate super junction MOSFET is as follows: the metalized source 10 is connected to a low potential, the metalized drain 1 is connected to a high potential, and the trench polysilicon gate electrode (the trench polysilicon gate first region 81 and the trench polysilicon gate second region 82) is connected to a high potential. When the forward bias voltage applied to the trench polysilicon gate electrode reaches the threshold voltage, an inversion channel is formed in the second conductivity type semiconductor body region 5 (P-type body region) near the sidewall of the trench polysilicon gate electrode, and electrons are injected into the first conductivity type semiconductor doped drift region 3 (N-type drift region) from the first conductivity type semiconductor doped source region 6 (n+ source region) through the inversion channel in the second conductivity type semiconductor body region 5 (P-type body region), forming forward conduction current. In the blocking mode, the electrode connection mode of the trench gate super junction MOSFET is as follows: the metalized source electrode 10 is connected with low potential, the metalized drain electrode 1 is connected with high potential, the grooved polysilicon gate electrode is connected with low potential, PN junctions formed by the second conductive type semiconductor body region 5 (P-type body region) and the second conductive type semiconductor doped column region 4 (P-type column region) and the first conductive type semiconductor doped drift region 3 (N-type drift region) are exhausted, and the depletion region bears withstand voltage.
FIG. 4 shows an avalanche current path diagram of the trench gate superjunction MOSFET of the present embodiment, wherein R B And characterizing the base resistance. The first conductive type semiconductor doped drift region 3 (N-type drift region) of the structure is internally provided with a first conductive type semiconductor doped buried layer 31 (N-type buried layer), and the doping concentration of the first conductive type semiconductor doped buried layer 31 (N-type buried layer) is higher than that of the first conductive type semiconductor doped drift region 3 (N-type drift region) to form a hole barrier region; the second conductivity type semiconductor doped column region 4 (P-type column region) has therein a second conductivity type semiconductor doped buried layer 41 (P-type buried layer), and the second conductivity type semiconductor doped buried layer 41 (P-type buried layer) has a higher doping concentration than the second conductivity type semiconductor doped column region 4 (P-type column region) to form a hole potential well region. When the device is in avalanche, holes are blocked by the hole barrier region and enter the P-type column region, due to the hole potentialThe well region, after the hole enters the P-type buried layer, rapidly flows to the source electrode through the P-type body region between the grooved polysilicon gate electrodes, and avalanche current is prevented from passing through the parasitic BJT, so that the parasitic BJT cannot be started, and the UIS failure resistance of the super-junction MOSFET device is enhanced.
Compared with the traditional trench gate superjunction MOSFET, the trench gate superjunction MOSFET has the advantages that the source electrode of hole current flowing out is arranged between the trench gates and is far away from the parasitic BJT, the N-type buried layer is arranged in the N-type drift region to form a hole barrier region, the P-type buried layer is arranged in the P-type drift region to form a hole potential well region, holes enter the P-type column region and flow out from the source electrode between the trench gates, and based on the technical means, the flow path of avalanche breakdown current is finally enabled to avoid the base resistance of the parasitic BJT, and further the parasitic BJT is prevented from being started when the device is subjected to avalanche breakdown, so that the UIS failure resistance of the superjunction MOSFET device is enhanced, and the reliability of the superjunction MOSFET device in non-clamping inductance load application is improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims (9)

1. The trench gate super-junction MOSFET is characterized by comprising a metalized drain, a first conductive type semiconductor doped substrate, a first conductive type semiconductor doped drift region, a second conductive type semiconductor doped column region, a second conductive type semiconductor body region, a first conductive type semiconductor doped source region, a second conductive type semiconductor doped contact region, a trench polysilicon gate first region, a trench polysilicon gate second region, a first gate oxide layer, a second gate oxide layer and a metalized source electrode;
the metalized drain is located on the back side of the first conductivity type semiconductor doped substrate,
the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift regions arranged on two sides of the second conductive type semiconductor doped column region form a super junction structure;
the super junction structure is positioned above the first conductive type semiconductor doped substrate;
the second conductive type semiconductor body region is positioned above the super junction structure;
the side surface and the bottom of the first region of the groove polysilicon gate are surrounded by the first gate oxide layer, and the side surface and the bottom of the second region of the groove polysilicon gate are surrounded by the second gate oxide layer; the second conductive type semiconductor body region is divided into three parts by the first gate oxide layer and the second gate oxide layer; the lower surface of the first gate oxide layer is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region at one side of the second gate oxide layer, and the lower surface of the second gate oxide layer is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region at the other side of the second gate oxide layer;
the first conductive type semiconductor doping source region is arranged in a region of the first conductive type semiconductor body region corresponding to the first conductive type semiconductor doping drift region;
the metalized source electrode is positioned on the surface of the trench gate superjunction MOSFET;
the upper surface of the second conductive type semiconductor body region is provided with the second conductive type semiconductor doped contact region.
2. The trench-gate superjunction MOSFET of claim 1, wherein a first conductivity type semiconductor doped buried layer is disposed within the first conductivity type semiconductor doped drift region, and a second conductivity type semiconductor doped buried layer is disposed within the second conductivity type semiconductor doped column region;
the doping concentration of the first conductive type semiconductor doping buried layer is larger than the doping concentration of the first conductive type semiconductor doping drift region, and the doping concentration of the second conductive type semiconductor doping buried layer is larger than the doping concentration of the second conductive type semiconductor doping column region;
the upper surface of the first conductive type semiconductor doped buried layer is lower than the lower surface of the first gate oxide layer, the upper surface of the first conductive type semiconductor doped buried layer is lower than the lower surface of the second gate oxide layer, the upper surface of the second conductive type semiconductor doped buried layer is lower than the lower surface of the first gate oxide layer, and the upper surface of the second conductive type semiconductor doped buried layer is lower than the lower surface of the second gate oxide layer.
3. The trench-gate superjunction MOSFET of claim 1 or 2, wherein said first conductivity type semiconductor is an N-type semiconductor and said second conductivity type semiconductor is a P-type semiconductor.
4. The manufacturing method of the trench gate super junction MOSFET is characterized by comprising the following steps of:
forming a first conductive type semiconductor doped substrate;
forming a super junction structure above the first conductive type semiconductor doped substrate, wherein the super junction structure comprises a second conductive type semiconductor doped column region and first conductive type semiconductor doped drift regions arranged on two sides of the second conductive type semiconductor doped column region;
forming a second conductive type semiconductor body region above the super junction structure;
etching the second conductive type semiconductor body region to form a first trench and a second trench, wherein the bottom of the first trench is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region on one side thereof, and the bottom of the second trench is in contact with the second conductive type semiconductor doped column region and the first conductive type semiconductor doped drift region on the other side thereof;
and manufacturing a first gate oxide layer in the first groove, manufacturing a second gate oxide layer in the second groove, manufacturing a first region of the groove polysilicon gate in the first groove, and manufacturing a second region of the groove polysilicon gate in the second groove.
5. The method of manufacturing a trench gate superjunction MOSFET of claim 4, further comprising the steps of:
forming a first conductive type semiconductor doped buried layer in the first conductive type semiconductor doped drift region, forming a second conductive type semiconductor doped buried layer in the second conductive type semiconductor doped column region, wherein the doping concentration of the first conductive type semiconductor doped buried layer is larger than that of the first conductive type semiconductor doped drift region, the doping concentration of the second conductive type semiconductor doped buried layer is larger than that of the second conductive type semiconductor doped column region, the upper surface of the first conductive type semiconductor doped buried layer is lower than the bottom surface of the first groove, the upper surface of the first conductive type semiconductor doped buried layer is lower than the bottom surface of the second groove, the upper surface of the second conductive type semiconductor doped buried layer is lower than the bottom surface of the first groove, and the upper surface of the second conductive type semiconductor doped buried layer is lower than the bottom surface of the second groove.
6. The method of manufacturing a trench gate superjunction MOSFET of claim 5, further comprising the steps of:
a first conductivity type semiconductor dopant source region is formed within the second conductivity type semiconductor body region corresponding to the first conductivity type semiconductor dopant drift region.
7. The method of manufacturing a trench gate superjunction MOSFET of claim 6, further comprising the steps of:
and forming a second conductive type semiconductor doped contact region above the second conductive type semiconductor body region.
8. The method of manufacturing a trench gate superjunction MOSFET of claim 7, further comprising the steps of:
and manufacturing and forming a metalized source electrode and a metalized drain electrode.
9. The method of manufacturing a trench gate superjunction MOSFET according to any of claims 4-8, wherein said first conductivity type semiconductor is an N-type semiconductor and said second conductivity type semiconductor is a P-type semiconductor.
CN202111313685.1A 2021-11-08 2021-11-08 Trench gate super junction MOSFET and manufacturing method thereof Pending CN116093158A (en)

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