CN116093070A - Semiconductor packaging structure and forming method thereof - Google Patents

Semiconductor packaging structure and forming method thereof Download PDF

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Publication number
CN116093070A
CN116093070A CN202111288436.1A CN202111288436A CN116093070A CN 116093070 A CN116093070 A CN 116093070A CN 202111288436 A CN202111288436 A CN 202111288436A CN 116093070 A CN116093070 A CN 116093070A
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China
Prior art keywords
layer
dielectric layer
package structure
substrate
reflective
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CN202111288436.1A
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Chinese (zh)
Inventor
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202111288436.1A priority Critical patent/CN116093070A/en
Publication of CN116093070A publication Critical patent/CN116093070A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices

Abstract

The invention relates to a semiconductor packaging structure and a forming method thereof. The semiconductor package structure includes: a substrate; the circuit layer is positioned on the substrate, and a reflecting layer is arranged on part of the side wall of the circuit layer; the optical fiber array is arranged opposite to the reflecting layer interval; an optical integrated circuit is partially over the wiring layer and a portion of a lower surface of the optical integrated circuit is over the reflective layer to form an optical transmission path between the optical fiber array and the portion of the lower surface of the optical integrated circuit via the reflective layer.

Description

Semiconductor packaging structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor package structure and a method for forming the same.
Background
In a silicon-on-silicon (si-ph) package, as shown in fig. 1, an optical Fiber Array (FAU) 12 and an optical integrated circuit (PIC) 14 are disposed on a surface of a substrate 20, and light guide (WG) components 18 of the FAU 12 and the PIC 14 are optically coupled by a reflective element 16 (e.g., a mirror). There is a large open space between FAU 12 and PIC 14. Due to environmental concerns, some particles (particles) adhere to the reflective element 16, which affects the accuracy of the direction of the coupling path, resulting in poor coupling efficiency. In addition, it is also desirable to further integrate the reflective element with the silicon light package structure.
Disclosure of Invention
In view of the above-mentioned problems in the related art, the present invention provides a semiconductor package structure and a method for forming the same.
According to an aspect of an embodiment of the present invention, there is provided a semiconductor package structure including: a substrate; the circuit layer is positioned on the substrate, and a reflecting layer is arranged at part of the side wall of the circuit layer; the optical fiber array is arranged opposite to the reflecting layer interval; an optical integrated circuit is positioned above the circuit layer, and a portion of a lower surface of the optical integrated circuit is positioned above the reflective layer to form an optical transmission path between the optical fiber array and the portion of the lower surface of the optical integrated circuit via the reflective layer.
In some embodiments, a protrusion is also provided at a portion of the lower surface of the optical integrated circuit, the protrusion being located above the space between the reflective layer and the array of optical fibers.
In some embodiments, a spacing between the lower surface of the protrusion and the substrate is less than a spacing between the lower surface of the optical integrated circuit and the substrate.
In some embodiments, an underfill is also included, and the underfill is further disposed between the optical integrated circuit and the wiring layer.
In some embodiments, the reflective layer of the wiring layer is a metal material.
In some embodiments, the sidewalls of the wiring layer covered by the reflective layer form an acute angle with the substrate under the wiring layer.
In some embodiments, the circuit layer includes a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, and the reflective layer is disposed on a sidewall of the second dielectric layer.
In some embodiments, the array of optical fibers is located on the first dielectric layer.
In some embodiments, a light guide member is provided at a portion of the lower surface of the optical integrated circuit, with the surface of the light guide member exposed by the underfill being located above the reflective layer.
In some embodiments, a portion of the sidewalls of the wiring layer are sloped, and the reflective layer is disposed along the sloped portion of the sidewalls.
Drawings
The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a schematic diagram of a conventional semiconductor package structure.
Fig. 2a is a schematic diagram of a semiconductor package according to an embodiment of the invention.
Fig. 2b is a partially enlarged view of a region A1 of the semiconductor package structure shown in fig. 2 a.
Fig. 3a to 5c are schematic views of semiconductor package structures according to other embodiments of the present invention.
Fig. 6 a-6 p are schematic diagrams illustrating various stages of a method of forming a semiconductor package according to an embodiment of the invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The embodiment of the invention provides a semiconductor packaging structure. Fig. 2a is a schematic diagram of a semiconductor package according to an embodiment of the present invention. As shown in fig. 2a, the semiconductor package structure includes a substrate 210. In some embodiments, the thickness of the substrate 210The degree is in the range of 20 μm to 200 μm. In some embodiments, the substrate 210 may include an organic material, such as Polyimide (PI), epoxy (Epoxy), acryl (Acrylic), a laminate film (ABF), or the like. In some embodiments, the substrate 210 may include an inorganic material, such as an oxide (e.g., siO x 、SiN x 、TaO x ) Glass, silicon, ceramic, etc. In some embodiments, the substrate 210 may include an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material.
The wiring layer 220 and the FAU250 are disposed on the substrate 210. A reflective layer 230 is disposed on a portion of the sidewalls of the wiring layer 220. The FAU250 is spaced from and disposed opposite the reflective layer 230. The PIC 240 also extends above the space between the FAU250 and the reflective layer 230 such that a portion of the lower surface of the PIC 240 is above the wiring layer 220.
A reflective layer 230 is provided on a portion of the sidewall of the wiring layer 220 so that an optical transmission path PG may be formed between the FAU250 and the lower surface of the PIC 240 via the reflective layer 230. Specifically, light from the FAU250 reaches the reflective layer 230 along the light transmission path PG, and then light from the FAU250 is reflected by the reflective layer 230 to the PIC 240 along the light transmission path PG. Or vice versa, light from the PIC 240 reaches the reflective layer 230 along the light transmission path PG, and the light is then reflected by the reflective layer 230 along the light transmission path PG and transmitted to the FAU 250.
In the semiconductor package structure of the present invention, the reflective layer 230 is formed by using the sidewall of the circuit layer 220, and the optical transmission path PG is formed through the reflective layer 230, so that light is transmitted between the FAU250 and the PIC 240 through the reflective layer 230. Further structural integration of the reflective element and the silicon optical package structure is realized.
In some embodiments, a light guide member 241 is provided at a portion of the lower surface of the PIC 240, the light guide member 241 being suspended above the reflective layer 230. The PIC 240 receives the light reflected by the reflective layer through the light guide member 241. In some embodiments, the light guide 241 may be a grating (ras). In other embodiments, light may be output or received by other components of the PIC 240.
In some embodiments, the reflective layer 230 is a metallic material. The reflective layer 230 of the metal material may be used for reflection only and may not be electrically connected with the wiring layer 220. In some embodiments, the reflective layer 230 may be formed by a process such as sputtering, evaporation, electroplating, electroless plating, or the like.
With continued reference to fig. 2a, the wiring layer 220 includes a first dielectric layer 221 on the substrate 210, a second dielectric layer 223 on the first dielectric layer 221, and a third dielectric layer 225 on the second dielectric layer 223. In some embodiments, the first, second and third dielectric layers 221, 223 and 225 may be formed of an organic material, such as Polyimide (PI), epoxy (Epoxy), acryl (Acrylic), laminated film (ABF), etc., and may be formed of an inorganic material, such as an oxide (e.g., siO x 、SiN x 、TaO x ) Glass, silicon, ceramic, etc., or an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material. In some embodiments, the thickness of each of the first dielectric layer 221, the second dielectric layer 223, and the third dielectric layer 225 of the wiring layer 220 is in the range of 5 μm to 20 μm. In some embodiments, the lines within the line layer 220 are fine lines, the line widths/pitches L/S of the lines<2μm/2μm。
The first dielectric layer 221 may cover the upper surface of the substrate 210. The size of the first dielectric layer 221 is larger than the size of the second dielectric layer 223 such that a portion of the upper surface of the first dielectric layer 221 is exposed by the second dielectric layer 223. The FAU250 is located on the upper surface of the first dielectric layer 221 exposed by the second dielectric layer 223. The FAU250 may be disposed adjacent to an edge of the first dielectric layer 221. In some embodiments, the FAU250 is attached to the first dielectric layer 221 by an adhesive layer 252. In some embodiments, the thickness of the adhesive layer 252 is in the range of 10 μm to 50 μm. In some embodiments, the adhesion layer 252 may be formed of an organic material, such as Polyimide (PI), epoxy (Epoxy), acryl (Acrylic), laminate film (ABF), or the like, or may be formed of an inorganic material, such as an oxide (e.g., siO x 、SiN x 、TaO x ) Glass, silicon, ceramic, etc. In some embodiments of the present invention, in some embodiments,the adhesive layer 252 may be an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material.
The second dielectric layer 223 may have a size greater than that of the third dielectric layer 225. The second dielectric layer 223 has sloped sidewalls 222. The side wall 222 is located below the light guide member 241. The reflective layer 230 is disposed along the sloped sidewall 222 such that the reflective layer 230 has a sloped surface for reflecting light to reflect light from the FAU250 to the light guide component 241 of the PIC 240.
Further, an Electrical Integrated Circuit (EIC) 280 is disposed above the wiring layer 220. In some embodiments, the size (width) of EIC 280 is in the range of 10 μm to 1000 μm. The thickness of EIC 280 is in the range of 20 μm to 100 μm. In some embodiments, the width of the PIC 240 is in the range of 10 μm to 1000 μm. The thickness of the PIC 240 is in the range of 20 μm to 100 μm. EIC 280 and PIC 240 may be connected to wiring layer 220 by bump connections 247, respectively. In some embodiments, bump connectors 247 have diameters in the range of 10 μm to 30 μm and a pitch (pitch) between bump connectors 247 in the range of 15 μm to 60 μm.
An underfill 270 is disposed between EIC 280 and wiring layer 220, and between PIC 240 and wiring layer 220. In some embodiments, the underfill 270 may be formed of an organic material, such as Polyimide (PI), epoxy, acryl (Acrylic), laminate film (ABF), or the like. In some embodiments, the underfill 270 may be formed of an inorganic material, such as an oxide (e.g., siO x 、SiN x 、TaO x ) Glass, silicon, ceramic, etc. In some embodiments, the underfill 270 may be an organic photosensitive liquid material, an organic non-photosensitive liquid material, an organic photosensitive dry film material, or an organic non-photosensitive dry film material. The lower surface of the substrate 210 is provided with solder balls 285. In some embodiments, the diameter of the solder balls 285 is in the range of 30 μm to 200 μm and the pitch between the solder balls 285 is in the range of 50 μm to 400 μm.
Fig. 2b is a partially enlarged view of a region A1 of the semiconductor package structure shown in fig. 2 a. As shown in connection with fig. 2a and 2b, an inclined sidewall 222 of the second dielectric layer 223 forms an inclination angle θ with the horizontal surface. In some embodiments, the tilt angle θ is in the range of 10 ° to 80 °. And covers the sidewall 222, and accordingly, the angle formed by the surface of the reflective layer 230 for reflecting light and the horizontal surface is also in the range of 10 ° to 80 °.
Specifically, the second dielectric layer 223 of the circuit layer 220 has a circuit 228 therein. The line 228 is comprised of a seed layer 232 and a conductive layer 234 on the seed layer 232. In the illustrated embodiment, the reflective layer 230 may be formed from a seed layer 232 and a conductive layer 234 used to form the wiring 228. The reflective layer 230 may not be electrically connected to the traces (e.g., trace 228) in the trace layer 220. The reflective layer 230 may include a lateral portion extending over a portion of the upper surface of the second dielectric layer 223, and an upper surface of the lateral portion of the reflective layer 230 on the second dielectric layer 223 may be coplanar with an upper surface of the wiring 228. The reflective layer 230 also extends from the top end of the sidewall 222 to the bottom end of the sidewall 222 and also continues onto a portion of the upper surface of the first dielectric layer 221.
Further, a protrusion 260 may be provided at the lower surface 244 of the PIC 240, and the protrusion 260 protrudes from the lower surface 244 of the PIC 240 and the lower surface of the light guiding member 241 to extend downward above the space between the reflective layer 230 and the FAU 250. The spacing between the lower surface of the protrusion 260 and the substrate 210 is less than the spacing between the lower surface of the PIC 240 and the substrate 210. Tab 260 may be engaged to lower surface 244 of PIC 240 by bump connector 247.
By providing the protruding portion 260 above the interval between the reflective layer 230 and the FAU250, the space through which the entire optical transmission path PG passes is reduced, thereby forming a Micro-channel (Micro-channel) for passing the optical transmission path PG from the FAU250 to the PI 240. The protrusion 260 and the upper surface of the first dielectric layer 221 define a height CH of the micro-channel. In some embodiments, the height CH of the micro-channels is defined in the range of 5 μm to 50 μm. By reducing the space through which the light transmission path PG passes, the content of particles in the space is reduced, the negative influence of particles in the environment on the light coupling efficiency is reduced, and the reduction of the light coupling efficiency caused by the particles is avoided.
Specifically, the tab 260 includes a dielectric layer 265. In some embodiments, the material of dielectric layer 265 may be the same as the material of third dielectric layer 225 of wiring layer 220 and may be formed in the same process step. Dielectric layer 265 is connected to lower surface 244 of PIC 240 by bump connector 247.
The sidewalls of dielectric layer 265 are sloped so that the width of dielectric layer 265 gradually increases in a downward direction from lower surface 244 of PIC 240. Also, the side wall of the third dielectric layer 225 opposite to the protruding portion 260 is inclined so that the space defined by the protruding portion 260 is gradually reduced in a downward direction from the light guide member 241.
The third dielectric layer 225 of the wiring layer 220 has a wiring 229 therein. The line 229 is comprised of a seed layer 262 and a conductive layer 264 on the seed layer 262. In this embodiment, an additional reflective layer 230' is also formed on the sidewalls of the third dielectric layer 225. The reflective layer 230' is formed from a seed layer 262 and a conductive layer 264 used to form the lines 229. The third dielectric layer 225 may cover an end of the reflective layer 230. The reflective layer 230' may extend from the top to the bottom of the sloped sidewalls of the third dielectric layer 225. The reflective layer 230' may also extend onto a portion of the upper surface of the third dielectric layer 225, and may extend onto a portion of the upper surface of the reflective layer 230.
In some embodiments, the protrusion 260 may further include a seed layer 262 and a conductive layer 264 on the dielectric layer 265. The seed layer 262 and the conductive layer 264 may be formed on sloped sidewalls of the dielectric layer 265 and may also be formed on a portion of the upper surface of the dielectric layer 265. Seed layer 262 and conductive layer 264 may also be disposed between bump connector 247 and dielectric layer 265 to connect bump connector 247 with dielectric layer 265.
An underfill 270 may be disposed between the lower surface 244 of the PIC 240 and the tab 260 and around the bump connector 247. The underfill 270 covers the sidewalls of the light guide member 241 and may expose a portion of the lower surface of the light guide member 241 to receive light reflected via the reflective layer 230.
Fig. 3a and 3b are schematic views of semiconductor package structures according to other embodiments of the present invention. As shown in fig. 3a and 3b, a molding compound 290 encapsulating the PIC 240, and the underfill 270 may be formed on the wiring layer 220. In the embodiment shown in fig. 3a, the molding compound 290 may have vertical sidewalls and a flat upper surface connected between the vertical sidewalls. The molding compound 290 covers the upper surfaces of the EIC 280 and the PIC 240. The molding compound 290 exposes the FAU250 and the space between the FAU250 and the tab 260. The bottom surface of the molding compound 290 may be lower than the bottom surface of the light guide member 241 and expose a portion of the bottom surface of the light guide member 241 to receive the light reflected by the reflective layer 230. In the embodiment shown in fig. 3b, the molding compound 290 may be formed, for example, by a dispensing process and has an upwardly convex curved surface profile. In such embodiments, the molding compound 290 may expose portions of the surfaces and/or sidewalls of the EIC 280 and/or the PIC 240.
Fig. 4 is a schematic view of a semiconductor package structure according to other embodiments of the present invention. In the embodiment shown in fig. 4, the tab 260 may not be provided on the lower surface of the PIC 240. Accordingly, a bump connector for connecting the protrusion 260 and an underfill surrounding the bump connector are not provided above the space between the FAU250 and the reflective layer 230. In this embodiment, the sidewalls of the FAU250 adjacent to the reflective layer 230 may extend below the PIC 240.
Fig. 5a to 5c are schematic views of semiconductor package structures according to other embodiments of the present invention. In the embodiment shown in fig. 5a, the reflective layer 230 extends continuously from the top end of the sidewall of the third dielectric layer 225 of the wiring layer 220 to the bottom end of the sidewall of the second dielectric layer 223. The reflective layer 230 may also extend onto a portion of the upper surface of the third dielectric layer 225 and onto a portion of the upper surface of the first dielectric layer 221. The third dielectric layer 225 has a line 229 therein. The line 229 is comprised of a seed layer 262 and a conductive layer 264 on the seed layer 262. In this embodiment, the reflective layer 230 is formed from a seed layer 262 and a conductive layer 264 that are used to form the lines 229.
In the embodiment shown in fig. 5b, the reflective layer 230 may be formed only on the second dielectric layer 223, without forming an additional reflective layer on the sidewalls of the third dielectric layer 225. In the embodiment shown in fig. 5c, the reflective layer 230 is formed using the sidewalls of the third dielectric layer 225. The reflective layer 230 is disposed on the sidewalls of the third dielectric layer 225 of the wiring layer 220, but not on the sidewalls of the second dielectric layer 223. In this embodiment, the second dielectric layer 223 extends beyond the sidewalls of the PIC 240 through under the light guiding member 241. Other aspects of the embodiments shown in fig. 3a to 5c may be similar to those of fig. 2a and 2b, and similar detailed descriptions are omitted.
Embodiments of the present invention also provide methods of forming semiconductor package structures. Fig. 6 a-6 p are schematic diagrams of various stages of a method of forming a semiconductor package according to an embodiment of the invention.
As shown in fig. 6a, a substrate 210 with pads 604 is provided. Openings 611 exposing pads 604 are formed on substrate 210, for example, by a laser drilling process, as shown in fig. 6 b. The opening 611 may reach the surface of the pad 604. A seed layer 612 is formed over the substrate 210 and within the opening 611. In some embodiments, the seed layer 612 may be deposited using a process such as Physical Vapor Deposition (PVD).
As shown in fig. 6c, a mask layer 613 is formed over the seed layer 612, for example, using a lamination process. And patterning the mask layer 613. In some embodiments, mask layer 613 may be a photomask and may be patterned using a lithography process.
As shown in fig. 6d, a plurality of openings 621 exposing the seed layer 612 are formed in the patterned mask layer 613. A portion of the plurality of openings 621 may be formed over the opening 611 of the substrate 210. Another portion of the openings 621 may not be formed above the opening 611. A conductive layer 614 is formed on the seed layer 612 within the opening 611 and on the bottom of the opening 621 of the mask layer 613. The conductive layer 614 may be formed by a plating process or the like.
As shown in fig. 6e, the patterned masking layer 613 and the seed layer 612 masked by the patterned masking layer 613 may be removed using, for example, an etching process. The remaining seed layer 612 and conductive layer 614 thereon form a line 608. The traces 608 include traces on the substrate 210 and vias interconnecting the traces and pads 604.
Steps similar to those of fig. 6 a-6 e may then be repeated to form multiple dielectric layers and lines in the dielectric layers. As shown in fig. 6f, a first dielectric layer 221 and a line 226 formed by a seed layer 622 and a conductive layer 624, a second dielectric layer 223 on the first dielectric layer 221, and a line 228 formed by a seed layer 232 and a conductive layer 234 are formed on the substrate 210. In some embodiments, the material of the conductive layers 614, 624, 234 described above may be metallic (e.g., cu, ag, au, al, ni, ti, pd, pt, solder) and/or non-metallic (e.g., graphene).
A cavity 271 exposing a portion of the first dielectric layer 221 is also formed in the second dielectric layer 223. In addition, the cavity 271 is formed with a support 655 at an edge of the upper surface of the first dielectric layer 231. A reflective layer 230 is formed on the side wall 222 of the second dielectric layer 223 defining the cavity 271 using the seed layer 232 and the conductive layer 234 forming the wiring 228. The reflective layer 230 may be formed simultaneously with the wiring 228. The reflective layer 230 may include a seed layer 232 and a conductive layer 234 overlying the seed layer 232, the seed layer 232 and the conductive layer 234 of the reflective layer 230 extending from a portion of the upper surface of the second dielectric layer 223 through the sidewalls 222 of the second dielectric layer 223 onto a portion of the upper surface of the first dielectric layer 221. It should be understood that the illustrated embodiment is merely an example, and that in other embodiments, the reflective layer 230 may be formed from any suitable metallic material. And the reflective layer 230 may be formed by any suitable process such as sputtering, evaporation, electroplating, electroless plating, and the like.
As shown in fig. 6g, a third dielectric layer 225 is formed on the second dielectric layer 223 and on the support 655 to dispose the third dielectric layer 225 over the cavity 271.
As shown in fig. 6h, third dielectric layer 225 is patterned. A plurality of openings 635 are formed in the patterned third dielectric layer 225. The opening 635 exposes the wiring 228 under the third dielectric layer 225. In addition, patterning the third dielectric layer 225 forms a dielectric layer 265 over a portion of the cavity 271. The reflective layer 230 is exposed between the third dielectric layer 225 and the dielectric layer 265, and a portion of the upper surface of the first dielectric layer 231 is also exposed on a side of the dielectric layer 265 opposite the reflective layer 230.
A seed layer 642 is then formed. A seed layer 642 is formed over third dielectric layer 225, within opening 635, and on sidewalls of third dielectric layer 225. The seed layer 642 is also formed on the reflective layer 230, on the sidewalls and upper surface of the dielectric layer 265, and on a portion of the upper surface of the first dielectric layer 265 exposed by the dielectric layer 265.
As shown in fig. 6i, a mask layer 623 is covered over the substrate 210. A mask layer 623 overlies the exposed upper surfaces of third dielectric layer 225, dielectric layer 265, and first dielectric layer 221. The mask layer 623 may not fill in the space between the reflective layer 230 and the dielectric layer 265, and the mask layer 623 does not entirely cover the reflective layer 230. But extends laterally from above the upper surface of the reflective layer 230, across the space between the reflective layer 230 and the dielectric layer 265, and to above the sidewalls of the dielectric layer 265.
The mask layer 623 is then patterned as shown in fig. 6 j. A plurality of openings 651 are formed in the patterned mask layer 623. Some of the openings 651 may be located above openings 635 in third dielectric layer 225. The plurality of openings 651 further includes an opening 651 on a sidewall of the third dielectric layer 225, an opening 651 on a sidewall of the dielectric layer 265, and an opening 651 on a portion of the upper surface of the dielectric layer 265. A conductive layer 264 is formed on the seed layer 262 in the opening 651 of the mask layer 623. In some embodiments, the material of the conductive layer 264 may be metal (e.g., cu, ag, au, al, ni, ti, pd, pt, solder) and/or non-metal (e.g., graphene). In some embodiments, the material of the seed layers 612, 622, 232, 262 may be, for example, ti, W, ni, etc.
As shown in fig. 6k, the mask layer 623 and the seed layer 262 covered by the mask layer 623 are removed. The seed layer 262 remaining on the third dielectric layer 225 and the conductive material 264 thereon form the lines 229. The remaining seed layer 262 and conductive layer 264 also form an additional reflective layer 230' on the sidewalls of the third dielectric layer 225. The remaining seed layer 262 and conductive layer 264 are also formed on the sidewalls of the dielectric layer 265 to form the protrusions 260 in combination with the dielectric layer 265. In some embodiments, the seed layer 262 and the conductive layer 264 may not be formed on sidewalls of the dielectric layer 265, and in such embodiments, the protrusions 260 are formed only of the dielectric layer 265. In addition, the remaining seed layer 262 and conductive layer 264 are also formed on a portion of the upper surface of the dielectric layer 265 to form a connection 267 for connecting the protrusion 260 in a subsequent process.
As shown in fig. 6l, EIC 280 and PIC 240 are bonded to wiring layer 220. The PIC 240 is also engaged with the tab 260. EIC 280 and PIC 240 may be connected to wiring layer 220 by bump connectors 247, respectively. The PIC 240 is connected to a connection 267 on the tab 260 by a bump connector 247. The lower surface of the PIC 240 is provided with a light guide member 241. The light guide member 241 is formed over the reflective layer 230.
As shown in fig. 6m, an underfill 270 is formed. Underfill 270 is formed between EIC 280 and wiring layer 220, and underfill 270 is also formed between PIC 240 and wiring layer 220. Underfill 270 is also formed between PIC 240 and tab 260. The underfill 270 surrounds the plurality of bump connectors 247.
The resulting structure of fig. 6m is then inverted and solder balls 285 are formed on pads 604 of substrate 210, as shown in fig. 6 n. In some embodiments, solder balls 285 may be made of solder.
As shown in fig. 6o, the structure of fig. 6n is inverted, and a dicing process is performed through the first dielectric layer 221 of the circuit layer 220 and the substrate 210 to remove the supporting portion 655. The FAU250 is then attached to the surface of the first dielectric layer 221 by an adhesive layer 252, as shown in fig. 6 p. The FAU250 is disposed opposite the reflective layer 230, and the protrusion 260 is located above the space between the FAU250 and the reflective layer 230. This forms the final package structure.
In the above method for forming a package structure of the present invention, first, a circuit layer 220 having a cavity 273 is formed on a substrate 210, wherein a reflective layer 230 is disposed at a sidewall of the cavity 273; simultaneously with the formation of the wiring layer 220, a protrusion 260 is formed over the cavity 273, wherein the reflective layer 230 is exposed by the protrusion 260; bonding EIC 280 to wiring layer 220, followed by bonding PIC 240 with light guiding member 241 on wiring layer 220, light guiding member 241 being disposed over reflective layer 230; dicing the substrate 210 and the wiring layer 220 through the cavity 237; the FAU250 is then placed opposite the reflective layer 230 to form the final package structure.
Light from the FAU250 is reflected to the light guide member 241 via the reflection layer 230 and received by the light guide member 241. Since the protrusion 260 is provided between the FAU250 and the reflective layer 230, the presence of the protrusion 260 restricts the light transmission path between the wiring layer 220 and the protrusion 260. The reduction of the light transmission path space reduces the content of particles in the space, reduces the negative impact of particles in the environment on the coupling efficiency, and forms a relatively sealed space between the FAU250 and the PIC 240, increasing the difficulty of particles in the environment attaching to the light-reflective guide 241 through the coupling path, and further reducing the reduction in coupling efficiency caused by particles. In addition, the reflective layer 230 may be formed together in the course of forming the wiring layer 220, and production costs may be saved compared to conventional techniques of separately forming reflective elements (e.g., mirrors).
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that the invention may readily be utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims (10)

1. A package structure, comprising:
a substrate;
the circuit layer is positioned on the substrate, and a reflecting layer is arranged at a part of the side wall of the circuit layer;
an optical fiber array disposed opposite the reflective layer;
an optical integrated circuit located above the wiring layer, a portion of a lower surface of the optical integrated circuit located above the reflective layer to form an optical transmission path between the array of optical fibers and the portion of the lower surface of the optical integrated circuit via the reflective layer.
2. The package structure of claim 1, wherein,
a protrusion is also provided at the portion of the lower surface of the optical integrated circuit, the protrusion being located over the space between the reflective layer and the array of optical fibers.
3. The package structure of claim 2, wherein,
the spacing between the lower surface of the protrusion and the substrate is smaller than the spacing between the lower surface of the optical integrated circuit and the substrate.
4. The package structure of claim 1, wherein,
an underfill is also included and is also disposed between the optical integrated circuit and the wiring layer.
5. The package structure of claim 1, wherein,
the reflecting layer of the circuit layer is made of a metal material.
6. The package structure of claim 1, wherein,
the side wall of the circuit layer covered by the reflecting layer forms an acute angle with the substrate below the circuit layer.
7. The package structure of claim 1, wherein,
the circuit layer comprises a first dielectric layer positioned on the substrate and a second dielectric layer positioned on the first dielectric layer, and the reflecting layer is arranged on the side wall of the second dielectric layer.
8. The package structure of claim 7, wherein,
the optical fiber array is positioned on the first dielectric layer.
9. The package structure of claim 4, wherein,
a light guide member is disposed at the portion of the lower surface of the light integrated circuit, the surface of the light guide member exposed by the underfill being located above the reflective layer.
10. The package structure of claim 1, wherein,
the partial side wall of the wiring layer is inclined, and the reflection layer is disposed along the inclined partial side wall.
CN202111288436.1A 2021-11-02 2021-11-02 Semiconductor packaging structure and forming method thereof Pending CN116093070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111288436.1A CN116093070A (en) 2021-11-02 2021-11-02 Semiconductor packaging structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111288436.1A CN116093070A (en) 2021-11-02 2021-11-02 Semiconductor packaging structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN116093070A true CN116093070A (en) 2023-05-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111288436.1A Pending CN116093070A (en) 2021-11-02 2021-11-02 Semiconductor packaging structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN116093070A (en)

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