CN116089328A - Distributed DDR memory access architecture, method, device and medium - Google Patents

Abstract

The application discloses a distributed DDR memory access architecture, a method, a device and a medium, which relate to the technical field of data storage and are used for realizing DDR memory access of a SoC chip, aiming at the problems of the currently used star access architecture, the distributed DDR memory access architecture is provided, and a dedicated DDR controller and a DRAM are arranged for each service module to provide dedicated data storage and reading service, so that the distributed splitting of DDR memory access is realized, the bandwidth of one DDR controller is not required to be preempted among the service modules, and the access time delay is shorter; the physical distance between each service module and the exclusive DDR controller can be set closer, so that delay caused by the length of the data line is reduced; the access characteristics of the service module can be subjected to targeted access optimization, so that the access speed of the service module is improved, and the requirements of the SoC chip in a high-performance application scene are well met.

Description

Distributed DDR memory access architecture, method, device and medium

Technical Field

The present disclosure relates to the field of data storage technologies, and in particular, to a distributed DDR memory access architecture, method, apparatus, and medium.

Background

The Double Data Rate (DDR) memory is widely applied to System on Chip (SoC), and currently, the most commonly used SoC Chip adopts a star access architecture, as shown in fig. 1, that is, a DDR controller is used as a core and is connected to each service module, and the DDR controller is further matched with a dynamic random access memory (Dynamic Random Access Memory, DRAM) for storing service Data of each service module.

In the star access architecture shown in fig. 1, since each service module competes for the bandwidth of one DDR controller, the following problems occur:

1. the bandwidth of the DDR controller is easy to become a bottleneck of the whole system;

2. competing accesses of the service modules also increase access delay;

3. the DDR controller is difficult to optimize the access characteristics of each service module;

4. in the implementation of the SoC chip, the DDR controller is connected with all the service modules as a core, and the connection between the DDR controller and each service module may be long, and this long connection may also affect the final implementation speed of the SoC chip.

Therefore, the access performance of the DDR becomes one of the important factors restricting the functions of the SoC chip. With the continuous development of the electronic information industry, such access connection manner has not been able to meet the actual needs in a high-performance scenario.

Disclosure of Invention

The present application is directed to a distributed DDR memory access architecture, method, apparatus, and medium, so as to solve the above technical problems caused by the currently used DDR memory access architecture.

In order to solve the above technical problems, the present application provides a distributed DDR memory access architecture, including: a plurality of service modules, a plurality of DDR controllers, a plurality of DRAMs, and a data bus; the DDR controllers and the DRAMs are the same in number;

each service module is correspondingly connected with one DDR controller;

each DDR controller is connected with the DRAM corresponding to the DDR controller one by one;

and each service module is respectively connected with the data bus.

Preferably, the number of DDR controllers and service modules is the same, each service module corresponding to a unique DDR controller.

Preferably, each DDR controller is connected to a data bus.

Preferably, the data bus is an AMBA bus.

In order to solve the above technical problems, the present application further provides a distributed DDR memory access method, which is applied to the above distributed DDR memory access architecture, and includes:

each DDR controller stores the data sent by the service module into the DRAM correspondingly connected with the DDR controller according to the request of the service module connected with the DDR controller, or reads the data from the DRAM and sends the data to the service module;

and the service modules exchange data through a data bus.

Preferably, the method further comprises:

when the access data amount of the service module is smaller than a preset threshold value, the DDR controller corresponding to the service module is switched to a low power consumption mode;

when the access data amount of the service module is zero, the DDR controller corresponding to the service module is closed.

Preferably, when the access data amount of the service module is smaller than a preset threshold, switching the DDR controller corresponding to the service module to the low power consumption mode includes:

when the access data amount of the service module is smaller than a preset threshold value and lasts for a first preset duration, the DDR controller corresponding to the service module is switched to a low power consumption mode;

when the access data amount of the service module is zero, closing the DDR controller corresponding to the service module comprises the following steps:

and when the access data volume of the service module is zero and the second preset time duration is continued, closing the DDR controller corresponding to the service module.

In order to solve the above technical problem, the present application further provides a distributed DDR memory access device, including:

the data access module is used for storing the data sent by the service module into the DRAM correspondingly connected with the DDR controllers according to the request of the service module connected with the DDR controllers or reading the data from the DRAM and sending the data to the service module;

and the data exchange module is used for carrying out data exchange among the service modules through a data bus.

Preferably, the above-mentioned distributed DDR memory access device further comprises:

and the first switching module is used for switching the DDR controller corresponding to the service module to a low power consumption mode when the access data quantity of the service module is smaller than a preset threshold value.

And the second switching module is used for closing the DDR controller corresponding to the service module when the access data volume of the service module is zero.

In order to solve the above technical problem, the present application further provides a distributed DDR memory access device, including:

a memory for storing a computer program;

a processor for implementing the steps of the distributed DDR memory access method described above when executing a computer program.

In order to solve the above technical problem, the present application further provides a computer readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements the steps of the distributed DDR memory access method described above.

According to the distributed DDR memory access architecture, the dedicated DDR controller and the DRAM are arranged for each service module, so that dedicated data storage and reading service are provided, the distributed splitting of DDR memory access is realized, the bandwidth of one DDR controller is not required to be preempted among the service modules, and the access time delay is shorter; in addition, due to the arrangement of the exclusive DDR controller, the physical distance between each service module and the exclusive DDR controller can be more closely arranged, and the delay caused by the length of the data line is reduced; in addition, due to the arrangement of the exclusive DDR controller, one DDR controller is not required to be in charge of all service modules, only one or a small number of corresponding service modules are required to be in charge of the DDR controller, and targeted access optimization can be performed aiming at the access characteristics of the service modules so as to improve the access speed of the service modules; finally, the data interaction between the service modules is realized through the data bus, and because DDR memory access is mainly responsible for data storage and reading of the corresponding service modules, compared with the data volume of the corresponding service modules, the data volume between the service modules is smaller, and the data exchange requirement can be met by generally using one data bus, so that the control of the bus scale is facilitated, and the cost is reduced.

The distributed DDR memory access method, the distributed DDR memory access device and the computer readable storage medium correspond to the above structure and have the same effects.

Drawings

For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a conventional star DDR memory access architecture;

FIG. 2 is a block diagram of a distributed DDR memory access architecture provided by the present invention;

FIG. 3 is a block diagram of another distributed DDR memory access architecture provided by the present invention;

FIG. 4 is a flow chart of a distributed DDR memory access method provided by the invention;

FIG. 5 is a block diagram of a distributed DDR memory access device according to the present invention;

FIG. 6 is a block diagram of another distributed DDR memory access device according to the present invention.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments herein without making any inventive effort are intended to fall within the scope of the present application.

The core of the application is to provide a distributed DDR memory access architecture, a method, a device and a medium.

In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description.

The star-shaped access structure generally used at present is shown in fig. 1, and uses a DDR controller 12 as a core, which is used for storing or reading data of a plurality of service modules 11, the data sent by the service modules 11 are stored in a DRAM13, and accordingly, corresponding data in the DRAM13 also need to be returned to the service modules 11 according to an access request of the service modules 11, so as to realize storage and reading of the data.

Therefore, as can be seen from the star access architecture shown in fig. 1, the data interaction between each service module 11 and the DDR controller 12 needs to preempt the bandwidth of one DDR controller 12, so that the bandwidth of the DDR controller 12 is easy to become the bottleneck of the whole SoC system, and the performance of the system is restricted; in addition, competing accesses between the service modules 11 also increase access latency; in addition, since the access characteristics such as the addresses of all the service modules 11 are different, and all the service modules 11 share the bandwidth of one DDR controller 12, the DDR controller 12 is difficult to adapt to so many different characteristics to make access optimization, and is also unfavorable for improving the access rate; in SoC chip implementation, the DDR controller 12 is a bridge between the service module 11 and the DRAM13, so that no matter how the DDR controller 12 is configured, a part of the service module 11 is physically far from the DDR controller 12, and a connection line between the DDR controller 12 and the part of the service module 11 is relatively long, which results in an influence on the data transmission speed and affects the final implementation speed of the chip.

Therefore, in order to solve the adverse effect of the currently used star access structure on the chip implementation speed, the present application provides an improved distributed DDR memory access architecture, and the specific structure is shown in fig. 2, and includes: a plurality of service modules 11, a plurality of DDR controllers 12, a plurality of DRAMs 13, and a data bus 14;

wherein the DDR controller 12 and the DRAM13 are the same in number;

each service module 11 is correspondingly connected with one DDR controller 12;

each DDR controller 12 is connected to the DRAM13 corresponding to the DDR controller one by one;

each service module 11 is connected to the data bus.

It should be noted that, the service module 11 is a hardware module with a certain function in the SoC system, and can complete a specific task, for example, for a service module for implementing temperature measurement, it is a temperature acquisition module including a temperature sensor and an acquisition circuit. In the above storage structure, a DDR controller 12 is allocated to each service module 11, where the DDR controller 12 is a dedicated DDR controller of the service module 11, and is matched with a corresponding DRAM13 to implement storage or reading of service data of the service module. However, a DDR controller 12 does not necessarily correspond to only one service module 11, that is, a DDR controller 12 may be a dedicated DDR controller for a plurality of service modules 11 at the same time, and be connected to all of the service modules 11.

In addition, the service modules 11 need to store or read data, and besides data interaction with the DDR controller 12 and the DRAM13, there is also a certain data interaction between each service module 11, but this data is much smaller than the amount of interaction data with the DDR controller 12, so in this application, the data interaction requirement between the service modules 11 can be achieved through one data bus 14.

For the data bus 14, a common SPI bus (a full duplex synchronous serial bus), an I2C bus (a bidirectional two-wire synchronous serial bus), a UART bus (a universal serial data bus), etc. may be used, but considering that in the SoC system, a chip under an ARM structure (a 32-bit reduced instruction set processor architecture) is generally used, an advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA) bus is preferably used to adapt to the characteristics of the SoC system, which is a bus architecture specifically used in a system-in-chip design under the ARM architecture, and has a better data transmission effect.

In one possible embodiment, each DDR controller 12 is only used to implement data storage or reading of one traffic module 11, i.e., the number of DDR controllers 12 and traffic modules 11 is the same, each traffic module 11 corresponding to a unique DDR controller 12. The limiting effect of DDR control bandwidth on chip performance is reduced to the greatest extent.

However, in another embodiment, as shown in fig. 3, the service modules 11 are combined according to a certain rule, that is, a plurality of service modules 11 share a set of DDR controllers 12 and DRAMs 13 to realize data storage and reading, so as to reduce cost.

For the above-described merge rule, several types of merge rules may be included, but are not limited to:

1. according to the service type of the service module 11;

the service module 11 is a functional module for completing a specific task in the SoC system, so that it can be classified into different service types according to the task completed by the functional module. The service data of the service modules 11 of the same service type may overlap and cross, or the relationship between the service data is tighter, and the data of one service module 11 may be required by another service module 11, so that the merging according to the service type of each service module 11 can effectively solve the problem of data interaction between the service modules 11, thereby reducing the load caused to the data bus 14 and reducing the possibility that the data bus 14 becomes a chip performance bottleneck.

2. According to the size of the amount of data exchanged between the service modules 11;

it is easy to understand that, since the dedicated DDR controller 12 is used in the present application to provide data storage and reading services for the service modules 11, the DDR controller 12 can no longer implement data interaction between the service modules 11, and thus, the above functions are implemented through the data bus 14. Although the amount of data exchanged between the traffic modules 11 is relatively small throughout the distributed DDR memory access architecture, the data transfer capability of the data bus 14 also presents a challenge. Therefore, in order to reduce the burden, the service modules 11 with frequent interaction and large interaction data volume can be combined according to the data volume exchanged between the service modules 11, the same DDR controller 12 provides the data storage and reading functions, the data interaction between the two service modules 11 can be realized through the DDR controller 12, the requirement on the data bus 14 is reduced, and the chip realization speed is also improved.

3. Depending on how tight the access is;

similar to the above service types, the service modules 11 have a strong correlation or compactness for access data, the data to be stored or read by the service modules 11 are similar, and the data interaction between the service modules 11 is possible to be frequent, so that the service modules 11 can be used as one of the bases for merging the service modules 11 to achieve the same effect as described above.

In addition, as shown in fig. 2, each service module 11 has a secondary channel connected to the data bus 14 for data exchange, in addition to a primary channel connected to its dedicated DDR controller 12. For the same purpose, a secondary channel connected to the data bus 14 may be provided at each DDR controller 12, which is also used for data exchange, so that the entire distributed DDR memory access architecture is more complete, and smooth data exchange is ensured by redundancy.

According to the distributed DDR memory access architecture provided by the application, the dedicated DDR controller 12 and the DRAM13 matched with each service module 11 are arranged to provide data storage and reading services, so that compared with the star access structure commonly used at present, the architecture after the DDR controller performs distributed splitting processing can effectively solve the problem that the bandwidth of the DDR controller becomes a chip performance bottleneck. In addition, the split design of the DDR controller ensures that one DDR controller 12 only needs to be responsible for one or a small number of service modules 11, and the DDR controller 12 can be access optimized according to the access characteristics of the service modules 11, so that the access speed is improved. Similarly, the split design of the DDR controller also enables the corresponding service module 11 and the DDR controller 12 to be disposed closer to each other in physical space, so as to reduce the physical length of the data line between the two, and also improve the data access speed to a certain extent. According to the distributed DDR memory access architecture provided by the application, the DDR controller 12 is subjected to distributed splitting treatment, so that the bandwidth bottleneck problem of the star access architecture can be effectively solved, the realization speed of the SoC chip is improved, and the actual requirements are better met.

In the foregoing embodiments, a detailed description is given of a distributed DDR memory access architecture, and the present application further provides an embodiment corresponding to a distributed DDR memory access method, which is applied to the access architecture described in the foregoing embodiments, as shown in fig. 4, including:

s11: and each DDR controller stores the data sent by the service module into the DRAM correspondingly connected with the DDR controller according to the request of the service module connected with the DDR controller, or reads the data from the DRAM and sends the data to the service module.

S12: and the service modules exchange data through a data bus.

That is, for the storage and reading of service data of the service module, the data is transmitted through the main channel between the service module and the corresponding DDR controller only through the corresponding dedicated DDR controller; the secondary channels of the service modules and the data buses are used for carrying out data exchange among the service modules so as to finish data transmission in the whole distributed DDR memory access architecture, and the bandwidth of the DDR controller is prevented from becoming a bottleneck of data transmission.

Similarly, in the embodiment of the architecture portion, there is an implementation manner that sub-channels are also provided between each DDR controller and the data bus to implement data exchange between service modules, so in the distributed DDR memory access architecture corresponding to this embodiment, data exchange between service modules is implemented by the service modules, the sub-channels corresponding to the DDR controllers, and the data bus, and exchange data is transmitted in the channels.

Further, since the above-mentioned distributed DDR memory access architecture includes a plurality of DDR controllers, there is a certain increase in power consumption of the entire SoC system, and in order to reduce the power consumption of the SoC system, this embodiment further provides a preferred implementation manner based on the above-mentioned embodiment, and the above-mentioned method further includes:

s21: when the access data volume of the service module is smaller than a preset threshold value, the DDR controller corresponding to the service module is switched to a low power consumption mode.

S22: when the access data amount of the service module is zero, the DDR controller corresponding to the service module is closed.

That is, the present embodiment provides an energy-saving control method for a DDR controller, which is capable of performing energy-saving control by the method of the above embodiment when a service module corresponding to the DDR controller has no data access request or a smaller amount of access data due to a part of reasons or a specific operating condition because the DDR controller has a certain specificity.

Specifically, the DDR controller, as a control device for controlling data storage and reading of the service module, can learn the size of the data volume sent or required by the service module, and can also adjust its own working mode according to the size of the access data volume:

when the access data amount of the service module is smaller than a preset threshold, the load of the current DDR controller can be considered to be lower, so that the DDR controller can work in a low power consumption state, the access requirement of the service module can be met, and the power consumption of the SoC system can be reduced. In this application scenario, the setting of the preset threshold should be determined according to the actual situation, in the design of the SoC system, it is considered how large the data size can be considered that the access data size of the service module is smaller, or the DDR controller can process the access request of how large the data size without affecting the access speed in the low power consumption working mode, and specific values of the preset threshold are set for the above conditions.

When the access data amount of the service modules is zero, namely the service modules do not need the DDR controller to store or read data with the DRAM, the data exchange between the service modules can be realized through the auxiliary channel and the data bus, the DDR controller does not need to be carried out, the DDR controller can be closed under the condition of no load, and the power consumption is reduced to the greatest extent.

In addition, considering that the access data amount of the service module may show a fluctuation situation in the actual application process, a short time lower than a preset threshold value or even zero may occur in the fluctuation, and considering that a certain time is required for switching the working mode of the DDR controller, a time is required from off to on, and at this time, the normal data access of the service module is easily affected by the power consumption reduction control method in the above embodiment. On the basis of the above example, this example also provides a preferred embodiment, and the above step S21 and step S22 are specifically:

s21-a: when the access data amount of the service module is smaller than a preset threshold value and lasts for a first preset duration, the DDR controller corresponding to the service module is switched to a low power consumption mode.

S22-a: and when the access data volume of the service module is zero and the second preset time duration is continued, closing the DDR controller corresponding to the service module.

That is, the above-mentioned judgment condition for judging that the DDR controller can perform the operation mode switching requires that it last for a period of time to reduce the possibility of erroneous judgment caused by fluctuation, thereby reducing the influence on the normal data access of the business system.

It should be noted that, for the "first" and "second" of the first preset duration and the second preset duration, only the means for distinguishing the two preset durations is applicable, in fact, the specific value of the first preset duration may be the same as or different from the second preset duration, and it should be determined according to the actual needs, and the specific value of the first preset duration and the second preset duration does not have any influence or limitation on the other party.

The distributed DDR memory access method provided by the embodiment is applied to the distributed DDR memory access architecture, and the data access of the service module is disassembled through the DDR controller designed in a distributed split way, so that the limitation of the bandwidth of the DDR controller on the performance of the SoC system is avoided. In addition, the access data is transmitted by the main channel, and the data exchanged between the service modules is transmitted by the auxiliary channel, so that the data separation is realized, and the possibility that the bandwidth becomes a performance bottleneck is reduced. In addition, the embodiment also aims at the problem of reducing the power consumption of the SoC system, and provides a preferred implementation scheme, the DDR controller is used for judging the amount of the access data of the corresponding service module, adjusting the corresponding working state, switching to the low-power mode operation when the access data of the service module is less, and temporarily closing the DDR controller when the access data of the service module is zero, so that the power consumption of the whole SoC system is reduced to the greatest extent. In addition, in order to avoid misjudgment of the DDR controller on the working condition of the service module due to fluctuation, the embodiment introduces the improvement of judging conditions of the first preset duration and the second preset duration, better fits the working characteristics of the actual service module, and reduces the influence of the DDR controller on the normal data access of the service module due to the switching working mode.

In the foregoing embodiments, a detailed description is given of a method for accessing a distributed DDR memory, and the present application further provides a corresponding embodiment of a distributed DDR memory access device. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.

Based on the angle of the functional modules, as shown in fig. 5, the present embodiment provides a distributed DDR memory access device, including:

the data access module 21 is configured to store data sent by the service module into a DRAM corresponding to the DDR controller according to a request of the service module connected to the DDR controller, or read data from the DRAM and send the data to the service module;

the data exchange module 22 is configured to exchange data between each service module through a data bus.

Preferably, the above-mentioned distributed DDR memory access device further comprises:

and the first switching module is used for switching the DDR controller corresponding to the service module to a low power consumption mode when the access data quantity of the service module is smaller than a preset threshold value.

And the second switching module is used for closing the DDR controller corresponding to the service module when the access data volume of the service module is zero.

Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.

Fig. 6 is a block diagram of a distributed DDR memory access device according to another embodiment of the present application, and as shown in fig. 6, the distributed DDR memory access device includes: a memory 30 for storing a computer program;

the processor 31 is configured to execute the steps of a distributed DDR memory access method according to the above embodiment when executing the computer program.

The distributed DDR memory access device provided in this embodiment may be the above-mentioned distributed DDR memory access architecture, and may be specifically performed by a DDR controller and a service module.

Processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 31 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 31 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 31 may be integrated with an image processor (Graphics Processing Unit, GPU) for taking care of rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 31 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.

Memory 30 may include one or more computer-readable storage media, which may be non-transitory. Memory 30 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used for storing a computer program 301, where the computer program is loaded and executed by the processor 31 to implement the steps of a distributed DDR memory access method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 30 may further include an operating system 302, data 303, and the like, where the storage manner may be transient storage or permanent storage. The operating system 302 may include Windows, unix, linux, among other things. The data 303 may include, but is not limited to, a distributed DDR memory access method and the like.

In some embodiments, a distributed DDR memory access device may further comprise a display 32, an input/output interface 33, a communication interface 34, a power supply 35, and a communication bus 36.

Those skilled in the art will appreciate that the architecture shown in fig. 6 is not limiting of a distributed DDR memory access device and may include more or fewer components than shown.

The embodiment of the application provides a distributed DDR memory access device, which comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the processor can realize the following method: a distributed DDR memory access method.

Finally, the present application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.

It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. With such understanding, the technical solution of the present application, or a part contributing to the prior art or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The above describes in detail a distributed DDR memory access architecture, method, apparatus and medium provided in the present application. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims (10)

1. A distributed DDR memory access architecture, comprising: a plurality of service modules, a plurality of DDR controllers, a plurality of DRAMs, and a data bus; wherein the DDR controller and the DRAM are the same in number;

each service module is correspondingly connected with one DDR controller;

each DDR controller is connected with the DRAM corresponding to the DDR controller one by one;

and each service module is respectively connected with the data bus.

2. The distributed DDR memory access architecture of claim 1, wherein the number of DDR controllers and the traffic modules are the same, each traffic module corresponding to a unique one of the DDR controllers.

3. The distributed DDR memory access architecture of claim 1, wherein each of said DDR controllers is coupled to said data bus.

4. A distributed DDR memory access architecture according to any of claims 1 to 3, wherein said data bus is an AMBA bus.

5. A method for accessing a distributed DDR memory according to any one of claims 1 to 4, comprising:

each DDR controller stores data sent by a service module into a DRAM correspondingly connected with the DDR controller according to a request of the service module connected with the DDR controller, or reads data from the DRAM and sends the data to the service module;

and data exchange is carried out among the service modules through a data bus.

6. The method of distributed DDR memory access of claim 5, further comprising:

when the access data amount of the service module is smaller than a preset threshold value, the DDR controller corresponding to the service module is switched to a low power consumption mode;

and when the access data volume of the service module is zero, closing the DDR controller corresponding to the service module.

7. The method of claim 6, wherein when the access data amount of the service module is smaller than a preset threshold, switching the DDR controller corresponding to the service module to a low power consumption mode includes:

when the access data amount of the service module is smaller than a preset threshold value and lasts for a first preset duration, the DDR controller corresponding to the service module is switched to a low power consumption mode;

and when the access data amount of the service module is zero, closing the DDR controller corresponding to the service module comprises the following steps:

and when the access data amount of the service module is zero and the second preset time duration is continuous, closing the DDR controller corresponding to the service module.

8. A distributed DDR memory access device, comprising:

the data access module is used for storing the data sent by the service module into the DRAM correspondingly connected with the DDR controller according to the request of the service module connected with the DDR controller or reading the data from the DRAM and sending the data to the service module;

and the data exchange module is used for carrying out data exchange between the service modules through a data bus.

9. A distributed DDR memory access device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the distributed DDR memory access method of any of claims 5 to 7 when executing the computer program.

10. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, which when executed by a processor, implements the steps of the distributed DDR memory access method of any of claims 5 to 7.

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