CN116088631B

CN116088631B - Power supply circuit and memory

Info

Publication number: CN116088631B
Application number: CN202310381597.8A
Authority: CN
Inventors: 倪潼; 颜崇根; 季汝敏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-11
Filing date: 2023-04-11
Publication date: 2023-06-30
Anticipated expiration: 2043-04-11
Also published as: CN116088631A

Abstract

The present disclosure relates to the field of integrated circuits, and discloses a power supply circuit and a memory. Wherein the power supply circuit includes: a temperature sensing circuit and a generating circuit. A temperature sensing circuit configured to generate a simulated first temperature controlled voltage as a function of temperature; the first temperature control voltage changes linearly with temperature; a generation circuit connected with the temperature sensing circuit and configured to receive the first temperature control voltage, convert the first temperature control voltage into a first digital signal and generate a digitized second temperature control voltage according to the first digital signal; the second temperature control voltage comprises a plurality of voltage values, and each voltage value is constant in a corresponding temperature interval. The embodiment of the disclosure can timely adjust the voltage/current conditions in the integrated circuit according to the temperature change to offset the negative influence caused by the temperature change, thereby improving the performance of the integrated circuit.

Description

Power supply circuit and memory

Technical Field

The present disclosure relates to the field of integrated circuits, and more particularly, to a power supply circuit and a memory.

Background

During operation of an integrated circuit, its temperature may rise due to thermal effects of the current. The greater the intensity of operation, the more the temperature rises. On the other hand, temperature changes in the external environment can also affect the temperature of the integrated circuit. Thus, the operation of integrated circuits needs to be adapted to different temperature conditions.

Disclosure of Invention

In view of the above, the embodiments of the present disclosure provide a power supply circuit and a memory, which can timely adjust the voltage/current conditions in the integrated circuit according to the temperature change to offset the negative effects caused by the temperature change, thereby improving the performance of the integrated circuit.

The technical scheme of the embodiment of the disclosure is realized as follows:

the disclosed embodiments provide a power supply circuit including: a temperature sensing circuit configured to generate a simulated first temperature controlled voltage as a function of temperature; the first temperature control voltage linearly changes along with the temperature; a generation circuit connected to the temperature sensing circuit and configured to receive the first temperature control voltage, convert the first temperature control voltage into a first digital signal, and generate a digitized second temperature control voltage according to the first digital signal; the second temperature control voltage comprises a plurality of voltage values, and each voltage value is constant in a corresponding temperature interval.

In the above aspect, the generating circuit includes: a first conversion circuit configured to receive the first temperature control voltage and a reference voltage and output the first digital signal; the first digital signal comprises 2 ⁿ Bit first data, n is a positive integer; the first clamping circuit is connected with the first conversion circuit and is configured to receive the first digital signal, process the first digital signal according to a first preset temperature range and output a second digital signal; the second digital signal comprises 2 ⁿ Bit second data, n is a positive integer; and the second conversion circuit is connected with the first clamping circuit and is configured to receive and output the corresponding second temperature control voltage according to the second digital signal.

In the above aspect, the first conversion circuit includes: a first reference voltage generation unit and a comparison unit; the first reference voltage generating unit is configured to receive the reference voltage and generate 2 which are reduced in sequence ⁿ A first reference voltage; the comparison unit is connected with the first reference voltage generation unit and is configured to receive the first temperature control voltage and 2 ⁿ Comparing each first reference voltage with the first temperature control voltage to obtain 2 ⁿ A first comparison result; each of the first comparison results corresponds to one bit of first data in the first digital signal.

In the above aspect, the first reference voltage generating unit includes: 2 ⁿ +1 first voltage dividing resistors connected in series in sequence; the first end of the first voltage dividing resistor is connected with a reference voltage end, and the second end of the last voltage dividing resistor is connected with a grounding end; the second end of each first voltage dividing resistor outputs the corresponding first reference voltage.

In the above aspect, the comparing unit includes: 2 ⁿ A first comparator; the first input end of each first comparator correspondingly receives oneThe first reference voltage; the second input end of each first comparator receives the first temperature control voltage; the output end of each first comparator correspondingly outputs one first comparison result.

In the above aspect, the first clamping circuit includes: a first encoder, a first clamping unit, and a first decoder; the first encoder is connected with the first conversion circuit and is configured to receive the first digital signal and encode the first digital signal into n-bit encoded information; the coding information corresponds to the temperature one by one; the first clamping unit is configured to receive the coding information, the first reference code and the second reference code, compare the coding information, the first reference code and the second reference code and output the second coding information; the temperature corresponding to the second coding information is located in the first preset temperature range; the first decoder is connected with the first clamping unit and is configured to decode and output the second digital signal according to the second coding information.

In the above aspect, the first clamping unit includes: the first comparison unit, the second comparison unit, the first gating device and the second gating device; the first preset temperature range comprises an upper limit temperature and a lower limit temperature; the first comparison unit is configured to receive and compare the coding information and the first reference code and output a first gating control signal; wherein the first reference code corresponds to the upper temperature limit; if the first reference code is larger than the coding information, the first gating control signal is of a first level; if the first reference code is smaller than the coding information, the first gating control signal is of a second level; the first gating device is configured to receive the coding information, the first reference code and the first gating control signal, and output the first reference code when the first gating control signal is at a second level; or outputting the encoded information when the first gate control signal is at a first level; the second comparing unit is configured to receive and compare the coding information and the second reference code and output a second gating control signal; wherein the second reference code corresponds to the lower limit temperature; if the second reference code is larger than the coding information, the second gating control signal is of a second level; if the second reference code is smaller than the coding information, the second gating control signal is of a first level; the second gate configured to receive the second reference code and the second gate control signal, and to receive the encoded information or the first reference code from the first gate, and to output the second reference code in the case where the second gate control signal is at a second level; or, in case the second gating control signal is at a first level, outputting the encoded information or the first reference code received from the first gate.

In the above aspect, the second conversion circuit includes: a first linear voltage regulating unit and a second temperature-controlled voltage generating unit; the first linear voltage regulating unit is configured to receive a reference voltage, compare and regulate according to the reference voltage and output a first reference voltage; the second temperature-controlled voltage generating unit is connected with the first linear voltage regulator and is configured to output the corresponding second temperature-controlled voltage according to the second digital signal and the first reference voltage.

In the scheme, the second conversion circuit further comprises a first control unit and a second control unit; the first control unit is connected with the first linear voltage regulating unit and is configured to receive an m-bit control code and regulate a first reference voltage according to the control code; the second control unit is connected with the second temperature control voltage generating unit and is configured to receive the control code and adjust the second temperature control voltage according to the control code.

In the above aspect, the first linear voltage adjusting unit includes: the first amplifier, the first current source and the protection resistor; the first current source includes: the first MOS tube and the second MOS tube are connected in series; the positive input end of the first amplifier receives the reference voltage; the output end of the first amplifier is connected with the grid electrode of the second MOS tube; the negative input end of the first amplifier is connected with the source electrode of the second MOS tube; the drain electrode of the first MOS tube is connected with the grid electrode; the first end of the protection resistor is connected with the source electrode of the second MOS tube, and the second end of the protection resistor is grounded.

In the above aspect, the second temperature-controlled voltage generating unit includes: 2 ⁿ Second voltage dividing resistor sum 2 ⁿ A plurality of pass transistors; 2 ⁿ The second voltage dividing resistors are sequentially connected in series; a first end of a first second voltage dividing resistor is connected to the first reference voltage, and a second end of a last second voltage dividing resistor is coupled with a ground end; the grid electrode of each transmission transistor correspondingly receives one bit of data in the second digital signal; the drain electrode of each transmission transistor is correspondingly connected with the first end of one second voltage dividing resistor; and the source electrode of each transmission transistor is connected in parallel, and the second temperature control voltage is output.

In the above aspect, the first control unit includes: second decoder and 2 ^m A second current source; the second decoder is configured to receive the control code and decode 2 ^m A bit first control code; each of the second current sources includes: the third MOS tube and the fourth MOS tube are connected in series; the source electrode of each third MOS tube is connected to the source electrode of the first MOS tube, and the grid electrode of each third MOS tube is connected to the grid electrode of the first MOS tube; the grid electrode of each fourth MOS tube correspondingly receives one bit of the first control code, and the source electrode of each fourth MOS tube is connected with the first end of the first second voltage dividing resistor.

In the above aspect, the second control unit includes: a third decoder, a plurality of third voltage dividing resistors and 2 ^m A plurality of control transistors; the third decoder is configured to receive the control code and decode 2 ^m A second control code of bits; the first end of the first third voltage dividing resistor is connected with the second end of the last second voltage dividing resistor, and the second end of the last third voltage dividing resistor is grounded; each control transistor is connected in parallel with at least one corresponding third voltage dividing resistor; the grid electrode of each control transistor correspondingly receives one bit of the second control code; each of said controlsAnd a transistor configured to be controlled by the second control code, and short-circuit the third voltage dividing resistor connected in parallel to the second control code so as to regulate the second temperature control voltage.

In the above scheme, the power supply circuit further includes: an output control circuit; the output control circuit is connected with the generating circuit and is configured to receive the second temperature control voltage, the first limiting voltage and the second limiting voltage, clamp the second temperature control voltage and generate a third temperature control voltage; the maximum value of the third temperature control voltage corresponds to the first limiting voltage, and the minimum value of the third temperature control voltage corresponds to the second limiting voltage.

In the above aspect, the output control circuit includes: a second clamping unit, a second linear voltage adjusting unit, and a control signal generating unit; the second clamping unit is configured to receive the second temperature control voltage, the first limiting voltage, the second limiting voltage and a feedback control signal, correspondingly output an initial output voltage according to the feedback control signal, and the initial output voltage is the first limiting voltage when the feedback control signal indicates that the second temperature control voltage is larger than the first limiting voltage; or, in the case where the feedback control signal characterizes the second temperature control voltage as being less than the second limit voltage, the initial output voltage is the second limit voltage; otherwise, the initial output voltage is the second temperature control voltage; the second linear voltage regulating unit is connected with the output end of the second clamping unit and is configured to receive the initial output voltage, compare and output a target output voltage; the control signal generation unit is connected with the output end of the second linear voltage regulation unit and is configured to compare the target output voltage with the first limit voltage and the second limit voltage respectively according to the target output voltage, the first limit voltage and the second limit voltage and generate the feedback control signal according to a comparison result.

In the above solution, the feedback control signal includes: a first feedback signal, a second feedback signal, and a third feedback signal; the second clamping unit includes: a first transmission gate, a second transmission gate, and a third transmission gate; the input end of the first transmission gate receives the first limiting voltage, the control end of the first transmission gate receives the first feedback signal, and the output end of the first transmission gate is connected to the output end of the second clamping unit; the input end of the second transmission gate receives the second temperature control voltage, the control end of the second transmission gate receives the second feedback signal, and the output end of the second transmission gate is connected to the output end of the second clamping unit; the input end of the third transmission gate receives the second limiting voltage, the control end of the third transmission gate receives the third feedback signal, and the output end of the third transmission gate is connected to the output end of the second clamping unit.

In the above aspect, the control signal generating unit includes: the second comparator, the third comparator, the first AND gate, the second AND gate and the third AND gate; the positive input end of the second comparator receives the first limiting voltage, the negative input end of the second comparator receives the target output voltage, and the second comparator outputs a second comparison result; the positive input end of the third comparator receives the target output voltage, the negative input end of the third comparator receives the second limiting voltage, and the third comparator outputs a third comparison result; the first AND gate receives the second comparison result and the third comparison result respectively, and outputs the first feedback signal; the second AND gate receives the second comparison result and the inverse value of the third comparison result respectively, and outputs the second feedback signal; and the third AND gate receives the inverted value of the second comparison result and the third comparison result respectively, and outputs the third feedback signal.

The embodiment of the disclosure also provides a memory, which comprises the power supply circuit in the scheme.

It can be seen that the embodiments of the present disclosure provide a power supply circuit and a memory. Wherein the power supply circuit includes: a temperature sensing circuit and a generating circuit. A temperature sensing circuit configured to generate a simulated first temperature controlled voltage as a function of temperature; the first temperature control voltage changes linearly with temperature; a generation circuit connected with the temperature sensing circuit and configured to receive the first temperature control voltage, convert the first temperature control voltage into a first digital signal and generate a digitized second temperature control voltage according to the first digital signal; the second temperature control voltage comprises a plurality of voltage values, and each voltage value is constant in a corresponding temperature interval. In this way, the second temperature control voltage related to temperature is generated, so that the voltage/current condition in the integrated circuit can be timely adjusted according to the temperature change to counteract the negative influence caused by the temperature change, and the performance of the integrated circuit is improved. Meanwhile, the value range of the second temperature control voltage only comprises a plurality of discrete voltage values, each voltage value corresponds to one temperature interval, and each voltage value is constant in the corresponding one temperature interval. Compared with the voltage continuously changing along with the temperature, the second temperature control voltage has lower sensitivity to the temperature, is not easy to change the voltage due to tiny temperature change, and further reduces misjudgment in the circuit.

Drawings

Fig. 1 is a schematic diagram of a power circuit according to an embodiment of the disclosure;

FIG. 2A is a schematic diagram of a first temperature control voltage according to an embodiment of the disclosure;

FIG. 2B is a second schematic diagram of a first temperature control voltage according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram I of a second temperature control voltage provided by an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a structure of a generating circuit in a power supply circuit according to an embodiment of the disclosure;

fig. 5 is a schematic diagram ii of a generating circuit in a power supply circuit according to an embodiment of the disclosure;

fig. 6 is a schematic structural diagram of a first conversion circuit in a power supply circuit according to an embodiment of the disclosure;

fig. 7 is a schematic diagram of a decoding circuit in a power circuit according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of a structure of a second conversion circuit in the power supply circuit according to the embodiment of the disclosure;

fig. 9 is a schematic diagram ii of a second conversion circuit in the power supply circuit according to the embodiment of the disclosure;

fig. 10 is a schematic diagram III of a second conversion circuit in the power supply circuit according to the embodiment of the disclosure;

fig. 11 is a schematic diagram of a second conversion circuit in a power supply circuit according to an embodiment of the disclosure;

FIG. 12 is a second schematic diagram of a second temperature control voltage provided by an embodiment of the disclosure;

fig. 13 is a schematic diagram of a structure of a temperature sensing circuit in a power supply circuit according to an embodiment of the disclosure;

fig. 14 is a schematic diagram ii of a temperature sensing circuit in a power supply circuit according to an embodiment of the disclosure;

fig. 15 is a second schematic structural diagram of a power supply circuit according to an embodiment of the disclosure;

fig. 16 is a schematic diagram of a structure of an output control circuit in a power supply circuit according to an embodiment of the disclosure;

fig. 17 is a schematic diagram ii of an output control circuit in the power supply circuit according to the embodiment of the disclosure;

fig. 18 is a schematic diagram III of a power supply circuit according to an embodiment of the disclosure;

FIG. 19 is a schematic diagram of a memory according to an embodiment of the disclosure;

fig. 20 is a schematic diagram of a second structure of the memory according to the embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first/second" appears in the present document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first/second/third" may interchange a specific order or precedence, as allowed, to enable embodiments of the disclosure described herein to be implemented in an order other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

Temperature variations in an integrated circuit may have an effect on electrical components in the integrated circuit, for example, on the charge/discharge rate of a capacitor, and, for example, on parasitic parameters of a transistor. Therefore, according to the temperature change, the voltage/current condition in the integrated circuit is adjusted timely, so that the negative influence caused by the temperature change can be counteracted, and the performance of the integrated circuit is improved.

Fig. 1 is a schematic diagram of an alternative configuration of a power circuit provided in an embodiment of the disclosure, and as shown in fig. 1, a power circuit 80 includes: a temperature sensing circuit 10 and a generating circuit 20.

The temperature sensing circuit 10 is configured to generate a simulated first temperature control voltage Vtemp1 from temperature. The first temperature control voltage Vtemp1 varies linearly with temperature.

The generating circuit 20 is connected to the temperature sensing circuit 10, and is configured to receive the first temperature control voltage Vtemp1, convert the first temperature control voltage Vtemp1 into a first digital signal, and generate a digitized second temperature control voltage Vtemp2 according to the first digital signal. The second temperature control voltage Vtemp2 includes a plurality of voltage values, and each voltage value is constant in a corresponding temperature interval.

In the embodiment of the disclosure, fig. 2A and 2B illustrate a curve of the first temperature control voltage Vtemp1 with temperature, as illustrated in fig. 2A and 2B, the first temperature control voltage Vtemp1 changes linearly with temperature continuously, that is, the first temperature control voltage Vtemp1 is modeled. The first temperature control voltage Vtemp1 may decrease with increasing temperature (refer to fig. 2A), and the first temperature control voltage Vtemp1 may also increase with increasing temperature (refer to fig. 2B), which may be achieved by providing different temperature sensing circuits 10. Referring to fig. 2A and 2B, each temperature corresponds to a first temperature control voltage Vtemp1, for example, the temperature values T1 to T8 correspond to the voltage values V1 to V8, respectively, that is, in the case that the current temperature is any one of the temperature values T1 to T8, the first temperature control voltage Vtemp1 is a corresponding one of the voltage values V1 to V8.

In the embodiment of the disclosure, fig. 3 illustrates a curve of the second temperature control voltage Vtemp2 with respect to the temperature, as illustrated in fig. 3, the second temperature control voltage Vtemp2 changes discretely with respect to the current temperature, that is, the second temperature control voltage Vtemp2 is digitized. Referring to fig. 3, the second temperature control voltage Vtemp2 includes a plurality of voltage values, each voltage value corresponding to one temperature interval in the current temperature, for example, the second temperature control voltage Vtemp2 includes voltage values V3, V4 and V5, wherein the voltage value V3 corresponds to the temperature interval T3 to T4, the voltage value V4 corresponds to the temperature interval T4 to T5, and the voltage value V5 corresponds to the temperature interval T5 to T6. That is, when the current temperature is any one of the temperature values T3 to T4, the second temperature control voltage Vtemp2 is the voltage value V3, and so on.

With continued reference to fig. 3, the second temperature-controlled voltage Vtemp2 may be clamped between the lower voltage limit Vclamp-and the upper voltage limit vclamp+. That is, in the case where the current temperature is lower than the temperature lower limit T3, the second temperature control voltage Vtemp2 is maintained as the voltage lower limit Vclamp-; in the case where the current temperature is higher than the upper temperature limit T6, the second temperature control voltage Vtemp2 is maintained as the upper voltage limit vclamp+. Here, the voltage lower limit Vclamp-and the voltage upper limit vclamp+ of the clamp, and the temperature lower limit and the temperature upper limit may be adjusted by adjusting the elements in the generating circuit 20.

It can be appreciated that the embodiment of the disclosure converts the first temperature control voltage into the first digital signal by performing the digitizing process on the analog first temperature control voltage, and further generates the digitized second temperature control voltage according to the first digital signal. In this way, the second temperature control voltage related to the current temperature is generated, so that the voltage/current condition in the integrated circuit can be timely adjusted according to the temperature change to offset the negative influence caused by the temperature change, and the performance of the integrated circuit is improved.

Meanwhile, the value range of the second temperature control voltage only comprises a plurality of discrete voltage values, each voltage value corresponds to one temperature interval in the current temperature, and each voltage value is constant in the corresponding one temperature interval. Compared with the voltage continuously changing along with the temperature, the second temperature control voltage has lower sensitivity to the temperature, is not easy to change the voltage due to tiny temperature change, and further reduces misjudgment in a circuit. Wherein erroneous decisions in the circuit, such as gate voltage changes, result in a false turn-on of the transistor, and input voltage changes, for example, result in a false output of the comparator.

In some embodiments of the present disclosure, as shown in fig. 4, the generation circuit 20 includes: a first conversion circuit 201, a first clamp circuit 202, and a second conversion circuit 203.

A first conversion circuit 201 configured to receive a first temperature control voltage Vtemp1 and a reference voltage Vref and output a first digital signal DS1; wherein the first digital signal DS1 comprises 2 ⁿ And (3) bit the first data, wherein n is a positive integer.

A first clamping circuit 202 connected to the first converting circuit 201 and configured to receive the first digital signal DS1, process the first digital signal DS1 according to a first preset temperature range, and output a second digital signal code2; the second digital signal code2 comprises 2 ⁿ And the second data is bit.

The second conversion circuit 203 is connected to the first clamping circuit 202, and is configured to receive and output a corresponding second temperature control voltage Vtemp2 according to the second digital signal code 2.

It is understood that the first clamping circuit may clamp the output second temperature-controlled voltage according to the first preset temperature range. In this way, the second temperature-controlled voltage can be clamped between the upper and lower limits, and the reliability of devices in the circuit is prevented from being damaged due to the fact that the voltage value is too high or too low, so that the performance of the integrated circuit is improved.

In some embodiments of the present disclosure, as shown in fig. 5, the first conversion circuit 201 includes: a first reference voltage generation unit 204 and a comparison unit 205.

A first reference voltage generating unit 204 configured to receive the reference voltage Vref and generate sequentially decreasing 2 ⁿ A first reference voltage.

A comparison unit 205 connected to the first reference voltage generation unit 204 and configured to receive the first temperature control voltages Vtemp1 and 2 ⁿ A first reference voltage, each of which is compared with a first temperature control voltage Vtemp1 to obtain 2 ⁿ And (5) first comparison results.

In fig. 5, taking n=3 as an example, the first reference voltage generating unit 204 generates 8 first reference voltages V1 to V8; correspondingly, the comparing unit 205 compares each of the 8 first reference voltages V1 to V8 with the first temperature control voltage Vtemp1 to obtain 8 first comparison results Com1 to Com8.

In the embodiment of the disclosure, referring to fig. 4 and 5, each first comparison result corresponds to one bit of first data in the first digital signal DS 1. For example, among 8 first comparison results Com 1-Com 8, the 1 st first comparison result Com1 is "1", and the rest of the first comparison results are "0", and then the first digital signal DS1 is "10000000"; for another example, among the 8 first comparison results Com1 to Com8, the 1 st first comparison result Com1 and the 2 nd first comparison result Com2 are "1", and the remaining first comparison results are "0", and then the first digital signal DS1 is "11000000".

It should be noted that fig. 5 is only illustrated by n=3, and is not a limitation of the embodiments of the present disclosure. In some embodiments of the present disclosure, n may also be other values, which will not be described in detail below. For example, in the case where n=4, the first reference voltage generating unit 204 generates 16 first reference voltages, and the comparing unit 205 may obtain 16 first comparison results, that is, the first digital signal DS1 includes 16 bits of data.

In some embodiments of the present disclosure, as shown in fig. 6, the first reference voltage generating unit 204 includes: 2 ⁿ +1 first voltage dividing resistors (including resistors R11 to R19) connected in series in order. The first end of the first voltage dividing resistor R11 is connected with the reference voltage end Vref, and the second end of the last first voltage dividing resistor R19 is connected with the grounding end. The second end of each first voltage dividing resistor outputs a corresponding first reference voltage (including voltages V1 to V8).

In fig. 6, taking n=3 as an example, the first reference voltage generating unit 204 includes 9 first voltage dividing resistors R11 to R19 connected in series in sequence. The 9 first voltage dividing resistors R11 to R19 divide the reference voltage Vref, that is, the sum of the voltages applied to the 9 first voltage dividing resistors R11 to R19 is the reference voltage Vref. The reference voltage Vref may be a constant voltage regardless of the temperature, that is, the current temperature is not changed.

Further, each first reference voltage is correspondingly generated at a connection point between every two adjacent first voltage dividing resistors, that is, the first reference voltages V1 to V8 are obtained by dividing the reference voltage Vref. Taking the example that the resistance values of the 9 first voltage dividing resistors R11 to R19 are equal, the value of V1 is

V2 has a value of +.>

By analogy, the value of V8 is

That is, the values of V1 to V8 decrease in sequence.

It should be noted that, the resistances of the first voltage dividing resistors R11 to R19 may be set to be unequal, so that the values of the first reference voltages V1 to V8 may also be changed accordingly, that is, the values of the first reference voltages may be adjusted by setting the resistances of the respective first voltage dividing resistors. On the other hand, the value of the first reference voltage may also be adjusted by changing the reference voltage Vref.

In some embodiments of the present disclosure, as shown in fig. 6, the comparison unit 205 includes: 2 ⁿ A first comparator 2051. The first input of each first comparator 2051 receives a first reference voltage. 2 ⁿ The second input terminals of the first comparators 2051 each receive the first temperature control voltage Vtemp1. The output terminal of each first comparator 2051 outputs a first comparison result.

In fig. 6, n=3 is taken as an example, and the comparing unit 205 includes 8 first comparators 2051. The first input terminal of the first comparator 2051 receives the first reference voltages V1 to V8, and compares the first reference voltages V1 to V8 with the first temperature control voltage Vtemp1, thereby outputting the first comparison results Com1 to Com8.

In the embodiment of the disclosure, with continued reference to fig. 6, when the value of the first temperature control voltage Vtemp1 is changed, 8 first comparison results Com1 to Com8 are changed. Further, since the first digital signal DS1 is composed of all the first comparison results, each of the first comparison results corresponds to one bit of data in the first digital signal DS1, and therefore, different values of the first temperature control voltage Vtemp1 correspondingly generate different first digital signals DS1.

In the embodiment of the disclosure, since the values of the first reference voltages V1 to V8 decrease sequentially, if the first temperature control voltage Vtemp1 is greater than V1, the first temperature control voltage Vtemp1 is greater than any one of the first reference voltages V1 to V8, and then, the 8 first comparators 2051 output low levels (i.e. "0"), and the first digital signal DS1 is "00000000". If the first temperature control voltage Vtemp1 is between V2 and V1, the first temperature control voltage Vtemp1 is smaller than the first reference voltage V1, and the first temperature control voltage Vtemp1 is larger than any one of the first reference voltages V2 to V8, and then the 1 st first comparator 2051 outputs a high level (i.e. "1"), the 2 nd to 8 th first comparators 2051 output a low level (i.e. "0"), and the first digital signal DS1 is "10000000". And so on.

It will be appreciated that the first conversion circuit is implemented by generating sequentially decreasing 2 ⁿ And comparing each first reference voltage with the first temperature control voltage to obtain a first digital signal. Because the first temperature control voltage linearly changes along with the current temperature, the generated first digital signal also corresponds to the current temperature, and then the voltage/current condition in the integrated circuit can be timely adjusted according to the temperature change to offset the negative influence caused by the temperature change, thereby improving the performance of the integrated circuit.

In some embodiments of the present disclosure, in conjunction with fig. 4 and 7, the first clamp circuit 202 includes: a first encoder 206, a first clamping unit 207 and a first decoder 208.

A first encoder 206, coupled to the first conversion circuit 201, configured to receive the first digital signal DS1 (comprising Com 1-Com 8), and encode the first digital signal DS1 into n-bit encoded information A3A2A1 (i.e. comprising 3-bit data A3, A2 and A1); the coded information corresponds to the temperature one by one.

A first clamping unit 207 configured to receive the encoded information A3A2A1 and to receive the first reference code A9A8A7 (i.e., including 3-bit data A9, A8, and A7) and the second reference code A6A5A4 (i.e., including 3-bit data A6, A5, and A4), compare the encoded information A3A2A1, the first reference code A9A8A7, and the second reference code A6A5A4, and output the second encoded information (including 3-bit data Out1, out2, and Out 3); the temperature corresponding to the second coding information is located in a first preset temperature range.

The first decoder 208 is connected to the first clamping unit 207 and configured to decode and output a second digital signal (including 8-bit data B1 to B8) according to the second encoded information.

It should be noted that, in fig. 7, n=3 is taken as an example for illustration, the encoded information, the first reference code, the second reference code and the second encoded information all include n bits of data, and the first digital signal and the second digital signal all include 2 ⁿ Bit data. This is not a limitation of the embodiments of the present disclosure, and will not be described in detail.

In the embodiment of the disclosure, with continued reference to fig. 4 and 7, after receiving the first digital signal DS1 (i.e., 8 first comparison results Com 1-Com 8), the first encoder 206 encodes the first digital signal DS1 and outputs the encoded information code1 (including 3-bit data A1, A2 and A3), wherein the encoded information code1 includes n-bit data, i.e., the encoded information code1 includes 3-bit data A1, A2 and A3 in fig. 5. For example, if the first digital signal DS1 is "10000000", the encoded information code1 is "001"; if the first digital signal DS1 is "11000000", the encoded information code1 is "010".

Table 1 below shows an alternative correspondence relationship of the first temperature control voltage Vtemp1, the first digital signal DS, and the encoded information code 1. Referring to table 1, since the values of the first reference voltages V1 to V8 decrease in sequence, if the first temperature control voltage Vtemp1 is greater than V1, the first temperature control voltage Vtemp1 is greater than any one of the first reference voltages V1 to V8, and further, the 8 first comparators 2051 output a low level (i.e. "0"), the first digital signal DS1 is "00000000", and the encoded information code1 is "000". If the first temperature control voltage Vtemp1 is between V2 and V1, the first temperature control voltage Vtemp1 is smaller than the first reference voltage V1, and the first temperature control voltage Vtemp1 is larger than any one of the first reference voltages V2 to V8, and then the 1 st first comparator 2051 outputs a high level (i.e. "1"), the 2 nd to 8 th first comparators 2051 output a low level (i.e. "0"), the first digital signal DS1 is "10000000", and the encoded information code1 is "001". And so on.

TABLE 1

；

Table 2 below shows that the second encoded information (including 3-bit data Out1, out2, and Out 3) is decoded into corresponding second digital signals (including 8-bit data B1-B8). Referring to table 2, different second digital signals may correspond to different temperature values T1 to T8, and the second digital signals may be used to control the magnitude of the second temperature control voltage Vtemp2, so that a corresponding relationship between the temperature value and the second temperature control voltage Vtemp2 may be established.

TABLE 2

；

In some embodiments of the present disclosure, referring to fig. 7, the first clamping unit 207 includes: a first comparison unit 2071, a second comparison unit 2072, a first gating device 2073 and a second gating device 2074. The first preset temperature range includes an upper limit temperature and a lower limit temperature.

A first comparing unit 2071 configured to receive and compare the encoded information A3A2A1 and the first reference code A9A8A7 and output a first gating control signal E1; wherein the first reference code A9A8A7 corresponds to an upper limit temperature; if the first reference code A9A8A7 is greater than the encoded information A3A2A1, the first strobe control signal E1 is at a first level (e.g., high level, i.e., "1"); if the first reference code A9A8A7 is smaller than the encoded information A3A2A1, the first strobe control signal E1 is at a second level (e.g., low level, i.e., "0").

A first gating 2073 configured to receive the encoded information A3A2A1, the first reference code A9A8A7 and the first gating control signal E1, and to output the first reference code A9A8A7 if the first gating control signal E1 is at the second level; alternatively, when the first strobe control signal E1 is at the first level, the encoded information A3A2A1 is output.

A second comparing unit 2072 configured to receive and compare the encoded information A3A2A1 and the second reference code A6A5A4 and output a second gating control signal E2; wherein the second reference code A6A5A4 corresponds to the lower limit temperature; if the second reference code A6A5A4 is greater than the encoded information A3A2A1, the second strobe control signal E2 is at a second level (e.g., low level, i.e., "0"); if the second reference code A6A5A4 is smaller than the encoded information A3A2A1, the second strobe control signal E2 is at a first level (e.g., a high level, i.e., "1").

A second gate 2074 configured to receive the second reference code A6A5A4 and the second gate control signal E2 and to receive the encoded information A3A2A1 or the first reference code A9A8A7 from the first gate 2073 and to output the second reference code A6A5A4 in case the second gate control signal E2 is at the second level; alternatively, in the case where the second gating control signal E2 is at the first level, the encoded information A3A2A1 or the first reference code A9A8A7 received from the first gating 2073 is output.

In the embodiment of the disclosure, referring to fig. 7, the encoded information includes 3-bit data A3, A2, and A1, the first reference code includes 3-bit data A9, A8, and A7, and the second reference code includes 3-bit data A6, A5, and A4. A first comparing unit 2071, for receiving the first reference code A9A8A7 from the first input terminal H and the encoded information A3A2A1 from the second input terminal L, and comparing the binary value corresponding to the encoded information A3A2A1 with the binary value corresponding to the first reference code A9A8 A7; for example, if the encoded information A3A2A1 is "010" and the first reference code A9A8A7 is "110", the encoded information A3A2A1 is smaller than the first reference code A9A8A7. Further, in the case where the encoded information A3A2A1 is smaller than the first reference code A9A8A7, the first comparing unit 2071 outputs the first gating control signal E1 of the first level (its value is "1", high level) to the first gating device 2073, and further, the first gating device 2073 selects the encoded information A3A2A1 to output to the second gating device 2074; accordingly, in the case where the encoded information A3A2A1 is greater than the first reference code A9A8A7, the first comparing unit 2071 outputs the first gating control signal E1 of the second level (its value is "0", low level) to the first gating device 2073, and further, the first gating device 2073 selects the first reference code A9A8A7 to output to the second gating device 2074.

With continued reference to fig. 7, the second comparing unit 2072 receives the encoded information A3A2A1 from the first input terminal H and the second reference code A6A5A4 from the second input terminal L, and may compare the binary value corresponding to the encoded information A3A2A1 with the binary value corresponding to the second reference code A6A5 A4; for example, if the encoded information A3A2A1 is "010" and the second reference code A6A5A4 is "001", the encoded information A3A2A1 is larger than the second reference code A6A5A4. Further, in the case where the encoded information A3A2A1 is smaller than the second reference code A6A5A4, the second comparing unit 2072 outputs the second gating control signal E2 (whose value is "0", low level) of the second level to the second gating device 2074, and further, the second gating device 2074 selects the second reference code A6A5A4 to output to the first decoder 208; accordingly, in the case where the encoded information A3A2A1 is greater than the second reference code A6A5A4, the second comparing unit 2072 outputs the second gating control signal E1 of the first level (its value is "1", high level) to the second gating device 2074, and further, the second gating device 2074 selectively outputs the encoded information A3A2A1 or the first reference code A9A8A7 received from the first gating device 2073 to the first decoder 208.

That is, the first reference code A9A8A7 corresponds to an upper limit temperature, and the second reference code A6A5A4 corresponds to a lower limit temperature, thereby clamping the temperature corresponding to the encoded information A3A2 A1. When the temperature corresponding to the encoding information A3A2A1 is less than the lower limit temperature; that is, in the case where the binary value of the encoded information A3A2A1 is smaller than the binary value of the second reference code A6A5A4, the first clamping unit 207 outputs the second reference code A6A5A4 as the data Out1, out2 and Out3 to the first decoder 208. In the case where the temperature corresponding to the encoded information A3A2A1 is greater than the upper limit temperature, that is, in the case where the binary value of the encoded information A3A2A1 is greater than the binary value of the first reference code A9A8A7, the first clamping unit 207 outputs the first reference code A9A8A7 as data Out1, out2 and Out3 to the first decoder 208. In the case where the temperature corresponding to the encoded information A3A2A1 is between the lower limit temperature and the upper limit temperature, that is, in the case where the binary value of the encoded information A3A2A1 is smaller than the binary value of the first reference code A9A8A7 and larger than the binary value of the second reference code A6A5A4, the first clamping unit 207 outputs the encoded information A3A2A1 as data Out1, out2, and Out3 to the first decoder 208.

It will be appreciated that by comparing the encoded information and outputting it, clamping of the temperature and, in turn, the second temperature controlled voltage can be achieved. Therefore, the voltage value can be prevented from being changed along with the temperature without limitation, and the voltage value corresponding to the basic function of the circuit is ensured to be realized by the second temperature control voltage, so that the performance of the integrated circuit is improved.

In some embodiments of the present disclosure, as shown in fig. 8, the second conversion circuit 203 includes: a first linear voltage adjustment unit 209 and a second temperature-controlled voltage generation unit 210.

The first linear voltage adjusting unit 209 is configured to receive the reference voltage Vref, and to output a first reference voltage Vint according to the reference voltage Vref comparison adjustment.

The second temperature-controlled voltage generating unit 210 is connected to the first linear voltage adjusting unit 209 and configured to output a corresponding second temperature-controlled voltage Vtemp2 according to the second digital signal code2 and the first reference voltage Vint.

In some embodiments of the present disclosure, as shown in fig. 9, the second conversion circuit 203 further includes: a first control unit 211 and a second control unit 212;

a first control unit 211 connected to the first linear voltage adjustment unit 209 and configured to receive the m-bit control code3 and adjust the first reference voltage Vint according to the control code 3;

The second control unit 212 is connected to the second temperature-controlled voltage generating unit 212 and configured to receive the control code3 and adjust the second temperature-controlled voltage Vtemp2 according to the control code 3.

In some embodiments of the present disclosure, as shown in fig. 10, the first linear voltage adjusting unit 209 includes: a first amplifier Amp2, a first current source and a protection resistor R5. The first current source includes: the first MOS tube MP4 and the second MOS tube MN1 are connected in series. The positive input of the first amplifier Amp2 receives a reference voltage Vref. The output end of the first amplifier Amp2 is connected with the grid electrode of the second MOS tube MN 1; the negative input end of the first amplifier Amp2 is connected with the source electrode of the second MOS tube MN1. The drain electrode of the first MOS tube MP4 is connected with the grid electrode. The first end of the protection resistor R5 is connected with the source electrode of the second MOS tube MN1, and the second end of the protection resistor R5 is grounded.

In the embodiment of the present disclosure, referring to fig. 10, the source of the second MOS transistor MN1 generates the reference current I1. The gate of the first MOS transistor MP4 is connected to the gate of the MOS transistor MP41, and the drain of the MOS transistor MP41 generates the first reference voltage Vint. The first amplifier Amp2, the first MOS transistor MP4 and the second MOS transistor MN1 form an LDO (Linear Drop Out regulator, linear regulator), wherein the voltage at the output end of the first amplifier Amp2 controls the turn-on degree of the second MOS transistor MN1, and the source current of the second MOS transistor MN1 is fed back to the negative input end of the first amplifier Amp 2. In this way, the negative feedback can be deepened, the noise can be reduced, and the stability of the first reference voltage Vint can be improved.

In one of the present disclosureIn some embodiments, as shown in fig. 10, the second temperature-controlled voltage generating unit 210 includes: 2 ⁿ Second voltage dividing resistors (including R20 to R27) and 2 ⁿ And pass transistors (including MN6 to MN 13).

In embodiments of the present disclosure, reference is made to fig. 10,2 ⁿ The second voltage dividing resistors R20-R27 are sequentially connected in series; the first terminal of the first second voltage dividing resistor R20 is connected to the first reference voltage Vint, and the second terminal of the last second voltage dividing resistor R27 is coupled to the ground. Thus, a partial voltage of the initial output voltage Vint is obtained between every two second voltage dividing resistors, and the magnitudes of the partial voltages are sequentially reduced. The first end of each of the second voltage dividing resistors R20 to R27 outputs a corresponding second temperature control voltage Vtemp2, that is, the second temperature control voltage Vtemp2 has different magnitudes according to the difference of the collected divided voltages.

With continued reference to FIG. 10, the gate of each pass transistor MN 6-MN 13 correspondingly receives one bit of data in the second digital signal (including 8 bits of data B1-B8); the drain electrode of each transmission transistor MN 6-MN 13 is correspondingly connected with the first end of one second voltage dividing resistor R20-R27, and the source electrodes of each transmission transistor MN 6-MN 13 are connected in parallel to output a second temperature control voltage Vtemp2. Meanwhile, in combination with table 2, since the data B1 to B8 of the second digital signal are related to the current temperature, the turn-on of the pass transistors MN6 to MN13 can be controlled according to the current temperature, and thus, the magnitude of the second temperature control voltage Vtemp2 can be controlled.

It is understood that the second temperature-controlled voltage generating unit outputs the second temperature-controlled voltage according to the second digital signal corresponding to the current temperature. Thus, the voltage/current condition in the integrated circuit can be timely adjusted according to the temperature change to counteract the negative influence caused by the temperature change, and the performance of the integrated circuit is improved.

In some embodiments of the present disclosure, as shown in fig. 11, the first control unit 211 includes: second decoders Dec2 and 2 ^m And a second current source.

In the embodiment of the disclosure, referring to fig. 11, the second decoder Dec2 is configured to receive the control code and decode 2 ^m The first control code is bit. It should be noted thatIn fig. 11, taking m=2 as an example, the control code received by the second decoder Dec2 includes 2-bit data C1 and C2, and the first control code output by the second decoder Dec2 includes 4-bit data D1, D2, D3, and D4.

In the disclosed embodiment, with continued reference to fig. 11, each second current source includes: and the third MOS tube (comprising MP5 to MP 8) and the fourth MOS tube (comprising MN2 to MN 5) are connected in series. Specifically, the NMOS tube MN2 and the PMOS tube MP5 form a 1 st second current source, the NMOS tube MN3 and the PMOS tube MP6 form a 2 nd second current source, the NMOS tube MN4 and the PMOS tube MP7 form a 3 rd second current source, and the NMOS tube MN5 and the PMOS tube MP8 form a 4 th second current source, thereby forming 2 ^m And a second current source (m=2). The source electrode of each third MOS tube MP 5-MP 8 is connected to the source electrode of the first MOS tube MP4, and the grid electrode of each third MOS tube MP 5-MP 8 is connected to the grid electrode of the first MOS tube MP 4; the gates of each of the fourth MOS transistors MN 2-MN 5 correspondingly receive one bit of the first control codes D1-D4.

In embodiments of the present disclosure, reference is continued to FIGS. 11,2 ^m The second current sources can be mirrored to the first current sources to generate a current of the same magnitude as the reference current I1, that is, the currents I2, I3, I4 and I5 are equal to the reference current I1. The currents I2, I3, I4 and I5 are converged to the output terminal of the first control unit 211, thereby generating the initial output voltage Vint.

Further, the fourth MOS transistors MN 2-MN 5 are controlled by 2 ^m The first control codes D1-D4 are turned on, so that the initial output voltage Vint can be adjusted.

Table 3 illustrates the correspondence of the control code (including 2-bit data C1 and C2) and the first control code (including 4-bit data D1, D2, D3, and D4).

TABLE 3 Table 3

；

Referring to fig. 11 and table 3, when the control code is "00", the first control code is "1000", the fourth MOS transistor MN2 is turned on, and the initial output voltage Vint is generated by the current I2. When the control code is "01", the first control code is "1100", the fourth MOS transistors MN2 and MN3 are turned on, and the initial output voltage Vint is generated by the currents I2 and I3. And so on. Thus, the slope of the second temperature control voltage Vtemp2 with respect to the temperature change can be controlled by the control code.

Fig. 12 shows a graph of the second temperature control voltage Vtemp2 as a function of temperature. Referring to fig. 12, the larger the number of the turned-on second current sources, the larger the slope of the second temperature-controlled voltage Vtemp2 with temperature change, that is, the slope of the curves 1 to 4 sequentially increases.

It is understood that the first control unit controls the slope of the second temperature-controlled voltage along with the temperature change according to the control code. Meanwhile, the first control unit can generate the second temperature control voltage which rises along with the rise of the temperature and also can generate the second temperature control voltage which decreases along with the decrease of the temperature, and the second temperature control voltage can be realized according to the control code gating voltage, that is, the first control unit can control not only the rising slope but also the corresponding slope. In this way, different temperature compensation speeds can be provided, so that the requirements of different use scenes can be met, and the adaptability of the integrated circuit is improved.

In some embodiments of the present disclosure, referring to fig. 11, the second control unit 212 includes: a third decoder Dec3, a plurality of third voltage dividing resistors (including R30-R39, and R5) and 2 ^m Control transistors (including MN 14-MN 17). A third decoder Dec configured to receive a control code (including 2-bit data C1 and C2) and decode 2 ^m A second control code of bits (including 4-bit data E1-E4).

With continued reference to fig. 11, a plurality of third voltage dividing resistors R30 to R39 are connected in series, wherein a first end of the first third voltage dividing resistor R30 is connected to a second end of the last second voltage dividing resistor R27, and a second end of the last third voltage dividing resistor R36 to R39 is grounded.

With continued reference to fig. 11, each control transistor is connected in parallel with a corresponding at least one third voltage dividing resistor; the gate of each control transistor receives a bit of the second control codes E1-E4. Each control transistor is configured to be controlled by the second control code, and short-circuits a third voltage dividing resistor connected in parallel with the second control code to adjust the second temperature control voltage Vtemp2.

That is, 2 ^m The source and the drain of each control transistor MN 14-MN 17 are sequentially connected among the third voltage dividing resistors, and each control transistor is connected with the third voltage dividing resistors in parallel. The gate of each control transistor receives a bit of the second control codes E1-E4. 2 ^m The control transistors are configured to be controlled by the second control codes E1 to E4, short-circuit part of the third voltage dividing resistor, so as to adjust the resistance value of the second control unit 212, and further adjust the second temperature control voltage Vtemp2.

For example, if the data E1 is "1", the control transistor MN14 is turned on, and the third voltage dividing resistor R30 is shorted; if the data E2 is "1", the control transistor MN15 is turned on, and the third voltage dividing resistors R31 and R32 are shorted. In this way, the resistance value of the second control unit 212 connected between the first control unit 211 and the second temperature-controlled voltage generating unit 210 can be adjusted; furthermore, it is possible to ensure that the starting voltage in the voltage-temperature variation curve is the same.

In some embodiments of the present disclosure, as shown in fig. 13, the temperature sensing circuit 10 includes: the second amplifier Amp4, the fifth MOS transistor MP10, the sixth MOS transistor MP11, the seventh MOS transistor MP12, the first resistor R8, the second resistor R9, and the first BJT transistor Q3. The source of the fifth MOS transistor MP10 is connected with the source of the sixth MOS transistor MP11 and the source of the seventh MOS transistor MP 12. The output end of the second amplifier Amp4 is connected with the grid electrode of the fifth MOS tube MP10, the grid electrode of the sixth MOS tube MP11 and the grid electrode of the seventh MOS tube MP 12. The negative input end of the second amplifier Amp4 is connected with the drain electrode of the fifth MOS transistor MP10, the base electrode and the collector electrode of the first BJT transistor Q3. The positive input end of the second amplifier Amp4 is connected with the drain electrode of the sixth MOS transistor MP11 and the first end of the first resistor R8. The drain electrode of the seventh MOS transistor MP12 is connected to the first end of the second resistor R9 and is used as the output end of the temperature sensing circuit 10. An emitter of the first BJT Q3 is connected to the second end of the first resistor R8 and the second end of the second resistor R9.

In the embodiment of the disclosure, the temperature sensing circuit 10 shown in fig. 13, whose output first temperature control voltage Vtemp1 decreases with the current temperature, and the change curve may refer to fig. 2A. The first temperature control voltage Vtemp1 satisfies the following formula:

；

in the above equation, vbe represents the voltage between the base and emitter of the first BJT Q3. Vbe is temperature dependent, and therefore, the first temperature control voltage Vtemp1 is also temperature dependent.

In some embodiments of the present disclosure, as shown in fig. 14, the temperature sensing circuit 10 further includes: and a second BJT Q4. The second BJT Q4 is connected between the first resistor R8 and the first BJT Q3, and between the first resistor R8 and the second resistor R9. The base and collector of the second BJT Q4 are connected to the second end of the first resistor R8. An emitter of the second BJT Q4 is connected to an emitter of the first BJT Q3 and a second end of the second resistor R9.

In the embodiment of the disclosure, the temperature sensing circuit 10 shown in fig. 14, whose output first temperature control voltage Vtemp1 rises with the rise of the current temperature, may refer to fig. 2B. The first temperature control voltage Vtemp1 satisfies the following formula:

；

in the above-mentioned method, the step of,

representing the difference in voltage between the base and emitter of the first BJT Q3 and the base and emitter of the second BJT Q4. / >

Is temperature dependent, and therefore, the first temperature control voltage Vtemp1 is also temperature dependent.

In some embodiments of the present disclosure, as shown in fig. 15, the power circuit 80 further includes: and an output control circuit 30. An output control circuit 30 connected to the generation circuit 20 and configured to receive the second temperature control voltage Vtemp2, the first limit voltage vclamp+ and the second limit voltage Vclamp-, clamp the second temperature control voltage Vtemp2, and generate a third temperature control voltage Vtemp3; the maximum value of the third temperature control voltage Vtemp3 corresponds to the first limit voltage vclamp+, and the minimum value of the third temperature control voltage Vtemp3 corresponds to the second limit voltage Vclamp-.

In some embodiments of the present disclosure, as shown in fig. 15, the power circuit 80 further includes: a reference source 40. The reference source 40 supplies a reference voltage Vref to the first conversion circuit 201 and the second conversion circuit 203. The reference voltage Vref is a constant voltage that does not vary with the current temperature.

In some embodiments of the present disclosure, as shown in fig. 16, the output control circuit 30 includes: a second clamping unit 301, a second linear voltage adjustment unit 302, and a control signal generation unit 303.

The second clamping unit 301 is configured to receive the second temperature control voltage Vtemp2, the first limiting voltage vclamp+, the second limiting voltage Vclamp-and the feedback control signal EN, and correspondingly output an initial output voltage Vout/accordingto the feedback control signal EN, where the feedback control signal EN characterizes that the second temperature control voltage Vtemp2 is greater than the first limiting voltage vclamp+, the initial output voltage Vout/-is the first limiting voltage vclamp+; or, in case the feedback control signal EN characterizes that the second temperature control voltage Vtemp2 is smaller than the second limit voltage Vclamp-, the initial output voltage Vout/is the second limit voltage Vclamp-; otherwise, the initial output voltage Vout/is the second temperature control voltage Vtemp2.

The second linear voltage adjusting unit 302, connected to the output terminal of the second clamping unit 301, is configured to receive the initial output voltage Vout/, compare and output the target output voltage Vout.

The control signal generating unit 303 is connected to the output terminal of the second linear voltage adjusting unit 302, and is configured to compare the target output voltage Vout with the first limit voltage vclamp+ and the second limit voltage Vclamp according to the target output voltage Vout, the first limit voltage vclamp+ and the second limit voltage Vclamp-, and generate the feedback control signal EN according to the comparison result.

In some embodiments of the present disclosure, as shown in fig. 17, the feedback control signal includes: first feedback signals EN1 and EN1F, second feedback signals EN2 and EN2F, and third feedback signals EN3 and EN3F; wherein, the feedback signals EN1 and EN1F are opposite to each other, the feedback signals EN2 and EN2F are opposite to each other, and the feedback signals EN3 and EN3F are opposite to each other.

The second clamping unit 301 includes: a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3. The input terminal of the first transmission gate TG1 receives the first limiting voltage vclamp+, the control terminal of the first transmission gate TG1 receives the first feedback signals EN1 and EN1F, and the output terminal of the first transmission gate TG1 is connected to the output terminal of the second clamping unit 301. The input terminal of the second transmission gate TG2 receives the second temperature control voltage Vtemp2, the control terminal of the second transmission gate TG2 receives the second feedback signals EN2 and EN2F, and the output terminal of the second transmission gate TG2 is connected to the output terminal of the second clamping unit 301. The input terminal of the third transmission gate TG3 receives the second limiting voltage Vclamp-, the control terminal of the third transmission gate TG3 receives the third feedback signals EN3 and EN3F, and the output terminal of the third transmission gate TG3 is connected to the output terminal of the second clamping unit 301.

In some embodiments of the present disclosure, as shown in fig. 17, the control signal generation unit 303 includes: the second comparator Com9, the third comparator Com10, the first inverter Inv1, the second inverter Inv2, the first And gate And1, the second And gate And2, the third And gate And3, the third inverter Inv3, the fourth inverter Inv4, and the fifth inverter Inv5.

The positive input terminal of the second comparator Com9 receives the first limiting voltage vclamp+, the negative input terminal of the second comparator Com9 receives the target output voltage Vout, and the second comparator Com9 outputs the second comparison result clamp1. The input terminal of the first inverter Inv1 is connected to the output terminal of the second comparator Com9, and the first inverter Inv1 outputs the inverted value clamp1F of the second comparison result. The positive input terminal of the third comparator Com10 receives the target output voltage Vout, the negative input terminal of the third comparator Com10 receives the second limiting voltage Vclamp-, and the third comparator Com10 outputs a third comparison result clamp2. The input terminal of the second inverter Inv2 is connected to the output terminal of the third comparator Com10, and the second inverter Inv2 outputs the inverted value clamp2F of the third comparison result. The first And gate And1 receives the second comparison result clamp1 And the third comparison result clamp2 respectively, and the first And gate And1 outputs a first feedback signal EN1; the input terminal of the third inverter Inv3 is connected to the output terminal of the first And gate And 1. The second And gate And2 receives the second comparison result clamp1 And the inverted value clamp2F of the third comparison result respectively, and the second And gate And2 outputs a second feedback signal EN2; the input of the fourth inverter Inv4 is connected to the output of the second And gate nd 2. The third And gate And3 receives the inverted value clamp1F of the second comparison result And the third comparison result clamp2, respectively, and the third And gate And3 outputs a third feedback signal EN3; the input terminal of the fifth inverter Inv5 is connected to the output terminal of the third And gate And 3.

In the embodiment of the disclosure, referring to fig. 17, the control signal generating unit 303 compares the output voltage Vout with the first limit voltage vclamp+ and compares the target output voltage Vout with the second limit voltage Vclamp-after receiving the target output voltage Vout, where the first limit voltage vclamp+ is the upper clamping limit of the target output voltage Vout and the second limit voltage Vclamp-is the lower clamping limit of the target output voltage Vout.

If the target output voltage Vout is smaller than the first limit voltage vclamp+ and larger than the second limit voltage Vclamp-, that is, the target output voltage Vout is between the upper clamping limit and the lower clamping limit, the first feedback signal EN1 is "1", and the second feedback signal EN2 and the third feedback signal EN3 are both "0". Thus, the second transmission gate TG2 is opened, and the first transmission gate TG1 and the third transmission gate TG3 are closed; thus, the second clamping unit 301 outputs the second temperature control voltage Vtemp2.

If the target output voltage Vout is greater than the first limit voltage vclamp+, that is, the target output voltage Vout is greater than the upper clamping limit, the second feedback signal EN2 is "1", and the first feedback signal EN1 and the third feedback signal EN3 are both "0". Thus, the first transmission gate TG1 is opened, and the second transmission gate TG2 and the third transmission gate TG3 are closed; thus, the second clamping unit 301 outputs the first limiting voltage vclamp+, that is, the target output voltage Vout is clamped at the first limiting voltage vclamp+.

If the target output voltage Vout is smaller than the second limiting voltage Vclamp-, that is, the target output voltage Vout is smaller than the clamping lower limit, the third feedback signal EN3 is "1", and the first feedback signal EN1 and the second feedback signal EN2 are both "0". Thus, the third transmission gate TG3 is opened, and the first and second transmission gates TG1 and TG2 are closed; thus, the second clamp unit 301 outputs the second limiting voltage Vclamp-, that is, the target output voltage Vout is clamped at the second limiting voltage Vclamp-.

It will be appreciated that the output control circuit may clamp the target output voltage between upper/lower voltages such that the voltage level is prevented from being too high or too low to damage the reliability of devices in the circuit, thereby improving the performance of the integrated circuit.

In some embodiments of the present disclosure, as shown in fig. 17, the second linear voltage adjusting unit 302 includes: the third amplifier Amp3, the eighth MOS transistor MP13, the third resistor R41 and the fourth resistor R42. The negative input of the third amplifier Amp3 is connected to the output of the second clamp 301. The output end of the third amplifier Amp3 is connected with the grid electrode of the eighth MOS tube MP 13. The source of the eighth MOS transistor MP13 is connected to the power source terminal VIN. The drain electrode of the eighth MOS transistor MP13 is connected to the first end of the third resistor R41, and is used as the output end of the second linear voltage adjusting unit 302. The second end of the third resistor R41 is connected to the positive input end of the third amplifier Amp3 and the first end of the fourth resistor R42. The second terminal of the fourth resistor R42 is grounded.

In the embodiment of the disclosure, referring to fig. 17, the third amplifier Amp3 and the eighth MOS transistor MP13 form an LDO, wherein the voltage at the output end of the third amplifier Amp3 controls the opening degree of the eighth MOS transistor MP13, and the source-drain current of the eighth MOS transistor MP13 is fed back to the positive input end of the third amplifier Amp 3. Thus, the negative feedback can be deepened, the noise is reduced, and the stability of the target output voltage Vout output by the drain electrode of the eighth MOS transistor MP13 is improved.

The third resistor R41 and the fourth resistor R42 are used for adjusting the target output voltage Vout, and protecting the eighth MOS transistor MP13 from the excessive source-drain current of the eighth MOS transistor MP 13. In some embodiments, the third resistor R41 may be removed, i.e., the drain of the eighth MOS transistor MP13 is directly connected to the positive input of the third amplifier Amp 3.

It should be noted that fig. 18 is a schematic structural diagram of the power supply circuit 80, and the circuit structure shown in the schematic structural diagram may be understood in conjunction with fig. 1 to 17.

The disclosed embodiments also provide a memory, as shown in fig. 19, where the memory 90 includes a power supply circuit 80. The power supply circuit 80 includes the structure of any of the above embodiments.

In some embodiments of the present disclosure, referring to fig. 19, power supply circuit 80 supplies power to bit lines and/or word lines in memory 90.

Fig. 20 shows a part of a circuit structure in the memory 90. Referring to fig. 20, memory cells are connected between bit lines and word lines. The voltage on the word line controls the turn-on of the transfer transistor T, so that the capacitor C is connected to the bit line, and the capacitor C is charged/discharged to complete writing or reading of data. Specifically, the row decoder gates the corresponding row according to the command and opens the corresponding word line, and the capacitor C in the memory cell and the capacitor on the bit line share charge. The bit line is precharged to Vcc/2 prior to charge sharing; further, if a "1" is stored in the memory cell, the voltage on the bit line after charge sharing increases, and if a "0" is stored in the memory cell, the voltage on the bit line after charge sharing decreases. Sense Amplifiers (SA) compare the bit line voltage to Vcc/2, pulling the corresponding bit line voltage high or low.

Referring to fig. 19 and 20, power is supplied to the bit lines and/or word lines in the memory 90 through the power circuit 80, that is, the voltage on the word lines and/or bit lines can be adjusted according to the current temperature, so that the negative effect caused by the temperature change can be counteracted, and the performance of the memory 90 is improved.

For example, the parasitic parameter of the transfer transistor T is affected by the current temperature, and in the low temperature case, the source parasitic resistance Rd and the drain parasitic resistance Rs of the transistor are both increased, so that the charging speed of the capacitor C is reduced. In particular, as the integration level of the integrated circuit is continuously improved, the size of the transfer transistor T is continuously reduced; with the decreasing size of the pass transistor T, the effect of parasitic parameters will become larger and larger. Therefore, at low temperature, the voltage on the word line and/or bit line can be increased to increase the source drain current in the pass transistor T, thereby increasing the charge speed of the capacitor C in the memory cell.

As another example, in a low temperature case, increasing the voltage of the bit line can improve the sensing margin (sensing margin) of the sense amplifier. When the bit line voltage increases, the voltage Vsignal transferred to the sense amplifier increases, so that the voltage difference across the sense amplifier increases, the speed of the sense amplifier increases, and thus, the speed of data reading and writing can be increased.

As another example, high voltage can reduce device reliability due to high temperature conditions. Therefore, at high temperature, the voltage rise of the bit line and the word line is avoided, and the reliability of the device can be ensured, thereby ensuring the normal operation of the memory 90.

In addition, the power supply circuit 80 is provided with a clamp voltage and a clamp temperature, and after the upper clamp limit or the lower clamp limit is reached, the output voltage is not changed. In this way, unrestricted variations in the voltages on the word lines and/or bit lines are avoided, and the reliability of devices in the circuit is prevented from being damaged by too high or too low a voltage value, thereby improving the performance of the memory 90.

Meanwhile, the slope of the voltage output from the power supply circuit 80 with temperature change is controllable. In this way, different temperature compensation speeds can be provided according to the requirements of different usage scenarios, thereby improving the adaptability of the memory 90.

The power supply circuit 80 is not limited to the memory 90, and supplies power to the bit lines and/or word lines in the memory 90. Other signal-related power circuits may employ the power circuit 80, and are not limited herein.

In some embodiments of the present disclosure, referring to fig. 19, the memory 90 may be a DRAM (dynamic random access memory). The DRAM may be any one of DDR4 (4 th generation double rate synchronous dynamic random access memory), DDR5 (5 th generation double rate synchronous dynamic random access memory), LPDDR4 (4 th generation low power consumption double rate synchronous dynamic random access memory), and LPDDR5 (5 th generation low power consumption double rate synchronous dynamic random access memory).

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims

1. A power supply circuit, the power supply circuit comprising:

a temperature sensing circuit configured to generate a simulated first temperature controlled voltage as a function of temperature; the first temperature control voltage linearly changes along with the temperature;

a generation circuit connected to the temperature sensing circuit and configured to receive the first temperature control voltage, convert the first temperature control voltage into a first digital signal, and generate a digitized second temperature control voltage according to the first digital signal; the second temperature control voltage comprises a plurality of voltage values, and each voltage value is constant in a corresponding temperature interval; wherein, the liquid crystal display device comprises a liquid crystal display device,

the generation circuit includes: a first conversion circuit, a first clamp circuit, and a second conversion circuit;

the first conversion circuit is configured to receive the first temperature control voltage and a reference voltage and output the first digital signal; the first digital signal comprises 2 ⁿ Bit first data, n is a positive integer;

the first clamping circuit is connected with the first conversion circuit and is configured to receive the first digital signal, process the first digital signal according to a first preset temperature range and output a second digital signal; the second digital signal comprises 2 ⁿ Bit the second data; the first preset temperature range comprises an upper limit temperature and a lower limit temperature;

the second conversion circuit is connected with the first clamping circuit and is configured to receive and output the corresponding second temperature control voltage according to the second digital signal;

wherein the first clamp circuit includes: a first encoder, a first clamping unit, and a first decoder;

the first encoder is connected with the first conversion circuit and is configured to receive the first digital signal and encode the first digital signal into n-bit encoded information; the coding information corresponds to the temperature one by one;

the first clamping unit is configured to receive the coding information, the first reference code and the second reference code, compare the coding information corresponding to the first digital signal with the first reference code and the second reference code, output the compared coding information and output the second coding information; the temperature corresponding to the second coding information is located in the first preset temperature range; the first reference code corresponds to the upper limit temperature; the second reference code corresponds to the lower limit temperature;

The first decoder is connected with the first clamping unit and is configured to decode and output the second digital signal according to the second coding information.

2. The power supply circuit of claim 1, wherein the first conversion circuit comprises: a first reference voltage generation unit and a comparison unit;

the first reference voltage generating unit is configured to receive the reference voltage and generate 2 which are reduced in sequence ⁿ A first reference voltage;

the comparison unit is connected with the first reference voltage generation unit and is configured to receive the first temperature control voltage and 2 ⁿ Comparing each first reference voltage with the first temperature control voltage to obtain 2 ⁿ A first comparison result; each of the first comparison results corresponds to one bit of first data in the first digital signal.

3. The power supply circuit according to claim 2, wherein the first reference voltage generating unit includes: 2 ⁿ +1 first voltage dividing resistors connected in series in sequence;

the first end of the first voltage dividing resistor is connected with a reference voltage end, and the second end of the last voltage dividing resistor is connected with a grounding end;

The second end of each first voltage dividing resistor outputs the corresponding first reference voltage.

4. The power supply circuit according to claim 2, wherein the comparing unit includes: 2 ⁿ A first comparator;

the first input end of each first comparator correspondingly receives one first reference voltage; the second input end of each first comparator receives the first temperature control voltage; the output end of each first comparator correspondingly outputs one first comparison result.

5. The power supply circuit of claim 1, wherein the first clamping unit comprises: the first comparison unit, the second comparison unit, the first gating device and the second gating device;

the first comparison unit is configured to receive and compare the coding information and the first reference code and output a first gating control signal; if the first reference code is larger than the coding information, the first gating control signal is of a first level; if the first reference code is smaller than the coding information, the first gating control signal is of a second level;

the first gating device is configured to receive the coding information, the first reference code and the first gating control signal, and output the first reference code when the first gating control signal is at a second level; or outputting the encoded information when the first gate control signal is at a first level;

The second comparing unit is configured to receive and compare the coding information and the second reference code and output a second gating control signal; if the second reference code is larger than the coding information, the second gating control signal is at a second level; if the second reference code is smaller than the coding information, the second gating control signal is of a first level;

the second gate configured to receive the second reference code and the second gate control signal, and to receive the encoded information or the first reference code from the first gate, and to output the second reference code in the case where the second gate control signal is at a second level; or, in case the second gating control signal is at a first level, outputting the encoded information or the first reference code received from the first gate.

6. The power supply circuit of claim 1, wherein the second conversion circuit comprises: a first linear voltage regulating unit and a second temperature-controlled voltage generating unit;

the first linear voltage regulating unit is configured to receive a reference voltage, compare and regulate according to the reference voltage and output a first reference voltage;

The second temperature-controlled voltage generating unit is connected with the first linear voltage regulator and is configured to output the corresponding second temperature-controlled voltage according to the second digital signal and the first reference voltage.

7. The power supply circuit of claim 6, wherein the second conversion circuit further comprises a first control unit and a second control unit;

the first control unit is connected with the first linear voltage regulating unit and is configured to receive an m-bit control code and regulate a first reference voltage according to the control code;

the second control unit is connected with the second temperature control voltage generating unit and is configured to receive the control code and adjust the second temperature control voltage according to the control code.

8. The power supply circuit of claim 6, wherein the first linear voltage regulation unit comprises: the first amplifier, the first current source and the protection resistor; the first current source includes: the first MOS tube and the second MOS tube are connected in series;

the positive input end of the first amplifier receives the reference voltage; the output end of the first amplifier is connected with the grid electrode of the second MOS tube; the negative input end of the first amplifier is connected with the source electrode of the second MOS tube;

The drain electrode of the first MOS tube is connected with the grid electrode;

the first end of the protection resistor is connected with the source electrode of the second MOS tube, and the second end of the protection resistor is grounded.

9. The power supply circuit according to claim 6, wherein the second temperature-controlled voltage generating unit includes: 2 ⁿ Second voltage dividing resistor sum 2 ⁿ A plurality of pass transistors;

2 ⁿ the second voltage dividing resistors are sequentially connected in series; a first end of a first second voltage dividing resistor is connected to the first reference voltage, and a second end of a last second voltage dividing resistor is coupled with a ground end;

the grid electrode of each transmission transistor correspondingly receives one bit of data in the second digital signal; the drain electrode of each transmission transistor is correspondingly connected with the first end of one second voltage dividing resistor; and the source electrode of each transmission transistor is connected in parallel, and the second temperature control voltage is output.

10. The power supply circuit of claim 7, wherein the first control unit comprises: second decoder and 2 ^m A second current source;

the second decoder is configured to receive the control code and decode 2 ^m A bit first control code;

each of the second current sources includes: the third MOS tube and the fourth MOS tube are connected in series; the source electrode of each third MOS tube is connected to the source electrode of the first MOS tube, and the grid electrode of each third MOS tube is connected to the grid electrode of the first MOS tube; the grid electrode of each fourth MOS tube correspondingly receives one bit of the first control code, and the source electrode of each fourth MOS tube is connected with the first end of the first second voltage dividing resistor.

11. The power supply circuit according to claim 7, wherein the second control unit includes: a third decoder, a plurality of third voltage dividing resistors and 2 ^m A plurality of control transistors;

the third decoder is configured to receive the control code and decode 2 ^m A second control code of bits;

the first end of the first third voltage dividing resistor is connected with the second end of the last second voltage dividing resistor, and the second end of the last third voltage dividing resistor is grounded;

each control transistor is connected in parallel with at least one corresponding third voltage dividing resistor; the grid electrode of each control transistor correspondingly receives one bit of the second control code;

each control transistor is configured to be controlled by the second control code, and short-circuits the third voltage dividing resistor connected in parallel with the second control code to regulate the second temperature control voltage.

12. The power supply circuit of claim 1, wherein the power supply circuit further comprises: an output control circuit;

the output control circuit is connected with the generating circuit and is configured to receive the second temperature control voltage, the first limiting voltage and the second limiting voltage, clamp the second temperature control voltage and generate a third temperature control voltage; the maximum value of the third temperature control voltage corresponds to the first limiting voltage, and the minimum value of the third temperature control voltage corresponds to the second limiting voltage.

13. The power supply circuit of claim 12, wherein the output control circuit comprises: a second clamping unit, a second linear voltage adjusting unit, and a control signal generating unit;

the second clamping unit is configured to receive the second temperature control voltage, the first limiting voltage, the second limiting voltage and a feedback control signal, correspondingly output an initial output voltage according to the feedback control signal, and the initial output voltage is the first limiting voltage when the feedback control signal indicates that the second temperature control voltage is larger than the first limiting voltage; or, in the case where the feedback control signal characterizes the second temperature control voltage as being less than the second limit voltage, the initial output voltage is the second limit voltage; otherwise, the initial output voltage is the second temperature control voltage;

the second linear voltage regulating unit is connected with the output end of the second clamping unit and is configured to receive the initial output voltage, compare and output a target output voltage;

the control signal generation unit is connected with the output end of the second linear voltage regulation unit and is configured to compare the target output voltage with the first limit voltage and the second limit voltage respectively according to the target output voltage, the first limit voltage and the second limit voltage and generate the feedback control signal according to a comparison result.

14. The power supply circuit of claim 13, wherein the feedback control signal comprises: a first feedback signal, a second feedback signal, and a third feedback signal;

the second clamping unit includes: a first transmission gate, a second transmission gate, and a third transmission gate;

the input end of the first transmission gate receives the first limiting voltage, the control end of the first transmission gate receives the first feedback signal, and the output end of the first transmission gate is connected to the output end of the second clamping unit;

the input end of the second transmission gate receives the second temperature control voltage, the control end of the second transmission gate receives the second feedback signal, and the output end of the second transmission gate is connected to the output end of the second clamping unit;

the input end of the third transmission gate receives the second limiting voltage, the control end of the third transmission gate receives the third feedback signal, and the output end of the third transmission gate is connected to the output end of the second clamping unit.

15. The power supply circuit according to claim 14, wherein the control signal generating unit includes: the second comparator, the third comparator, the first AND gate, the second AND gate and the third AND gate;

The positive input end of the second comparator receives the first limiting voltage, the negative input end of the second comparator receives the target output voltage, and the second comparator outputs a second comparison result;

the positive input end of the third comparator receives the target output voltage, the negative input end of the third comparator receives the second limiting voltage, and the third comparator outputs a third comparison result;

the first AND gate receives the second comparison result and the third comparison result respectively, and outputs the first feedback signal;

the second AND gate receives the second comparison result and the inverse value of the third comparison result respectively, and outputs the second feedback signal;

and the third AND gate receives the inverted value of the second comparison result and the third comparison result respectively, and outputs the third feedback signal.

16. A memory comprising the power supply circuit of any one of claims 1 to 15.