CN116088622A - Slow start circuit, low dropout linear voltage regulator, chip and electronic equipment - Google Patents

Abstract

The embodiment of the disclosure provides a slow start circuit, a low dropout linear voltage regulator, a chip and electronic equipment. The slow start circuit includes: first and second current source circuits, first and second tank circuits, and an operational amplifier. The first current source circuit generates a first current under control of a first voltage from the first voltage terminal and provides the first current to the first tank circuit via the first node. The first tank circuit stores charge from the first current to generate a ramp signal. The first input terminal of the operational amplifier is coupled to the first node. The second input terminal of the operational amplifier is coupled to the second node. The output end of the operational amplifier is coupled with the second current source circuit. The second current source circuit generates a second current under the control of the output signal of the operational amplifier and the reference voltage from the reference voltage terminal, and supplies the second current to the second tank circuit via the second node. The second tank circuit stores charge from the second current to generate a soft start signal at the second node.

Description

Slow start circuit, low dropout linear voltage regulator, chip and electronic equipment

Technical Field

The embodiment of the disclosure relates to the technical field of integrated circuits, in particular to a slow start circuit, a low dropout linear voltage regulator, a chip and electronic equipment.

Background

Low dropout linear regulators (Low Dropout Regulator, LDOs for short) are widely used in integrated circuits for providing a supply voltage required inside the integrated circuits. During the start-up phase of the LDO, it is desirable that the LDO inner loop be slowly established to avoid the output of the LDO from generating a large inrush current. Accordingly, a slow start circuit may be provided in the LDO to help the LDO start slowly.

Disclosure of Invention

Embodiments described herein provide a slow start circuit, a low dropout linear regulator, a chip, and an electronic device.

According to a first aspect of the present disclosure, a soft start circuit is provided. The slow start circuit includes: the circuit comprises a first current source circuit, a second current source circuit, a first energy storage circuit, a second energy storage circuit and an operational amplifier. The first current source circuit is configured to generate a first current under control of a first voltage from the first voltage terminal and to provide the first current to the first tank circuit via the first node. The first tank circuit is configured to store charge from the first current to generate a ramp signal. The first input terminal of the operational amplifier is coupled to the first node. The second input terminal of the operational amplifier is coupled to the second node. The output end of the operational amplifier is coupled with the second current source circuit. The second current source circuit is configured to generate a second current under control of an output signal of the operational amplifier and a reference voltage from the reference voltage terminal and to provide the second current to the second tank circuit via the second node. The second tank circuit is configured to store charge from the second current to generate a soft start signal at the second node.

In some embodiments of the present disclosure, the first current source circuit includes: a first transistor. The control electrode of the first transistor is coupled to the bias voltage terminal. The first electrode of the first transistor is coupled to the first voltage terminal. The second pole of the first transistor is coupled to the first node.

In some embodiments of the present disclosure, the second current source circuit includes: and a second transistor. Wherein the control electrode of the second transistor is coupled to the output terminal of the operational amplifier. The first electrode of the second transistor is coupled to the reference voltage terminal. The second diode of the second transistor is coupled to the second node.

In some embodiments of the present disclosure, the first tank circuit includes: a first capacitor. Wherein a first end of the first capacitor is coupled to the first node. The second terminal of the first capacitor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the second tank circuit includes: and a second capacitor. Wherein the first end of the second capacitor is coupled to the second node. The second terminal of the second capacitor is coupled to the second voltage terminal.

In some embodiments of the present disclosure, the first input of the operational amplifier is an inverting input. The second input of the operational amplifier is a non-inverting input.

According to a second aspect of the present disclosure, a soft start circuit is provided. The slow start circuit includes: a first transistor, a second transistor, a first capacitor, a second capacitor, and an operational amplifier. The control electrode of the first transistor is coupled to the bias voltage terminal. The first electrode of the first transistor is coupled to the first voltage terminal. The second pole of the first transistor is coupled to the inverting input of the operational amplifier and the first end of the first capacitor. The control electrode of the second transistor is coupled to the output end of the operational amplifier. The first electrode of the second transistor is coupled to the reference voltage terminal. The second diode of the second transistor is coupled to the non-inverting input of the operational amplifier and to the first terminal of the second capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal. The second terminal of the second capacitor is coupled to the second voltage terminal.

According to a third aspect of the present disclosure, a low dropout linear regulator is provided. The low dropout linear regulator includes: a slow start circuit according to the first or second aspect of the present disclosure.

According to a fourth aspect of the present disclosure, a chip is provided. The chip comprises a low dropout linear regulator according to the third aspect of the present disclosure.

According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a chip according to the fourth aspect of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 is an exemplary circuit diagram of a soft start circuit and a low dropout linear regulator;

fig. 2 is an equivalent circuit diagram of the low dropout linear regulator shown in fig. 1;

FIG. 3 is a timing diagram of some of the signals used in the low dropout linear regulator shown in FIG. 1;

FIG. 4 is a schematic block diagram of a slow start circuit according to an embodiment of the present disclosure;

FIG. 5 is an exemplary circuit diagram of the slow start circuit and low dropout linear regulator of the embodiment shown in FIG. 4; and

fig. 6 is a timing diagram of some of the signals for the low dropout linear regulator shown in fig. 5.

In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

Fig. 1 shows an exemplary circuit diagram of a soft start circuit 120 and a low dropout linear regulator 110. Although the soft-start circuit 120 is shown in fig. 1 as being independent of the low dropout linear regulator 110, the soft-start circuit 120 may be considered to be part of the low dropout linear regulator 110 in an alternative example of fig. 1.

In the example of fig. 1, the current source I1 may charge the capacitor C to generate the ramp signal Vsl on the upper plate of the capacitor C. The ramp signal Vsl is supplied to the gate of the transistor Mp 1. The control electrode of the transistor Mp2 is supplied with a fixed reference voltage Vref. The control electrode of the transistor Mp3 is supplied with the feedback voltage Vfb. The feedback voltage Vfb is the output voltage V of the low dropout regulator 110 through the resistor R1 and the resistor R2 _LDO And performing partial pressure. The aspect ratio of the transistor Mp1, the transistor Mp2, and the transistor Mp3 are equal.

When the voltage of the ramp signal Vsl is far smaller than the reference voltage Vref, it is known from the circuit connection relationship that approximately half of the tail current flows into the transistor Mp1, the other half flows into the transistor Mp3, and the transistor Mp2 is disabled at this time. In the overall closed loop configuration, the feedback voltage vfb=vsl.

When the voltage of the ramp signal Vsl is much larger than the reference voltage Vref, approximately half of the current in the tail current of the op-amp flows into the transistor Mp2, and the other half flows into the transistor Mp3. At this time, vfb=vref under the closed loop action of the overall structure.

The structure shown in fig. 1 has the following problems: when vsl=vref, the structural circuit shown in fig. 1 can be equivalent to that shown in fig. 2. The transistor Mp1 and the transistor Mp2 can be equivalent to the transistor Mc. The transistor Mc and the transistor Mp3 form an op-amp input pair. The width-to-length ratio of the transistor Mc becomes twice that of the transistor Mp1 (or the transistor Mp 2). Therefore, the width-to-length ratio of the transistor Mc is also twice that of the transistor Mp3. Under the action of the closed loop of the whole structure, the current flowing through the transistor Mc is equal to that flowing through the transistor Mp3, but the width-to-length ratio of the transistor Mc is larger than that of the transistor Mp3, which is equivalent to the artificial mismatch. According to the current formula of the MOS tube, the following is known:

the |Vgs_Mc| < |Vgs_Mp3|, i.e., |Vsl-Vs| < |Vfb-Vs|.

Where vgs_mc represents the gate-source voltage of the transistor Mc, vgs_mp3 represents the gate-source voltage of the transistor Mp3, and Vs represents the source voltage of the transistor Mc (or the source voltage of the transistor Mp 3).

From the above equation, the relationship between Vfb and Vsl is:

Vfb<Vsl＝Vref。

due to the output voltage V of LDO _LDO Is a multiple (e.g. beta) of the feedback voltage Vfb, thus the output voltage V of LDO _LDO <The waveform of the output voltage of the LDO at vref×β will appear in the "arc" shaped section shown in fig. 3 when vsl=vref, and the "arc" shape will not disappear until the ramp signal Vsl rises far above the reference voltage Vref (at this time, almost no current flows through the transistor Mp 1).

To avoid the mismatch problem _LDO Embodiments of the present disclosure propose a slow start circuit. Fig. 4 shows a schematic block diagram of a slow start circuit 420 according to an embodiment of the present disclosure. The slow start circuit 420 includes: a first current source circuit 421, a second current source circuit 423, a first tank circuit 422, a second tank circuit 424, and an operational amplifier a.

The first current source circuit 421 is coupled to the first tank circuit 422 and the first input terminal of the operational amplifier a via the first node N1. The first current source circuit 421 is further coupled to the first voltage terminal V1. The first current source circuit 421 is configured to: the first current I1 is generated under control of a first voltage from the first voltage terminal V1 and provided to the first tank circuit 422 via the first node N1.

The first tank circuit 422 is coupled to the first current source circuit 421 and the first input terminal of the operational amplifier a via the first node N1. The first tank circuit 422 is further coupled to the second voltage terminal V2. The first tank circuit 422 is configured to store charge from the first current I1 to generate a ramp signal Vsl.

The first input terminal of the operational amplifier A is coupled to the first node N1. The second input terminal of the operational amplifier A is coupled to the second node N2. The output terminal of the operational amplifier a is coupled to the second current source circuit 423.

The second current source circuit 423 is coupled to the second tank circuit 424 and the second input terminal of the operational amplifier a via the second node N2. The second current source circuit 423 is further coupled to the reference voltage terminal Vref and the output terminal of the operational amplifier a. The second current source circuit 423 is configured to generate a second current I2 under control of an output signal of the operational amplifier a (i.e., a signal output from an output terminal of the operational amplifier a) and a reference voltage Vref from a reference voltage terminal Vref, and to supply the second current I2 to the second tank circuit 424 via a second node N2.

The second tank circuit 424 is coupled to the second current source circuit 423 and the second input terminal of the operational amplifier a via the second node N2. The second tank circuit 424 is configured to store charge from the second current I2 to generate a soft start signal at the second node N2.

The voltage at the first node N1 is equal to the voltage at the second node N2 under the clamping action of the operational amplifier a at the beginning. Therefore, the slow start signal has the same slope as the ramp signal Vsl at the beginning. When the voltage of the first node N1 is greater than the voltage of the second node N2, the operational amplifier a is switched from the closed-loop mode to the open-loop mode. The voltage of the second node N2 is at most equal to the reference voltage Vref.

The slow start signal may be provided to one input of an error amplifier in the LDO (e.g., the gate of transistor Mp2 in fig. 1), causing the LDO to start slowly.

In some embodiments of the present disclosure, the first input of the operational amplifier a is an inverting input. The second input of the operational amplifier a is a non-inverting input.

Fig. 5 shows an exemplary circuit diagram of the soft start circuit 520 of the embodiment shown in fig. 4. The first current source circuit 521 includes: a first transistor M1. The control electrode of the first transistor M1 is coupled to the bias voltage terminal Vb. The first pole of the first transistor M1 is coupled to the first voltage terminal V1. The second pole of the first transistor M1 is coupled to the first node N1. The magnitude of the first current I1 can be adjusted by adjusting the magnitude of the bias voltage terminal Vb, thereby adjusting the slope of the ramp signal Vsl.

The second current source circuit 523 includes: and a second transistor M2. The control electrode of the second transistor M2 is coupled to the output terminal of the operational amplifier a. The first pole of the second transistor M2 is coupled to the reference voltage terminal Vref. The second diode of the second transistor M2 is coupled to the second node N2.

The first tank circuit 522 includes: a first capacitor C1. Wherein, the first end of the first capacitor C1 is coupled to the first node N1. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2.

The second tank circuit 524 includes: and a second capacitor C2. Wherein the first end of the second capacitor C2 is coupled to the second node N2. The second terminal of the second capacitor C2 is coupled to the second voltage terminal V2.

The first current I1 is injected into the first capacitor C1 to generate the ramp signal Vsl required for the slow start. Under the clamping action of the operational amplifier A, the voltage of the first node N1 is equal to the voltage of the second node N2. It can be seen that the voltage of the second node N2 is not increased again after rising to be equal to the reference voltage Vref with the same slope as the voltage of the first node N1. The voltage at the first node N1 continues to rise under the effect of the first current I1 charging the first capacitor C1. When the voltage of the first node N1 is greater than the voltage of the second node N2, the operational amplifier a is switched from the closed-loop mode to the open-loop mode. The operational amplifier a outputs a low level to fully turn on the second transistor M2, and the voltage of the second node N2 is equal to the reference voltage Vref. The voltage of the first node N1 continues to rise to the first voltage V1.

In the scheme shown in fig. 1, the control electrode of the transistor Mp2 is supplied with a fixed reference voltage Vref, whereas in the scheme shown in fig. 5, the control electrode of the transistor Mp2 is supplied with a voltage signal having a slow start-up procedure and a final value equal to Vref. The ratio of the input to the aspect ratio of LDO 510 (transistors Mp2 and Mp 3) is still 1:1, there is no artificially introduced mismatch. According to relation V of output voltage of LDO _LDO As can be seen from =vfb× (r1+r2)/r1=vref× (r1+r2)/R1, the scheme shown in fig. 5 can make the LDO output voltage V _LDO The voltage waveform of (2) is shown in fig. 6. The solution shown in fig. 5 eliminates the problems that exist in the solution shown in fig. 1. As shown in FIG. 6, the output voltage V of LDO _LDO There is no interval of "arc" shape.

In the example of fig. 5, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. The voltage value of the high voltage signal input from the first voltage terminal V1 is higher than the reference voltage Vref. The first transistor M1 and the second transistor M2 are PMOS transistors. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 5 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 5.

The embodiment of the disclosure also provides an LDO. The LDO includes a soft start circuit according to an embodiment of the present disclosure. One input end of the LDO input pair is coupled with the output end of the slow start circuit, so that the LDO is slowly started by utilizing the slow start signal output by the slow start circuit.

The embodiment of the disclosure also provides a chip. The chip includes an LDO according to an embodiment of the present disclosure. The chip is, for example, a power management type chip.

The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is for example a smart terminal device such as a tablet computer, a smart phone or the like.

In summary, the slow start circuit according to the embodiments of the present disclosure can avoid introducing mismatch to the LDO to which it is coupled, so that the output voltage of the LDO does not have a nonlinear interval.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A slow start circuit comprising: a first current source circuit, a second current source circuit, a first tank circuit, a second tank circuit, and an operational amplifier,

wherein the first current source circuit is configured to generate a first current under control of a first voltage from a first voltage terminal and to provide the first current to the first tank circuit via a first node;

the first tank circuit is configured to store charge from the first current to generate a ramp signal;

the first input end of the operational amplifier is coupled with the first node, the second input end of the operational amplifier is coupled with the second node, and the output end of the operational amplifier is coupled with the second current source circuit;

the second current source circuit is configured to generate a second current under the control of an output signal of the operational amplifier and a reference voltage from a reference voltage terminal, and to provide the second current to the second tank circuit via the second node;

the second tank circuit is configured to store charge from the second current to generate a soft start signal at the second node.

2. The slow start circuit of claim 1, wherein the first current source circuit comprises: the first transistor(s) is (are) formed,

the control electrode of the first transistor is coupled to the bias voltage terminal, the first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the first node.

3. The slow start circuit of claim 1, wherein the second current source circuit comprises: a second transistor is provided for the purpose of providing a second transistor,

the control electrode of the second transistor is coupled to the output end of the operational amplifier, the first electrode of the second transistor is coupled to the reference voltage end, and the second electrode of the second transistor is coupled to the second node.

4. The slow start circuit of claim 1, wherein the first tank circuit comprises: the first capacitor is arranged to be connected to the first capacitor,

the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second voltage end.

5. The slow start circuit of any one of claims 1 to 4, wherein the second tank circuit comprises: the second capacitor is used to form a second capacitor,

the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the second voltage end.

6. The slow start circuit of any one of claims 1 to 4, wherein the first input of the operational amplifier is an inverting input and the second input of the operational amplifier is a non-inverting input.

7. A slow start circuit comprising: a first transistor, a second transistor, a first capacitor, a second capacitor, and an operational amplifier,

the control electrode of the first transistor is coupled with a bias voltage end, the first electrode of the first transistor is coupled with a first voltage end, and the second electrode of the first transistor is coupled with the inverting input end of the operational amplifier and the first end of the first capacitor;

the control electrode of the second transistor is coupled with the output end of the operational amplifier, the first electrode of the second transistor is coupled with the reference voltage end, and the second electrode of the second transistor is coupled with the non-inverting input end of the operational amplifier and the first end of the second capacitor;

the second end of the first capacitor is coupled with a second voltage end;

the second terminal of the second capacitor is coupled to the second voltage terminal.

8. A low dropout linear regulator comprising: the slow start circuit according to any one of claims 1-7.

9. A chip, comprising: the low dropout linear regulator according to claim 8.

10. An electronic device, comprising: the chip of claim 9.

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