CN116087756B - Chip voltage detection method and device based on digital ring oscillator - Google Patents
Chip voltage detection method and device based on digital ring oscillator Download PDFInfo
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Abstract
The invention provides a chip voltage detection method and device based on a digital ring oscillator. The method provided by the invention comprises the steps of firstly testing a chip by adopting a plurality of different test voltages at two different temperatures, respectively obtaining two groups of RO values, then calculating according to the obtained two groups of RO value fitting functions to obtain voltage conversion coefficients, obtaining calibration voltages corresponding to the two different temperatures through the voltage conversion coefficients, further obtaining a temperature calibration coefficient according to the calibration voltages, and finally calibrating the voltage by utilizing the temperature calibration coefficient to obtain the actual voltage of the chip at the specific temperature. The technical scheme provided by the invention can realize the detection of the chip voltage by adopting a pure digital logic circuit without additional power supply, the sampling precision can reach mV level, and the reading of the voltage in the 200 MHz-500 Mhz frequency band can be realized.
Description
Technical Field
The present invention relates to the field of chip voltage detection, and in particular, to a method and apparatus for detecting chip voltage based on a digital ring oscillator.
Background
In the prior art, an analog circuit is used for grabbing the internal voltage of the chip.
In general, an analog voltage detection module includes: analog sensors, typically using piezoresistors; the analog-to-digital conversion module is used for converting the analog signal into a digital signal; the filtering module is used for filtering voltage noise generated by the analog sensor due to temperature influence, voltage noise caused by high-frequency voltage noise and the like; the temperature compensation module is used for compensating a change value of the sampling value of the analog sensor, which is influenced by temperature; and the calibration voltage is used for providing a voltage with known and stable value to calibrate, thereby improving the output precision.
However, the analog circuit voltage detection module has the following problems, although the accuracy is high:
1. the sampling rate is lower, namely the level of KHz/us can be achieved, however, the working frequency of the chip depends on the voltage of an MOS tube in the chip rather than the power output voltage, when the chip works at the GHz frequency, the power noise frequency influenced by the time sequence can also jump from a plurality of KHz to a plurality of GHz, only the power noise with higher frequency is accurately grabbed, the corresponding time sequence is more accurate, and obviously the analog voltage detection module at the level of KHz cannot meet the requirement of grabbing high-frequency voltage drop;
2. to increase accuracy, it is often necessary to additionally provide a very stable voltage, which increases the design cost.
Disclosure of Invention
In view of the above, the present invention provides a method and apparatus for detecting a chip voltage based on a digital ring oscillator, which are used for solving the above-mentioned technical problems in the prior art.
According to one aspect of the present invention, there is provided a digital ring oscillator-based chip voltage detection method comprising the steps of:
s1: testing the chip at a first temperature and a second temperature by adopting a plurality of different test voltages respectively, and obtaining a first set of RO values of the chip corresponding to the plurality of different test voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different test voltages at the second temperature respectively, wherein the RO values represent the pulse quantity generated by the ring oscillator in unit time;
s2: obtaining a first voltage conversion coefficient P corresponding to the first set of RO values according to the first set of RO values and the second set of RO values 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 And a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 ；
S3: according to the first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 Third voltage conversion coefficient P 3 Obtaining a first calibration of the chip at a first temperatureVoltage V 1 The method comprises the steps of carrying out a first treatment on the surface of the According to the fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 Sixth voltage conversion coefficient P 6 Obtaining a second calibration voltage V of the chip at a second temperature 2 ；
S4: according to the first calibration voltage V 1 With a second calibration voltage V 2 Obtaining a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 ；
S5: according to a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 The actual voltage of the chip at a specific temperature is output.
According to another aspect of the present invention, there is provided a digital ring oscillator-based chip voltage detection apparatus, the apparatus comprising:
the voltage testing module is configured to test the chip at a first temperature and a second temperature by adopting a plurality of different testing voltages respectively, and respectively obtain a first set of RO values of the chip corresponding to the plurality of different testing voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different testing voltages at the second temperature, wherein the RO values represent the number of pulses generated by the ring oscillator in unit time;
a voltage conversion module configured to obtain a first voltage conversion coefficient P corresponding to the first set of RO values according to the first set of RO values and the second set of RO values, respectively 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 And a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 ；
A voltage calculation module configured to convert the first voltage according to the first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 Third voltage conversion coefficient P 3 Obtaining a first calibration voltage V of the chip at a first temperature 1 The method comprises the steps of carrying out a first treatment on the surface of the According to the fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 Sixth voltage conversion coefficient P 6 Obtaining a second calibration voltage V of the chip at a second temperature 2 ；
A temperature calibration module configured to calibrate the voltage according to the first calibration voltage V 1 With a second calibration voltage V 2 Obtaining a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 ；
An actual voltage detection module configured to calibrate the coefficient T according to a first temperature 1 Second temperature calibration coefficient T 2 The actual voltage of the chip at a specific temperature is output.
According to still another aspect of the present invention, there is provided an electronic apparatus including: one or more processors and a memory, wherein the memory is to store executable instructions; the one or more processors are configured to implement the methods described above via executable instructions.
According to still another aspect of the present invention, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the above-described method.
From the above technical solution, the technical solution provided by the present invention has at least the following advantages:
the combined circuit of the general multi-output digital logic ring oscillator, the pulse counter and the accumulator is adopted to realize the response to the high-frequency voltage, the circuit is a pure digital logic circuit, all logic is powered by the measured voltage domain voltage, and no additional power supply or reference voltage is needed to calculate the voltage;
the sampling frequency and the sampling precision of the voltage can be controlled, so that the sampling frequency can reach hundreds of MHz to GHz, and according to the requirement of the sampling frequency, the sampling precision can reach mV level, and the reading of the voltage in the 200 MHz-500 Mhz frequency band is realized.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.
Fig. 1 shows a block diagram of a prior art voltage detection device;
FIG. 2 shows a flow chart of a voltage detection method provided by an exemplary embodiment of the present invention;
fig. 3 shows a block diagram of a voltage detection apparatus provided by an exemplary embodiment of the present invention;
fig. 4 is a block diagram showing the structure of a control module in the voltage detection apparatus according to the exemplary embodiment of the present invention;
fig. 5 shows a block diagram of an electronic device according to an exemplary embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative, and is not intended to be any limitation on the invention, its application or use. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the elements may be one or more. As used in this specification, the term "plurality/number" means two or more, and the term "based on" should be interpreted as "based at least in part on". Furthermore, the term "and/or" and "at least one of … …" encompasses any and all possible combinations of the listed items.
In addition, in this specification there are descriptions of "first," "second," "third," etc., which are for descriptive purposes only and are not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features indicated.
In the prior art, an analog circuit is used for grabbing the internal voltage of the chip, but the analog circuit has a low speed and cannot grab the transient high-frequency voltage, and fig. 1 shows a structural block diagram of a voltage detection device in the prior art. The invention provides a method for voltage testing by adopting a pure digital circuit so as to realize the correspondence of high-frequency voltage. In addition, the invention adopts a general multi-output digital logic Ring Oscillator (RO), a pulse counter and an accumulator to obtain the RO value of the chip, and the RO value and the test voltage of the chip can be found to be in a quadratic function relationship through chip simulation, and the RO value and the chip temperature are in a linear relationship. The RO value represents the number of pulses generated by the ring oscillator per unit time, which can be recorded by a counter.
Based on the above relation, the chip can be tested at a plurality of different temperatures by adopting a plurality of different test voltages respectively, so as to obtain a plurality of groups of test data, and each group of test data records a plurality of test voltages and RO values corresponding to each test voltage.
Then, a quadratic polynomial (v=p a ×Cunt 2 +P b ×Cunt+P c ) Fitting with multiple groups of actual test data, substituting the actual test data into a test data solution equation to calculate P a 、P b And P c The specific values of the three coefficients, namely the functional equation between the RO value and the chip voltage, can be obtained. Wherein Cunt is the RO value corresponding to a certain temperature. At this time, for any RO value, the corresponding voltage at a certain temperature can be solved. And because the calculated voltage and the chip temperature are in a linear relation, a temperature compensation function can be set to carry out temperature compensation on the calculated voltage so as to obtain the actual voltage of the chip.
Let the temperature compensation function be: actual voltage=t m X temperature value +T b Wherein T is m And T b For the temperature calibration parameter, the voltage may be calibrated according to the actual temperature value. Because the temperature compensation function is a linear equation, T can be calculated by substituting two sets of voltage and temperature values m And T is b Is a value of (2).
The actual voltage of the chip can be calculated through the temperature compensation function.
The foregoing parts of the specification briefly introduce the basic principles of the present invention, and the following parts describe embodiments of the present invention in detail with reference to the drawings.
One aspect of the invention provides a method for detecting chip voltage based on a digital ring oscillator.
Referring to fig. 2, a flow chart of a method provided by an exemplary embodiment of the present invention is shown.
The method provided by the invention comprises the following steps of:
s1: testing the chip at a first temperature and a second temperature by adopting a plurality of different test voltages, and respectively obtaining a first set of RO values of the chip corresponding to the plurality of different test voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different test voltages at the second temperature;
s2: obtaining a first voltage conversion coefficient P corresponding to the first set of RO values according to the first set of RO values and the second set of RO values 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 And a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 ；
S3: according to the first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 Third voltage conversion coefficient P 3 Obtaining a first calibration voltage V of the chip at a first temperature 1 The method comprises the steps of carrying out a first treatment on the surface of the According to the fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 Sixth voltage conversion coefficient P 6 Obtaining a second calibration voltage V of the chip at a second temperature 2 ；
S4: according to the first calibration voltage V 1 With a second calibration voltage V 2 Obtaining a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 ；
S5: according to a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 The actual voltage of the chip at a specific temperature is output.
In a preferred embodiment, the plurality of different test voltages at the first temperature in S1 are recorded as
Which corresponds to a first set of RO values obtained as +.>
The plurality of different test voltages at the second temperature is denoted +.>
Which corresponds to a second set of RO values obtained as +.>
Wherein the total number of the plurality of different test voltages is +.>
。
From the above, the RO value and the test voltage of the chip are in quadratic relation, so that the specific values of the voltage conversion coefficients in S2 are calculated as follows. The following section will be described with reference to the first temperature.
Firstly, setting a fitting function as a unitary quadratic equation V 1 =P 1 ×Cunt 2 +P 2 ×Cunt+P 3 Where Cunt is the RO value of the chip at a first temperature corresponding to a different test voltage, then the coefficients of the fit function can be solved by making the mean square error of the fit function and the test data. Of course, those skilled in the art will recognize that this method is not the only way to calculate the unitary quadratic equation, other solutions substantially equivalent to this way, or a method of directly substituting a plurality of RO values to sequentially convert them into the ternary quadratic equation and calculate the coefficients, all of which can be implemented in the present invention S2 to obtain the first voltage conversion coefficient P corresponding to the first set of RO values 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 And a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 The foregoing calculation methods are all within the scope of the present invention.
In a preferred embodiment of the present invention,the mean square error of the fitting function and the test data is:
then it is possible to obtain:
the following settings were further made:
the above equation 1 can be simplified to the following form:
i.e. the following linear system of equations can be obtained:
solving according to the Kramer rule gives the following result:
substituting the result into the linear equation set to obtain the first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 The method comprises the following steps of:
thus, the fitting function at the first temperature is:
。
next, the above-mentioned meter is usedCalculated first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 A first calibration voltage at a certain RO value at a first temperature can be obtained
：
Similarly, the calculation process at the second temperature is explained in the following section. It should be noted that, the calculation manner at the second temperature is not substantially different from the calculation manner at the first temperature, so the same parts will not be described in detail, which does not affect implementation by those skilled in the art.
For the second temperature, a fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 Sixth voltage conversion coefficient P 6 The method comprises the following steps of:
wherein,,
and, in addition, the processing unit,
the fourth voltage conversion coefficient calculated as described above can be used
Fifth voltage conversion coefficient->
And a sixth voltage conversion coefficient->
Deriving a second calibration voltage for a certain RO value at a second temperature>
：
Those skilled in the art know that to obtain the actual voltage of the MOS transistor inside the chip, the voltage needs to be calibrated according to the actual temperature value. Thus, further, as previously described, again due to the linear relationship between the calculated calibration voltage and the chip temperature, a calibration formula can be obtained by calculating the slope and intercept of the linear equation. Let the slope of the linear equation be the first temperature calibration coefficient
The intercept is the second temperature calibration coefficient +.>
The actual voltage of the chip at a specific temperature = =>
X value of specific temperature +>
。
Wherein the first temperature calibration coefficient
Second temperature calibration coefficient->
Calculated by:
the following will specifically describe examples in which the first temperature is 100deg.C, the second temperature is 0deg.C, and the total number of the plurality of different test voltages is 7 (0.65V, 0.70V, 0.75V, 0.85V, 0.95V, 1.05V, and 1.15V respectively). When the first temperature is 100 ℃ and the second temperature is 0 ℃, the values corresponding to the two temperatures are 100 and 0 respectively. It will be appreciated by those skilled in the art that the selection of the two temperature values, the selection of the total number of test voltages, and the selection of different test voltages are not intended to limit the invention, but are merely examples. In the implementation of the invention, the first temperature and the second temperature can take any two values which are different from each other, and the total number of the plurality of different test voltages can be freely selected and can take any values which are different from each other.
In one embodiment, when the specific temperature is 80 ℃, the RO value at 80 ℃ has been read to be 100, at which time the actual voltage of the chip at 80 ℃ needs to be obtained. The steps provided by the present invention are performed sequentially.
Corresponding to S1, the chips were first tested at 100℃and 0℃with test voltages of 0.65V, 0.70V, 0.75V, 0.85V, 0.95V, 1.05V and 1.15V, respectively, to obtain RO values of the chips. The RO value of the obtained chip is a single test result, and the RO value is affected by voltage and temperature, so that the RO value needs to ensure stable test voltage and test temperature.
The two sets of RO values obtained are tested at 100deg.C and 0deg.C, respectively, as shown in Table 1 below:
corresponding to S2, voltage conversion coefficients are calculated from the obtained first set of RO values and the second set of RO values, respectively. From the foregoing, the RO value and the chip voltage are in quadratic relation, so specific values of the respective voltage conversion coefficients in S2 are calculated as follows.
For the first set of RO values, a fitting function is set to a first calibration voltage V 1 =P 1 ×Cunt 2 +P 2 ×Cunt+P 3 At this time, the total number of the plurality of different test voltages
Taking 7, test voltage +.>
The method comprises the following steps of: />
Then the corresponding obtained first set of RO values
. Sequentially calculating a first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 The method comprises the following steps of: />
For the second set of RO values, a fitting function is set to a second calibration voltage V 2 =P 4 ×Cunt 2 +P 5 ×Cunt+P 6 At this time, the total number of the plurality of different test voltages
Taking 7, the test voltage of a plurality of different test voltages at the second temperature +.>
The method comprises the following steps of: />
Then the corresponding obtained second set of RO values +.>
. Sequentially calculating a fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 Sixth voltage conversion coefficient P 6 The method comprises the following steps of: />
Corresponding to S3, respectively calculating a first calibration voltage of the chip at a first temperature of 100 ℃ and a second calibration voltage of the chip at a second temperature of 0 ℃:
corresponding to S4, calculating a first temperature calibration coefficient
Second temperature calibration coefficient->
The method comprises the following steps of:
corresponding to S5, the actual voltage of the chip at 80 ℃ can be obtained =
。
In addition, it should be noted that steps S1 and S2 in the present invention are completed in the chip test stage, and the first voltage conversion coefficient P is obtained 1 Second voltage conversion coefficient P 2 Third voltage conversion coefficient P 3 Fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 The 6 values will then be written into an on-chip memory cell, preferably an eFuse memory cell, of the chip. In practical applications, S3 to S5 may be performed by the firmware of the microcontroller provided on the chip in accordance with the results obtained in S1-S2.
It will be appreciated by those skilled in the art that each chip is independent and the test results of the individual chips are individual rather than generic, and therefore, steps S1 to S5 need to be performed for each chip to detect the actual voltage inside the chip.
Another aspect of the invention provides a digital ring oscillator based chip voltage detection apparatus.
Referring to fig. 3, a block diagram of an apparatus according to an exemplary embodiment of the present invention is shown.
The device provided by the invention comprises the following modules:
the voltage testing module is configured to test the chip at a first temperature and a second temperature by adopting a plurality of different testing voltages respectively, and respectively obtain a first set of RO values of the chip corresponding to the plurality of different testing voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different testing voltages at the second temperature;
the voltage testing module is configured to test the chip at a first temperature and a second temperature by adopting a plurality of different testing voltages respectively, and respectively obtain a first set of RO values of the chip corresponding to the plurality of different testing voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different testing voltages at the second temperature;
a voltage conversion module configured to obtain a first voltage conversion coefficient P corresponding to the first set of RO values according to the first set of RO values and the second set of RO values, respectively 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 And a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 ；
A voltage calculation module configured to convert the first voltage according to the first voltage conversion coefficient P 1 Second voltage conversion coefficient P 2 Third voltage conversion coefficient P 3 Obtaining a first calibration voltage V of the chip at a first temperature 1 The method comprises the steps of carrying out a first treatment on the surface of the According to the fourth voltage conversion coefficient P 4 Fifth voltage conversion coefficient P 5 Sixth voltage conversion coefficient P 6 Obtaining a second calibration voltage V of the chip at a second temperature 2 ；
A temperature calibration module configured to calibrate the voltage according to the first calibration voltage V 1 With a second calibration voltage V 2 Obtaining a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 ；
An actual voltage detection module configured to calibrate the coefficient T according to a first temperature 1 Second temperature calibration coefficient T 2 The actual voltage of the chip at a specific temperature is output.
It should be understood that the various modules of the apparatus shown in fig. 3 may correspond to the various steps in the method described earlier in this specification. Thus, the operations, features and advantages described above for the method are equally applicable to the apparatus and the modules comprised thereof. For brevity, certain operations, features and advantages are not described in detail herein.
Although specific functions are discussed above with reference to specific modules, it should be noted that the functions of each module in the present disclosure may also be implemented by dividing the functions into a plurality of modules, and/or at least some functions of the plurality of modules may be implemented by combining at least some functions of the plurality of modules into a single module. The manner in which a particular module performs an action in the present disclosure includes that the particular module itself performs the action, or that the particular module invokes or otherwise accesses the performed action (or performs the action in conjunction with the particular module). Thus, a particular module that performs an action may include that particular module itself that performs the action and/or another module that the particular module invokes or otherwise accesses that performs the action.
In addition, the control module arranged inside the chip in the invention comprises a general multi-output digital logic ring oscillator, a pulse counter and an accumulator, which can realize the response to the high-frequency voltage, and the structural block diagram of the control module is shown in fig. 4. The first set of RO values and the second set of RO values are generated by the control module.
In addition to the technical scheme, the invention further provides electronic equipment, which comprises one or more processors and a memory for storing executable instructions. Wherein the one or more processors are configured to implement the above-described methods via executable instructions.
The invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the above method.
In the following part of the present description, illustrative examples of the aforementioned electronic device, non-transitory computer readable storage medium, and computer program product will be described in connection with fig. 5.
Fig. 5 shows an example configuration of an electronic device 300 that may be used to implement the methods described herein. The neural network segmentation system provided by the technical scheme of the invention can also be completely or at least partially realized by the electronic device 300 or similar devices or systems.
The electronic device 300 may be a variety of different types of devices. Examples of electronic device 300 include, but are not limited to: a desktop, server, notebook, or netbook computer, a mobile device (e.g., tablet, cellular, or other wireless telephone (e.g., smart phone), notepad computer, mobile station), a wearable device (e.g., glasses, watch), an entertainment appliance (e.g., an entertainment appliance, a set-top box communicatively coupled to a display device, a gaming machine), a television or other display device, an automotive computer, and so forth.
Memory 304 and mass storage device 303 are examples of computer-readable storage media for storing instructions that are executed by processor 302 to implement the various functions as previously described. For example, memory 304 may generally include both volatile memory and nonvolatile memory (e.g., RAM, ROM, etc.). In addition, mass storage device 303 may generally include hard disk drives, solid state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CD, DVD), storage arrays, network attached storage, storage area networks, and the like. Memory 304 and mass storage device 303 may both be referred to collectively as memory or a computer-readable storage medium in the present invention, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that may be executed by processor 302 as a particular machine configured to implement the operations and functions described in the examples of the present invention.
A number of programs may be stored on the mass storage device 303. These programs include an operating system 305, one or more application programs 306, other programs 307, and program data 308, and they may be loaded into memory 304 for execution. Examples of such application programs or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing the following components/functions: a digital ring oscillator based chip voltage detection method (including any suitable steps of the method) and/or additional embodiments described herein.
Although illustrated in fig. 5 as being stored in memory 304 of electronic device 300, operating system 305, one or more application programs 306, other programs 307, and program data 308, or portions thereof, may be implemented using any form of computer readable media accessible by electronic device 300. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.
Communication media includes, for example, computer readable instructions, data structures, program modules, or other data in a communication signal that is transferred from one system to another system. Communication media may include conductive transmission media such as electrical cables and wires, and wireless media such as acoustic, electromagnetic, RF, microwave, and infrared, capable of transmitting energy waves. Computer readable instructions, data structures, program modules, or other data may be embodied as a modulated data signal, such as in a wireless medium (e.g., carrier wave, or similar mechanism that is implemented as part of a spread spectrum technology, for example). The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. The modulation may be analog, digital or hybrid modulation techniques.
By way of example, computer-readable storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. For example, computer-readable storage media include, but are not limited to, volatile memory, such as random access memory (RAM, DRAM, SRAM); and non-volatile memories such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic/ferroelectric memories (MRAM, feRAM); and magnetic and optical storage devices (hard disk, tape, CD, DVD); or other known media or later developed computer-readable information/data that may be stored for use by a computer system.
One or more communication interfaces 309 are used to exchange data with other devices, such as via a network, direct connection, or the like. Such communication interfaces may be one or more of the following: any type of network interface (e.g., a Network Interface Card (NIC)), a wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, a worldwide interoperability for microwave access (Wi-MAX) interface, an ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, a Near Field Communication (NFC) interface, etc. The communication interface 309 may facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the internet, etc. The communication interface 309 may also provide communication with external storage devices (not shown) such as in a storage array, network attached storage, storage area network, or the like.
In some examples, a display device 301, such as a monitor, may be included for displaying information and images to a user. Other I/O devices 310 may be devices that receive various inputs from a user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input/output devices, and so on.
The technical solutions described in the present invention may be supported by these various configurations of the electronic device 300, and are not limited to the specific examples of the technical solutions described in the present invention.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. A plurality of units or means recited in the apparatus claims can also be implemented by means of one unit or means in software or hardware.
Claims (30)
1. A method for detecting chip voltage based on a digital ring oscillator, the method comprising the steps of:
s1: testing the chip at a first temperature and a second temperature by adopting a plurality of different test voltages, respectively, and obtaining a first set of RO values of the chip corresponding to the plurality of different test voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different test voltages at the second temperature, wherein the RO values represent the pulse quantity generated by the ring oscillator in unit time;
s2: according to the quadratic function relationship between the first set of RO values and the second set of RO values and the test voltage of the chip, respectively, to obtain a first voltage conversion coefficient P corresponding to the first set of RO values 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 According to test voltage=p 1 Value of x RO 2 + P 2 X RO value +P 3 Fitting a function to a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 According to test voltage=p 4 Value of x RO 2 + P 5 X RO value +P 6 Fitting the function to obtain the first voltage conversion coefficient P by making a mean square error between the fitting function and the test voltage 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 The fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 And the sixth voltage conversion coefficient P 6 ；
S3: according to the first voltage conversion coefficient P 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 Obtaining a first calibration voltage V of the chip at the first temperature 1 The method comprises the steps of carrying out a first treatment on the surface of the According to the fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 Said sixth voltage conversion coefficient P 6 Obtaining a second calibration voltage V of the chip at the second temperature 2 ；
S4: according to the first calibration voltage V 1 With the second calibration voltage V 2 Obtaining a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 ；
S5: according to the first temperature calibration coefficient T 1 The second temperature calibration coefficient T 2 An actual voltage of the chip at a specific temperature is obtained.
2. The method of claim 1, wherein the first set of RO values and the second set of RO values are quadratic in relation to the test voltage of the chip in S1 and S2 and the calibration voltage of the chip and the temperature of the chip in S3 and S4.
3. The method according to claim 2, wherein the first voltage conversion coefficient P in S2 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 The method comprises the following steps of:
wherein,,
and, in addition, the processing unit,
wherein (1)>
For the total number of the plurality of different test voltages, +.>
For the plurality of different test voltages at the first temperature +.>
To correspond to the test voltage +.>
RO value of (2), and->
The first set of RO values is formed.
4. A method according to claim 3, wherein in S2The fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 The sixth voltage conversion coefficient P 6 The method comprises the following steps of:
wherein,,
and, in addition, the processing unit,
wherein (1)>
For the total number of the plurality of different test voltages, +.>
For said plurality of different test voltages at said second temperature +.>
To correspond to the test voltage +.>
RO value of (2), and->
The second set of RO values is constructed.
5. The method according to claim 4, wherein the first calibration voltage V in S3 1 With the second calibration voltage V 2 The method comprises the following steps of:
the method comprises the steps of carrying out a first treatment on the surface of the Wherein, cut is the RO value at the specific temperature.
6. The method according to claim 5, wherein the first temperature calibration coefficient T in S4 1 AndThe second temperature calibration coefficient T 2 The method comprises the following steps of:
7. the method of claim 6, wherein the actual voltage of the chip at a specific temperature in S5 = T 1 X value of specific temperature +T 2 。
8. The method of claim 1, wherein the total number of the plurality of different test voltages is 7.
9. The method of claim 8, wherein the plurality of different voltage points have values of 0.65V, 0.70V, 0.75V, 0.85V, 0.95V, 1.05V, and 1.15V, respectively.
10. The method according to claim 1, wherein the first voltage conversion coefficient P 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 The fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 Said sixth voltage conversion coefficient P 6 Stored in an on-chip memory unit of the chip.
11. The method of claim 10, wherein the on-chip memory cell is an eFuse memory cell.
12. The method of claim 1, wherein the first temperature is 100 ℃ and the second temperature is 0 ℃.
13. The method of claim 1, wherein S3 to S5 are performed by microcontroller firmware included on the chip.
14. The method of claim 1, wherein the chip includes a control module for obtaining the first set of RO values and the second set of RO values, the control module including a digital ring oscillator, a pulse counter, and an accumulator.
15. A digital ring oscillator based chip voltage detection apparatus, the apparatus comprising:
the voltage testing module is configured to test the chip at a first temperature and a second temperature by adopting a plurality of different testing voltages respectively, and respectively obtain a first set of RO values of the chip corresponding to the plurality of different testing voltages at the first temperature and a second set of RO values of the chip corresponding to the plurality of different testing voltages at the second temperature, wherein the RO values represent the number of pulses generated by the ring oscillator in unit time;
a voltage conversion module configured to generate a first voltage conversion coefficient P corresponding to the first set of RO values according to a quadratic function relationship between the first set of RO values and the second set of RO values and the test voltage of the chip 1 Second voltage conversion coefficient P 2 And a third voltage conversion coefficient P 3 According to test voltage=p 1 Value of x RO 2 + P 2 X RO value +P 3 Fitting a function to a fourth voltage conversion coefficient P corresponding to the second set of RO values 4 Fifth voltage conversion coefficient P 5 And a sixth voltage conversion coefficient P 6 According to test voltage=p 4 Value of x RO 2 + P 5 X RO value +P 6 Fitting the function to obtain the first voltage conversion coefficient P by making a mean square error between the fitting function and the test voltage 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 The fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 And the sixth voltage conversion coefficient P 6 ；
A voltage calculation module configured to convert the first voltage conversion coefficient P 1 Said second electricityPressure conversion coefficient P 2 The third voltage conversion coefficient P 3 Obtaining a first calibration voltage V of the chip at the first temperature 1 The method comprises the steps of carrying out a first treatment on the surface of the According to the fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 Said sixth voltage conversion coefficient P 6 Obtaining a second calibration voltage V of the chip at the second temperature 2 ；
A temperature calibration module configured to calibrate the voltage according to the first calibration voltage V 1 With the second calibration voltage V 2 Obtaining a first temperature calibration coefficient T 1 Second temperature calibration coefficient T 2 ；
An actual voltage detection module configured to calibrate the coefficient T according to the first temperature 1 The second temperature calibration coefficient T 2 An actual voltage of the chip at a specific temperature is obtained.
16. The apparatus of claim 15, wherein the first set of RO values and the second set of RO values in the voltage test module and the voltage conversion module are quadratic with the test voltage of the chip, and wherein the calibration voltage of the chip in the voltage calculation module and the temperature calibration module are linear with the temperature of the chip.
17. The apparatus of claim 16, wherein the first voltage conversion coefficient P in the voltage conversion module 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 The method comprises the following steps of:
wherein,,
and, in addition, the processing unit,
wherein (1)>
For the total number of the plurality of different test voltages, +.>
For the plurality of different test voltages at the first temperature +.>
To correspond to the test voltage +.>
RO value of (2), and->
The first set of RO values is formed.
18. The apparatus of claim 17, wherein the fourth voltage conversion coefficient P in the voltage conversion module 4 The fifth voltage conversion coefficient P 5 The sixth voltage conversion coefficient P 6 The method comprises the following steps of:
wherein,,
and, in addition, the processing unit,
wherein (1)>
For the total number of the plurality of different test voltages, +.>
For said plurality of different test voltages at said second temperature +.>
To correspond to the test voltage +.>
RO value of (2), and->
The second set of RO values is constructed.
19. The apparatus of claim 18, wherein the first calibration voltage V in the voltage calculation module 1 With the second calibration voltage V 2 The method comprises the following steps of:
the method comprises the steps of carrying out a first treatment on the surface of the Wherein, cut is the RO value at the specific temperature.
20. The apparatus of claim 19, wherein the first temperature calibration coefficient T in the temperature calibration module 1 The second temperature calibration coefficient T 2 The method comprises the following steps of:
21. the device according to claim 20, wherein the actual voltage of the chip at a specific temperature in the actual voltage detection module = T 1 X value of specific temperature +T 2 。
22. The apparatus of claim 15, wherein a total number of the plurality of different test voltages is 7.
23. The device of claim 22, wherein the plurality of different voltage points have values of 0.65V, 0.70V, 0.75V, 0.85V, 0.95V, 1.05V, and 1.15V, respectively.
24. The apparatus of claim 15, wherein the first voltage conversion coefficient P 1 The second voltage conversion coefficient P 2 The third voltage conversion coefficient P 3 The fourth voltage conversion coefficient P 4 The fifth voltage conversion coefficient P 5 Said sixth voltage conversion coefficient P 6 Stored in an on-chip memory unit of the chip.
25. The apparatus of claim 24, wherein the on-chip memory cell is an eFuse memory cell.
26. The apparatus of claim 15, wherein the first temperature is 100 ℃ and the second temperature is 0 ℃.
27. The apparatus of claim 15, wherein the voltage calculation module to the actual voltage detection module are performed by microcontroller firmware included on the chip.
28. The apparatus of claim 15, wherein the on-chip comprises a control module for obtaining the first set of RO values and the second set of RO values, and wherein the control module comprises a digital ring oscillator, a pulse counter, and an accumulator.
29. An electronic device, the electronic device comprising:
one or more processors;
a memory for storing executable instructions;
the one or more processors are configured to implement the method of any one of claims 1 to 14 via the executable instructions.
30. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, causes the processor to perform the method of any of claims 1 to 14.
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| US5795068A (en) * | 1996-08-30 | 1998-08-18 | Xilinx, Inc. | Method and apparatus for measuring localized temperatures and voltages on integrated circuits |
| KR19990065976A (en) * | 1998-01-20 | 1999-08-16 | 구본준 | Self-calibration circuit of semiconductor device |
| US7091796B2 (en) * | 2003-08-20 | 2006-08-15 | Hewlett-Packard Development Company, L.P. | Method and system for calibration of a voltage controlled oscillator (VCO) |
| US8154353B2 (en) * | 2009-11-03 | 2012-04-10 | Arm Limited | Operating parameter monitor for an integrated circuit |
| US9448125B2 (en) * | 2011-11-01 | 2016-09-20 | Nvidia Corporation | Determining on-chip voltage and temperature |
| JP6415285B2 (en) * | 2014-12-08 | 2018-10-31 | セイコーＮｐｃ株式会社 | Temperature voltage sensor |
| US10527503B2 (en) * | 2016-01-08 | 2020-01-07 | Apple Inc. | Reference circuit for metrology system |
| KR20180078897A (en) * | 2016-12-30 | 2018-07-10 | 삼성전자주식회사 | The test method of semiconductor device and test system for performing the same |
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