CN116074406A

CN116074406A - Instruction sending method and device

Info

Publication number: CN116074406A
Application number: CN202211515601.7A
Authority: CN
Inventors: 全斌; 张军强
Original assignee: Beijing Huafeng Equipment Technology Co ltd
Current assignee: Beijing Huafeng Equipment Technology Co ltd
Priority date: 2022-11-29
Filing date: 2022-11-29
Publication date: 2023-05-05

Abstract

The application relates to an instruction sending method and device, comprising the following steps: when an instruction to be sent is received, writing the instruction into a buffer for buffering, resetting a counter and starting self-counting; performing a first operation and a second operation using a contention mode: the first operation includes: when the counter reaches a preset period threshold, reading the instruction cached by the buffer, packaging the instruction into a frame of data, and resetting the counter; the second operation includes: when the number of the instructions cached in the buffer reaches a preset number threshold, reading the instructions cached in the buffer, packaging the instructions in one frame of data, and resetting a counter; and transmitting the frame of data. The method and the device can improve the sending efficiency of the instruction.

Description

Instruction sending method and device

Technical Field

The present invention relates to the field of semiconductor testing technology, and in particular, to a method and apparatus for sending an instruction, a method and apparatus for receiving an instruction, a computing device, a computer readable storage medium, and a computer program product.

Background

At present, optical fiber communication is carried out between a PCIE card and an interface board of a data receiving end in an ATE test system, wherein the PCIE card and the interface board both adopt FPGA of AMD company as core chips, and a communication protocol is Aurora protocol. The Aurora protocol is characterized by simplicity and high efficiency for short instructions. But has the disadvantage of poor versatility and does not support communication with other corporate FPGA devices. Therefore, when the interface board at the data receiving end adopts FPGAs of other companies (such as the Arria10 model of Intel corporation), the PCIE card and the interface board cannot communicate by using the Aurora protocol, and at this time, the communication between the PCIE card and the interface board can be realized by using the universal protocol Ethernet.

When a data transmitting end (i.e., a PC) in an ATE test system transmits a large number of instructions (all instructions of a tester can be taken as an example, and write instructions are taken as the following) to a data receiving end (a specific instruction transmitting process is that the PC executes PCIE software codes, and the PCIE software codes are transmitted to FIFOs of FPGAs of PCIE through PCIE driving and PCIE ip and then transmitted to the data receiving end through ethernet), because the number of write instructions transmitted by the PC each time is different, time consumption among write instructions is also different, transmission frequency is also different, the PC executes the same section of PCIE software codes, the instructions are transmitted at different times, and intervals among instructions received by the FPGAs are also different, at least 10 cycles, and at most 80 cycles. If the Ethernet protocol is adopted, and a frame of data only contains one instruction, when the instruction interval is shorter (10 periods), the transmission is not timely, the FIFO overflows, and the Ethernet transmission also causes the data overflow problem, resulting in packet loss, and the time for transmitting one instruction is more than that of the Aurora protocol. The situation restricts the quantity and frequency of the sending instructions of the PC, and only a plurality of writing instructions are contained in one frame of data of the Ethernet protocol, so that the communication efficiency of the Ethernet protocol can be improved, even the communication efficiency is close to that of an Aurora protocol.

Under the background, how to determine how many write instructions are specifically included in one frame of Ethernet protocol data, so that the number and frequency of the instructions sent by the PC are not limited, and the one frame of Ethernet protocol data can be quickly sent, thereby improving the communication efficiency, which is a technical problem to be solved.

Disclosure of Invention

In view of the above problems in the prior art, the present application provides an instruction sending method and apparatus, an instruction receiving method and apparatus, a computing device, a computer readable storage medium, and a computer program product, so that the number and frequency of the instructions sent by a PC are not limited, and the communication efficiency can be improved through the Ethernet protocol.

To achieve the above object, a first aspect of the present application provides an instruction sending method, including:

when an instruction to be sent is received, writing the instruction into a buffer for buffering, resetting a counter and starting self-counting;

performing a first operation and a second operation using a contention mode:

the first operation includes: when the counter reaches a preset period threshold, reading the instruction cached by the buffer, packaging the instruction into a frame of data, and resetting the counter;

the second operation includes: when the number of the instructions cached in the buffer reaches a preset number threshold, reading the instructions cached in the buffer, packaging the instructions in one frame of data, and resetting a counter;

and transmitting the frame of data.

The method and the device use the self-adaptive mechanism, so that the Ethernet protocol frame data not only contains the transmission of one instruction, but also can be transmitted with high efficiency no matter how many interval periods are between the instructions, and the quantity and the frequency of the PC transmitting instructions are not restricted.

A second aspect of the present application provides an instruction receiving method, including:

receiving a frame of data transmitted through an Ethernet protocol; the frame data comprises a target MAC address field, a source MAC address field, a length field, an instruction field and a stop instruction field;

analyzing the target MAC address field, the source MAC address field and the length field;

analyzing the instruction field and the stop instruction field, judging that the analyzed stop instruction is obtained, stopping analyzing, caching the instruction, and waiting for the next frame of data; if the instruction is analyzed, caching the instruction, and continuing to analyze the instruction field and the stop instruction field until the stop instruction is analyzed.

To achieve the above object, a third aspect of the present application provides an instruction transmitting apparatus, including:

the first execution unit is used for writing an instruction into the buffer for buffering when receiving the instruction to be sent, resetting the counter and starting self-counting;

the second execution unit is used for executing the first operation and the second operation in a competing mode:

and the third execution unit is used for sending the frame of data.

To achieve the above object, a fourth aspect of the present application provides an instruction transmitting apparatus, including:

the buffer module comprises a buffer, wherein the buffer is used for buffering an instruction to be sent;

the detection module is used for resetting a counter and starting self-counting when the instruction to be sent by the buffer is written in, resetting the counter when the instruction buffered by the buffer is read, and generating a sending signal when the counter count reaches a preset period threshold or when the number of the instructions buffered in the buffer reaches a preset number threshold;

and the sending module is used for reading the instruction cached by the buffer according to the sending signal and packaging the instruction into one frame of data for sending.

A fifth aspect of the present application provides an instruction receiving apparatus, including:

the data receiving module is used for receiving a frame of data sent by an Ethernet protocol; the frame data comprises a target MAC address field, a source MAC address field, a length field, an instruction field and a stop instruction field;

the analysis module is used for analyzing the target MAC address field, the source MAC address field and the length field; analyzing the instruction field and the stop instruction field, judging that the analyzed stop instruction is obtained, stopping analyzing, caching the instruction, and waiting for the next frame of data; if the instruction is analyzed, caching the instruction, and continuing to analyze the instruction field and the stop instruction field until the stop instruction is analyzed.

A sixth aspect of the present application provides a computing device comprising: a communication interface, and at least one processor; wherein the at least one processor is configured to execute program instructions that, when executed by the at least one processor, cause the computing device to perform any of the instruction sending methods of the first aspect described above, or that, when executed by the at least one processor, cause the computing device to implement the method of the second aspect described above.

A seventh aspect of the present application provides a computer-readable storage medium having stored thereon program instructions that, when executed by a computer, cause the computer to perform the method of any of the first aspects described above, or that, when executed by the computer, cause the computer to implement the method of the second aspect described above.

An eighth aspect of the present application provides a computer program product comprising program instructions which, when executed by a computer, cause the computer to perform the method of any of the first aspects described above, or which, when executed by the computer, cause the computer to perform the method of the second aspect described above.

Drawings

FIG. 1 is a flow chart of a first embodiment of an instruction issue method of the present application;

FIG. 2 is a schematic diagram of a data frame structure when the number of FIFO buffered data reaches a threshold value;

FIG. 3 is a schematic diagram of a data frame structure when the detection counter exceeds a threshold period;

FIG. 4 is a schematic diagram of a specific example of an instruction sending method of the present application;

FIG. 5 is a schematic diagram of a configuration of the instruction issue apparatus of the present application;

FIG. 6 is another schematic structural view of the instruction issue apparatus of the present application;

FIG. 7 is a flow chart of a method of instruction reception of the present application;

FIG. 8 is a schematic diagram of the instruction receiving apparatus of the present application;

fig. 9 is a schematic structural diagram of a computing device provided in an embodiment of the present application.

It should be understood that in the foregoing structural schematic diagrams, the sizes and forms of the respective block diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of the present invention. The relative positions and inclusion relationships between the blocks presented by the structural diagrams are merely illustrative of structural relationships between the blocks, and are not limiting of the physical connection of embodiments of the present invention.

Detailed Description

The technical scheme provided by the application is further described below by referring to the accompanying drawings and examples. It should be understood that the system structures and service scenarios provided in the embodiments of the present application are mainly for illustrating possible implementations of the technical solutions of the present application, and should not be construed as the only limitation of the technical solutions of the present application. As one of ordinary skill in the art can know, with the evolution of the system structure and the appearance of new service scenarios, the technical scheme provided in the application is applicable to similar technical problems.

It should be understood that the instruction sending and receiving schemes provided in the embodiments of the present application include an instruction sending method and apparatus, and an instruction receiving method and apparatus. Because the principles of solving the problems in these technical solutions are the same or similar, in the following description of the specific embodiments, some repetition is not described in detail, but it should be considered that these specific embodiments have mutual references and can be combined with each other.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. If there is a discrepancy, the meaning described in the present specification or the meaning obtained from the content described in the present specification is used. In addition, the terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application. For the purpose of accurately describing the technical content of the present application, and for the purpose of accurately understanding the present invention, the terms used in the present specification are given the following explanation or definition before the explanation of the specific embodiments:

1) ATE (AutomaticTestEquipment) in the semiconductor industry, an automatic Integrated Circuit (IC) tester is used to test the integrity of integrated circuit functions, and is the final process of integrated circuit manufacturing to ensure the quality of integrated circuit manufacturing.

2) PCIE (peripheralcomponentinterconnectexpress) is a high-speed serial computer expansion bus standard. PCIE belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, PCIE buses use an end-to-end connection mode, and only one device can be connected to each of two ends of one PCIE link, and the two devices are mutually a data sending end and a data receiving end. The PCIE card is a network card with a PCIE interface, and is used as an expansion port in a motherboard-level connection. Specifically, the PCIE-based expansion card can be inserted into PCIE slots in a device motherboard such as a host, a server, and a network switch.

3) FPGA (Field-programmable gate array), which is a product of further development on the basis of programmable devices such as PAL, GAL, CPLD.

4) Aurora is an extensible lightweight link layer protocol for moving data between point-to-point serial links.

5) Ethernet (Ethernet) belongs to a network underlying protocol, and generally operates at the physical layer and data link layer of the OSI model.

6) FIFO (FirstInputFirstOutput) first-in first-out queue, which is a traditional sequential execution method, is that an instruction entered first completes and retires before a second instruction is executed.

In order to solve the technical problem and realize the self-adaptive receiving of the PC instruction to send through the Ethernet protocol, the sending efficiency is improved, an instruction sending mechanism is designed, and the embodiment of the application provides an instruction sending method.

An embodiment of the instruction sending method of the present application will be described below with reference to the flowchart shown in fig. 1. As shown in fig. 1, the method includes:

s110: when an instruction to be sent is received, writing the instruction into a buffer for buffering, resetting a counter and starting self-counting;

s120: performing a first operation and a second operation using a contention mode:

s130: and transmitting the frame of data.

The method can be applied to PCIE boards provided with the FPGA, and the buffer can be the FIFO of the FPGA; the frame of data is a frame of Ethernet protocol data.

According to the method and the device, the self-adaptive mechanism is adopted, so that a plurality of instructions can be sent in one frame of Ethernet protocol data, the quantity and the frequency of the PC sending instructions are not constrained, the one frame of Ethernet protocol data can be quickly sent, the quantity and the frequency of the PC sending instructions are not constrained, and the communication efficiency is improved.

The embodiment of the application can be applied to any scene of transmitting frame data by using an Ethernet protocol, and is suitable for transmitting any instruction in a test system.

The data transmitting end receives an instruction from the data transmitting end, and the data transmitting end can refer to a PC in an ATE test system. And the PC sends an instruction to the FIFO to communicate in a PCIE mode, namely, the instruction sent by the PC is transmitted to the FPGA end through PCIE driving and PCIEIP, and data is stored in the FIFO. The instructions referred to herein may include all instructions that are involved in testing the system.

In an embodiment, the counter calculates a clock of a transmitting end of the Ethernet user side, namely, the PCIE board card core chip is an FPGA, the board is provided with a clock chip, after the FPGA is introduced, the clock is multiplied by frequency to generate 200MHz, and the clock always exists. When the timer is started, a count may be made every 5 ns (5 ns is a period of 200 MHz). The preset threshold period can be set to 7 periods, namely 7 periods of 5 nanoseconds, or other values, and is determined manually according to the data processing conditions of the FPGA at the transmitting end and the receiving end of the actual instruction.

In one embodiment, the writing the instruction to the buffer for buffering, resetting the counter and starting the self-count includes:

when the instruction is written into a buffer so that the buffer state of the buffer is changed from empty to non-empty, an empty port of the buffer is changed from high level to low level; when the buffer state of the buffer is empty, the empty port is at a high level, and the counter is kept in a reset state;

detecting that the empty port is changed from high level to low level, releasing reset of a counter and starting self-counting;

and resetting the counter when the instruction is written into the buffer so that the buffered instruction in the buffer changes.

when the instruction is written into the buffer, enabling a write-in enabling signal of the buffer to be valid or enabling a write-in counting signal to be changed;

and resetting a counter and starting self-counting when the write-in enabling signal of the buffer is valid or the write-in counting signal is changed.

In one embodiment, the reading the buffered instruction of the buffer and the and resetting the counter includes:

when the instruction cached by the buffer is read, the reading counting signal of the buffer is changed;

and resetting the counter when detecting the change of the reading counting signal of the buffer.

when the instruction cached by the buffer is read, the buffer state of the buffer is made to be empty, so that an empty port of the buffer is made to be high level;

and resetting a counter when the empty port is detected to be at a high level.

Wherein, the empty is the output signal of FIFO, when there is no data to buffer, the empty signal is 1; when there is cached data, empty goes to 0.

The read count signal rd_data_count and the write count signal wr_data_count are both counted for the buffered instruction and FIFO self-contained. When the read count signal rd_data_count and the write count signal wr_data_count have no cached data in the FIFO (i.e., the FIFO is empty), the rd_data_count and the wr_data_count are both 0, 1 is added when an instruction is written into the FIFO, 1 is subtracted when an instruction is read from the FIFO, that is, the read count signal rd_data_count and the write count signal wr_data_count are both changed when an instruction is written into or read from the FIFO, and the signal change indicates that the instruction is changed. The counter is cleared when BIT0, which may be a write count signal wr_data_count and/or a read count signal rd_data_count, changes. BIT0 changes from 0 to 1 or from 1 to 0, indicating that there is a change in a cache instruction, either stored or read, and is to be determined.

When the write-in device is used, the wr_data_count is synchronized by adopting a clock of a write-in terminal, the write-in clock is 250MHz, and the PCIE instruction is stored in the FIFO at 250 MHz. The rd_data_count adopts clock synchronization of a reading end, the reading clock is 200MHz, and the back end sends and detects judgment, which are all under 200 MHz. Therefore, if wr_data_count is used as the detection signal, it is necessary to synchronize the write clock to 200 MHz.

Or when the change of the enabling write signal and the enabling read signal of the FIFO end is detected, the instruction which is cached is indicated to be changed, and the counter is cleared.

The write enable signal wren and the read enable signal rden at the FIFO end may also be used together to determine if the instruction is changing, where the write enable signal wren and the read enable signal rden are ored. Because the buffered data changes include increases and decreases, wren increases the buffer and rden decreases the buffer, these two signals are used together if the buffered data changes are to be fully determined. Furthermore, the write enable signal wren is 250MHz from the write side clock, the read enable signal rden is 200MHz from the read side clock, and the write enable signal wren needs to be synchronized to the 200MHz clock.

In one embodiment, for S120, it may be the following specific procedure:

if the interval period between instructions is small and the number of instructions is large, the counter is continuously cleared. When the number of instructions in the cache FIFO exceeds a threshold number (the threshold number may be 16, and the rd_data_count > =16 is directly determined), data is read from the FIFO, the read enable signal changes, and reading the data causes the rd_data_count to change, thereby resetting the counter. When the instruction interval period is long or the number of instructions is small, the value of the counter reaches the threshold period and releases a sending signal (the signal keeps 1 after exceeding the threshold period, and the reading data is reset and becomes 0), the reading data is read from the FIFO, and the reading data can cause the rd_data_count to change, so that the counter is cleared and the sending signal is reset. The detection is always performed, and the change of the rd_data_count clears the counter (including the increase of the rd_data_count during writing and the decrease of the rd_data_count during reading).

After the sending is finished, if instructions are still in the FIFO, when the counter counts the instructions exceeding the threshold period, all instructions of the current FIFO are sent, and when new instructions are still stored in the sending process, the new instructions are not sent and only the instructions which are cached in the FIFO at the moment exceeding the threshold period are sent; if the counter counts no more than a threshold period and the buffered instructions exceed the threshold number, a fixed threshold number of instructions are issued.

When the threshold number is up, a threshold period signal is sent at the same time, and at the moment, the buffered instruction in the FIFO is read, the counter is cleared, the signals sent in the threshold period are reset, and the problem of repeated sending is avoided. Both of these cases, either of which results in the transmission of data, are reset to each other.

In an embodiment, the total length of one frame of data is a preset fixed length, and one frame of data further comprises a target MAC address field, a source MAC address field, a length field, an instruction field and a stop instruction field;

wherein the instruction field fills the read instruction cached by the cache;

the stop instruction field is filled with a stop instruction of a variable length to make the total length of the one frame of data reach the preset fixed length.

Wherein, the IEEE802.3 format is adopted to define the Ethernet protocol data frame format.

Specifically, when the number of FIFO buffer commands reaches a threshold, a frame of Ethernet protocol data is composed of a 6-byte destination address, a 6-byte source address, a 2-byte length, a fixed threshold number of command data, and a 4-byte stop command, as shown in fig. 2; when the counter reaches the threshold period, a frame of Ethernet protocol data is composed of 6 bytes of destination address, 6 bytes of source address, 2 bytes of length, all instruction data in FIFO, and adaptive fill stop instruction, as shown in fig. 3.

Specifically, fig. 4 is a schematic diagram of a specific example of instruction sending in the present application, referring to fig. 5, where the threshold number is set to 15, and when the number of instructions in the buffer FIFO exceeds 15, a frame of Ethernet protocol data including 15 write instructions is sent. When the number of instructions in the buffer FIFO does not exceed 15, but the counter count exceeds a period threshold, for example, only one instruction in the buffer FIFO, a frame of Ethernet protocol data including 1 write instruction is sent. When the time interval is long, it is judged that the counter count exceeds the period threshold again, and then 3 instructions are in the buffer FIFO, and then a frame of Ethernet protocol data comprising 3 writing instructions is sent.

As shown in fig. 4, an embodiment of the present application provides an instruction transmitting apparatus that may be used to implement the instruction transmitting method in the above embodiment, as shown in fig. 5, the instruction transmitting apparatus 500 includes: the first execution unit 510 is configured to write an instruction to the buffer for buffering, reset the counter, and start self-counting when receiving the instruction to be sent; the second execution unit 520 is configured to execute the first operation and the second operation in a contention manner: the first operation includes: when the counter reaches a preset period threshold, reading the instruction cached by the buffer, packaging the instruction into a frame of data, and resetting the counter; the second operation includes: when the number of the instructions cached in the buffer reaches a preset number threshold, reading the instructions cached in the FIFO, packaging the instructions in one frame of data, and resetting a counter; and a third execution unit 530 for transmitting the one frame of data.

As shown in fig. 6, an embodiment of the present application provides an instruction sending apparatus, which may be used to implement the instruction sending method in the foregoing embodiment, and as shown in fig. 6, the instruction sending apparatus 600 has a buffering module 610, a detecting module 620, and a sending module 630. The buffer module 610 includes a buffer, where the buffer is used to buffer the instruction to be sent; the detection module 620 is configured to reset a counter and start self-counting when an instruction to be sent from the buffer is written, reset the counter when an instruction buffered in the buffer is read, and generate a sending signal when the counter count reaches a preset period threshold or when the number of instructions buffered in the buffer reaches a preset number threshold; and the sending module 630 is configured to read the instruction buffered by the buffer according to the sending signal, and encapsulate the instruction into a frame of data for sending.

Reference may be made specifically to the detailed description of the method embodiments, which are not described here in detail.

The instruction sending method and device provided by the application can obtain the following beneficial effects:

1. the PC executes the same PCIE software code, the instructions are sent at different moments, the intervals between the instructions received by the FPGA are different, the minimum intervals are 10 periods, and the maximum intervals are 80 periods. Under the Ethernet protocol, when single frame data only sends one instruction, the phenomena of untimely sending, FIFO overflow and data overflow can occur when the instruction interval is short and the number of the instructions is large (more than 10 periods), and the data packet loss is caused by the Ethernet sending. After the instruction sending mechanism is adopted, the quantity and the frequency of PCIE instructions sent by the PC are not restricted no matter how many interval periods are between the instructions, and the PCIE instructions can be efficiently forwarded through an Ethernet protocol.

2. The test software instruction of the ATE test system is sent in a PCIE mode, the original sending mode is not changed, and the Ethernet protocol is made in the FPGA, so that the test software of the ATE test system is not changed.

For the above-mentioned instruction sending method, there is also an instruction receiving method at the data receiving end, as shown in fig. 7, the present application provides an instruction receiving method, which includes:

analyzing the instruction field and the stop instruction field, judging whether the analyzed instruction is a stop instruction, and stopping analyzing if the analyzed instruction is the stop instruction, and waiting for the next frame of data; and if the analyzed instruction is not the stop instruction, caching the instruction, and continuing to analyze the instruction field and the stop instruction field until the stop instruction is analyzed.

As shown in fig. 8, the embodiment of the present application provides an instruction receiving apparatus, which may be used to implement the instruction receiving method in the above embodiment, and as shown in fig. 8, the instruction receiving apparatus 800 has a data receiving module 810 and a parsing module 820.

Wherein, the data receiving module 810 is configured to receive a frame of data sent by an Ethernet protocol; the frame data comprises a target MAC address field, a source MAC address field, a length field, an instruction field and a stop instruction field;

the parsing module 820 is configured to parse the destination MAC address field, the source MAC address field, and the length field; analyzing the instruction field and the stop instruction field, judging whether the analyzed instruction is a stop instruction, and stopping analyzing if the analyzed instruction is the stop instruction, and waiting for the next frame of data; and if the analyzed instruction is not the stop instruction, caching the instruction, and continuing to analyze the instruction field and the stop instruction field until the stop instruction is analyzed.

Fig. 9 is a schematic diagram of a computing device 900 provided by an embodiment of the present application. The computing device may act as instruction transmitting means to perform the various alternative embodiments of the instruction transmitting method described above, or the computing device may act as instruction receiving means to perform the various alternative embodiments of the instruction receiving method described above. The computing device may be a terminal or a chip or chip system within the terminal. As shown in fig. 9, the computing device 900 includes: processor 910, memory 920, and communication interface 930.

It should be appreciated that the communication interface 930 in the computing device 900 shown in fig. 9 may be used to communicate with other devices, and in particular may include one or more transceiver circuits or interface circuits.

Wherein the processor 910 may be coupled to a memory 920. The memory 920 may be used to store the program codes and data. Accordingly, the memory 920 may be a storage unit internal to the processor 910, an external storage unit independent of the processor 910, or a component including a storage unit internal to the processor 910 and an external storage unit independent of the processor 910.

Optionally, computing device 900 may also include a bus. The memory 920 and the communication interface 930 may be connected to the processor 910 through a bus. The bus may be a peripheral component interconnect (PeripheralComponent Interconnect, PCI) bus, or an extended industry standard architecture (ExtendedIndustryStandardArchitecture, EISA) bus, among others. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, an unbiased line is shown in FIG. 9, but does not represent only one bus or one type of bus.

It should be appreciated that in embodiments of the present application, the processor 910 may employ a central processing unit (central processingunit, CPU). The processor may also be other general purpose processors, digital signal processors (digital signalprocessor, DSP), application Specific Integrated Circuits (ASIC), off-the-shelf programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 910 may employ one or more integrated circuits for executing associated programs to perform the techniques provided in the embodiments of the present application.

The memory 920 may include read only memory and random access memory and provide instructions and data to the processor 910. A portion of the processor 910 may also include nonvolatile random access memory. For example, the processor 910 may also store information of the device type.

When the computing device 900 is running, the processor 910 executes computer-executable instructions in the memory 920 to perform any of the operational steps of the methods described above, as well as any of the alternative embodiments.

It should be understood that the computing device 900 according to the embodiments of the present application may correspond to a respective subject performing the methods according to the embodiments of the present application, and that the foregoing and other operations and/or functions of the respective modules in the computing device 900 are respectively for implementing the respective flows of the methods of the embodiments, and are not described herein for brevity.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RandomAccessMemory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Embodiments of the present application also provide a computer-readable storage medium having stored thereon a computer program for performing the above-described method when executed by a processor, the method comprising at least one of the aspects described in the above-described embodiments.

Any combination of one or more computer readable media may be employed as the computer storage media of the embodiments herein. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

In addition, the terms "first, second, third, etc." or module a, module B, module C, etc. in the description and the claims are used solely for distinguishing between similar objects and not necessarily for a specific ordering of objects, it being understood that a specific order or sequence may be interchanged if allowed to enable the embodiments of the application described herein to be practiced otherwise than as specifically illustrated and described herein.

In the above description, reference numerals indicating steps such as S110, S120, … …, etc. do not necessarily indicate that the steps are performed in this order, and the order of the steps may be interchanged or performed simultaneously as the case may be.

The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the expression "a device comprising means a and B" should not be limited to a device consisting of only components a and B.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments as would be apparent to one of ordinary skill in the art from this disclosure.

Note that the above is only a preferred embodiment of the present application and the technical principle applied. Those skilled in the art will appreciate that the present application is not limited to the particular embodiments described herein, but is capable of numerous obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the present application. Thus, while the present application has been described in terms of the foregoing embodiments, the present application is not limited to the foregoing embodiments, but may include many other equivalent embodiments without departing from the spirit of the present application, all of which fall within the scope of the present application.

Claims

1. A method of transmitting an instruction, comprising:

performing a first operation and a second operation using a contention mode:

and transmitting the frame of data.

2. The method of claim 1, wherein writing the instruction to a buffer for buffering, resetting a counter, and starting a self-count comprises:

3. The method of claim 1, wherein writing the instruction to a buffer for buffering, resetting a counter, and starting a self-count comprises:

when the instruction is written into the buffer, the writing count signal of the buffer is changed;

and resetting a counter and starting self-counting when detecting the change of the write count signal of the buffer.

4. The method of claim 1, wherein the reading the buffered instruction from the buffer and the and resetting the counter comprises:

5. The method of claim 1, wherein the reading the buffered instruction from the buffer and the and resetting the counter comprises:

and resetting a counter when the empty port is detected to be at a high level.

6. The method of claim 1, wherein the total length of the frame of data is a preset fixed length, and the frame of data includes a destination MAC address field, a source MAC address field, a length field, an instruction field, and a stop instruction field;

wherein the instruction field fills the read instruction cached by the cache;

7. The method according to claim 1 to 6, wherein,

the method is applied to PCIE boards provided with the FPGA, and the buffer is a FIFO of the FPGA;

the frame of data is a frame of Ethernet protocol data.

8. An instruction transmitting apparatus, comprising:

the first execution unit is used for writing the instruction into the buffer to be buffered when receiving an instruction to be sent, resetting the counter and starting self-counting;

the second operation includes: when the number of the instructions cached in the buffer reaches a preset number threshold, reading the instructions cached in the FIFO, packaging the instructions in one frame of data, and resetting a counter;

and the third execution unit is used for sending the frame of data.

9. An instruction transmitting apparatus, comprising:

10. A computing device, comprising:

processor and method for controlling the same

A memory having stored thereon program instructions that, when executed by the processor, cause the processor to perform the instruction transmission method of any of claims 1 to 7.