CN116073832A

CN116073832A - Data processing method, device, electronic equipment and storage medium

Info

Publication number: CN116073832A
Application number: CN202310202399.0A
Authority: CN
Inventors: 孙桂喜; 樊崇斌; 黄宁
Original assignee: Shanghai Lichi Semiconductor Co ltd
Current assignee: Shanghai Lichi Semiconductor Co ltd
Priority date: 2023-03-03
Filing date: 2023-03-03
Publication date: 2023-05-05

Abstract

The disclosure provides a data processing method, a device, an electronic device and a storage medium, wherein the method comprises the following steps: confirming a simulation channel identifier based on a trigger event and a pre-configured trigger event channel selection comparison table, wherein the simulation channel identifier comprises at least one internal simulation channel identifier; receiving at least one path of analog signals based on the analog channels corresponding to the analog channel identifiers; performing analog-to-digital conversion on the at least one path of analog signals to obtain an analog-to-digital conversion result; the analog-to-digital conversion result comprises a signal path identifier corresponding to the at least one path of analog signals and a result of converting the at least one path of analog signals into digital signals; the signal path identifier includes the at least one internal analog channel identifier.

Description

Data processing method, device, electronic equipment and storage medium

Technical Field

The disclosure relates to the technical field of chips, and in particular relates to a data processing method, a data processing device, electronic equipment and a storage medium.

Background

When the analog-to-digital converter in the chip performs analog-to-digital conversion, the analog-to-digital conversion can be performed only after the channel for receiving the analog signal is manually switched based on the triggering event, and for some applications requiring real-time data acquisition and timely data processing, the analog channel in the chip cannot realize continuous event triggering analog-to-digital conversion sampling, so that the requirement of the application on data processing cannot be met.

Disclosure of Invention

The present disclosure provides a data processing method, apparatus, electronic device, and storage medium, so as to at least solve the above technical problems in the prior art.

According to a first aspect of the present disclosure, there is provided a data processing method comprising:

confirming a simulation channel identifier based on a trigger event and a pre-configured trigger event channel selection comparison table, wherein the simulation channel identifier comprises at least one internal simulation channel identifier;

receiving at least one path of analog signals based on the analog channels corresponding to the analog channel identifiers;

performing analog-to-digital conversion on the at least one path of analog signals to obtain an analog-to-digital conversion result;

the analog-to-digital conversion result comprises a signal path identifier corresponding to the at least one path of analog signals and a result of converting the at least one path of analog signals into digital signals; the signal path identifier includes the at least one internal analog channel identifier.

According to a second aspect of the present disclosure, there is provided a data processing apparatus comprising:

a confirmation unit, configured to confirm a simulation channel identifier based on a trigger event and a pre-configured trigger event channel selection comparison table, where the simulation channel identifier includes at least one internal simulation channel identifier;

The receiving unit is used for receiving at least one path of analog signals based on the analog channels corresponding to the analog channel identifiers;

the analog-to-digital conversion unit is used for carrying out analog-to-digital conversion on the at least one path of analog signals to obtain an analog-to-digital conversion result;

According to a third aspect of the present disclosure, there is provided an electronic device comprising:

at least one processor; and a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.

According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method described in the present disclosure.

According to the data processing method, a simulation channel identifier is confirmed through a comparison table selected based on a trigger event and a pre-configured trigger event channel, wherein the simulation channel identifier comprises at least one internal simulation channel identifier; receiving at least one path of analog signals based on the analog channels corresponding to the analog channel identifiers; and carrying out analog-to-digital conversion on the at least one path of analog signals to obtain an analog-to-digital conversion result. The analog channel identification corresponding to the trigger event can be confirmed based on a pre-configured trigger event channel selection comparison table, so that the corresponding analog signal is automatically received based on the analog channel identification, the analog channel automatic switching based on the trigger event is realized, and the analog-to-digital conversion sampling triggered by the continuous event is realized.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

FIG. 1 illustrates an alternative flow diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 2 shows a first alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 3 illustrates another alternative flow diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 4 shows a second alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 5 shows a third alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 6 shows a fourth alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 7 shows a fifth alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 8 shows a sixth alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 9 shows a seventh alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 10 shows an eighth alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure;

FIG. 11 is a schematic diagram showing an alternative configuration of a data processing apparatus provided by an embodiment of the present disclosure;

fig. 12 is a schematic diagram showing a composition structure of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

The analog-to-digital converter (ADC 1) inside the chip generally needs software to configure the conduction of the external analog channel and/or the internal analog channel, so that the analog-to-digital converter can receive the corresponding analog signal through the conducted analog channel to perform analog signal and digital signal conversion (ADC sampling), and when the analog channel for receiving the analog signal is changed, the software needs to reconfigure the conduction of the corresponding external analog channel and/or the internal analog channel, and the software needs time to reconfigure, so that continuous event triggering ADC sampling cannot be implemented.

In view of the drawbacks of the related art, the present disclosure provides a data processing method, which can solve some or all of the above technical problems.

Fig. 1 shows an alternative flowchart of a data processing method according to an embodiment of the present disclosure, and will be described according to the steps.

Step S201, based on the trigger event and the pre-configured trigger event channel selection comparison table, confirming the analog channel identification.

In some embodiments, the pre-configured trigger event channel selection lookup table includes a correspondence between trigger events, at least one analog multiplexer, and at least one internal analog channel identification.

In some embodiments, the data processing apparatus (hereinafter referred to as an apparatus) confirms, based on the generated trigger event, an analog channel identifier corresponding to the trigger event, where the analog channel identifier may include at least one internal analog channel identifier. Optionally, the device may further confirm an analog multiplexer corresponding to the trigger event based on the trigger event.

The analog multiplexer may include at least one first analog multiplexer, where the at least one first analog multiplexer corresponds to the analog-to-digital converters in the chip one by one, and is configured to turn on or off an internal analog channel of each analog-to-digital converter that receives an analog signal. The analog multiplexer may further include at least one second analog multiplexer; the second analog multiplexers are in one-to-one correspondence with at least one first analog multiplexer, or the plurality of first analog multiplexers are in one second analog multiplexer; the second analog multiplexer is used for switching on or switching off an external analog channel. Each second analog multiplexer corresponds to a plurality of external analog channels corresponding to one or more external chip modules.

That is, each analog-to-digital converter in the chip corresponds to one first analog multiplexer, each analog-to-digital converter corresponds to one second analog multiplexer, or a plurality of first analog-to-digital converters corresponds to one second analog multiplexer. When each first analog-to-digital converter corresponds to one second analog multiplexer, the second analog multiplexer is used for switching on or switching off an external analog channel corresponding to one or more chip external modules; when the first analog-to-digital converters correspond to a second analog multiplexer, the second analog multiplexer is used for switching on or switching off a plurality of external analog channels corresponding to the chip external modules.

In some alternative embodiments, each analog-to-digital converter in the chip corresponds to an internal analog channel set, each internal analog channel set includes a plurality of internal analog channels, the plurality of internal analog channels corresponding to different analog-to-digital converters can be coincident or not, if so, the coincident internal analog channels have two internal analog channel identifiers, and respectively correspond to different analog-to-digital converters; the internal analog channel identifier is used for representing a channel for receiving the analog signal in a plurality of internal analog channels in the chip, the internal analog channel identifier comprises a character string composed of binary characters, and each internal analog channel is concentrated in the chip, and the character string corresponding to each channel for receiving the analog signal is different; the internal analog channel identifier can be used for distinguishing different internal analog channels in one internal analog channel set and can also be used for distinguishing all internal analog channels in a chip. The character string may be composed of any number of binary characters, such as 6 binary character strings in the present disclosure, and optionally, other numbers of binary character strings, which is not specifically limited in the present disclosure.

In some alternative embodiments, the triggering event may be a pulse or other form generated by a level comparison, and the disclosure is not particularly limited.

Step S202, receiving at least one analog signal based on the analog channel corresponding to the analog channel identifier.

In some embodiments, the device sends a first conduction signal to at least one analog multiplexer based on the trigger event, so that the at least one analog multiplexer conducts at least one internal analog channel in the internal analog channel set corresponding to the analog-to-digital converter based on the first conduction signal; an analog signal is received based on the at least one internal analog channel.

In some embodiments, the first on signal may include an internal analog channel identifier and an external analog channel identifier to be turned on, and since only the internal analog channel is involved in this embodiment, the first on signal may include only the internal analog channel identifier, and a portion of the external analog channel identifier is set to be null or other default character strings or inactive, and if multiple analog-to-digital converters are required to receive the analog signal, the apparatus may send the first on signal to a corresponding multiple analog multiplexers respectively; alternatively, if an analog-to-digital converter is required to receive the analog signal, the apparatus may send the first on signal to the corresponding analog multiplexer.

After the analog multiplexers or the analog multiplexer receives the first conduction signal, the corresponding internal analog channels are controlled to be conducted, so that the analog signals are received by the analog-to-digital converters based on the conducted internal analog channels.

Step S203, performing analog-to-digital conversion on the at least one analog signal to obtain an analog-to-digital conversion result.

In some embodiments, the analog-to-digital conversion result includes a signal path identifier corresponding to the at least one analog signal and a result of converting the at least one analog signal into a digital signal; the signal path identifier includes the at least one internal analog channel identifier.

In particular, if each analog multiplexer includes a first analog multiplexer and a second analog multiplexer, characterizing each analog multiplexer as controlling a channel of an analog-to-digital converter for receiving analog signals; if each analog multiplexer includes at least one analog multiplexer and a second analog multiplexer, the analog multiplexer controls channels of the plurality of analog-to-digital converters for receiving the analog signals.

Correspondingly, if each analog multiplexer includes a first analog multiplexer and a second analog multiplexer, the conduction signal sent to the first analog multiplexer included in the analog multiplexer includes only the internal analog channel identifier to be conducted, and the conduction signal sent to the second analog multiplexer included in the analog multiplexer includes only the external analog channel identifier to be conducted. If each analog multiplexer includes at least one first analog multiplexer and one second analog multiplexer, the on signal sent to the first analog multiplexer and the second analog multiplexer included in the analog multiplexer includes both an internal analog channel identifier and an external analog channel identifier to be turned on.

As shown in fig. 2, the chip includes 1 analog-to-digital converter (i.e. ADC 1), the internal analog channel set corresponding to the analog-to-digital converter includes a plurality of internal analog channels (e.g. 48 internal analog channels), and 1 analog multiplexer, and since fig. 2 does not involve the external analog channel corresponding to the external chip module, the analog multiplexer may be formed by 1 first analog multiplexer and 1 second analog multiplexer, or may be formed by 1 first analog multiplexer. Correspondingly, when the analog multiplexer is composed of 1 first analog multiplexer, the on signal sent to the analog multiplexer may include only the internal channel identifier for the first analog multiplexer; when the analog multiplexer is composed of 1 first analog multiplexer and 1 second analog multiplexer, the on signal sent to the analog multiplexer includes an internal analog channel identification and an external analog channel identification, except that the external analog channel identification is null or other symbol.

The following description will be made with the analog multiplexer consisting of only 1 first analog multiplexer:

in some embodiments, in response to generating a trigger event, the apparatus validates the first analog multiplexer and the internal analog channel identification (e.g., CH 5) based on the trigger event and a pre-configured trigger event channel selection look-up table; and sending a first conducting signal to the first analog multiplexer to enable the first analog multiplexer to conduct the internal analog channels, which are collectively marked as CH5, of the internal analog channels, receiving the analog signals based on the CH5, performing analog-to-digital conversion on the analog signals by the ADC1, and outputting analog-to-digital conversion results, wherein the results comprise a signal path mark (AMSEL [0:8 ]) and a result (SAR [0:11 ]) of converting the analog signals into digital signals. Wherein the first on signal includes an internal analog channel identifier and an external analog channel identifier, in this embodiment, the external analog channel identifier is null or other agreed symbol such as XXX, because the external analog channel is not involved.

In some embodiments, the apparatus selects a look-up table based on the trigger event and a pre-configured trigger event channel, a validated first analog multiplexer for validating a recipient of a first turn-on signal; the internal analog channel identifier is used for characterizing the internal analog channel that the first analog multiplexer needs to conduct, that is, the signal path identifier in this embodiment. The signal path identifier may be a string composed of 8-bit binary characters, in which the 1 st to 6 th bits (i.e. 0-5) represent identifiers of internal analog channels, the 7 th to 9 th bits (i.e. 6-8) represent identifiers of external analog channels, and for the case that only internal analog channels are involved in this embodiment, the 7 th to 9 th bits may be any number or letter, such as XXX, because the second analog multiplexer is not involved in the confirmation result based on the trigger event and the pre-configured trigger event channel selection comparison table, and the turn-on signal is not sent to the second analog multiplexer. SAR [0:11] characterizes the result of converting an analog signal into a digital signal, including a 12-bit string.

The following description will be made with an analog multiplexer composed of 1 first analog multiplexer and 1 second analog multiplexer:

In some embodiments, in response to generating a trigger event, the apparatus validates the analog multiplexer and the internal analog channel identification (e.g., CH 5) based on the trigger event and a pre-configured trigger event channel selection look-up table; sending a first conducting signal to the analog multiplexer, enabling the analog multiplexer to conduct an internal analog channel, which is collectively marked as CH5, of the internal analog channels, receiving the analog signal based on the CH5, performing analog-to-digital conversion on the analog signal by an ADC1, and outputting an analog-to-digital conversion result, wherein the result comprises a signal path mark (AMSEL [0:8 ]) and a result (SAR [0:11 ]) of converting the analog signal into a digital signal. Wherein the first on signal includes an internal analog channel identifier and an external analog channel identifier, in this embodiment, the external analog channel identifier is null or other agreed symbol such as XXX, because the external analog channel is not involved.

In some embodiments, the apparatus selects a look-up table based on the trigger event and a pre-configured trigger event channel, an acknowledge analog multiplexer for acknowledging the recipient of the first turn-on signal; the internal analog channel identifier is used for characterizing the internal analog channel that the first analog multiplexer needs to conduct, that is, the signal path identifier in this embodiment. Since no external analog channels are involved in this embodiment, only the first on signal needs to be sent to the first analog multiplexer.

Similarly, for the case that at least two analog-to-digital converters (e.g., analog-to-digital converter 1 and analog-to-digital converter 2) are included in the chip, in response to the generation of a trigger event, the apparatus determines at least two analog multiplexers (e.g., analog multiplexer 1 and analog multiplexer 2) and internal analog channel identifications (e.g., CH5 corresponding to analog-to-digital converter 1 and CH4 corresponding to analog-to-digital converter 2) based on the trigger event and a pre-configured trigger event channel selection lookup table; respectively sending a conducting signal to the at least two analog multiplexers, so that the analog multiplexer 1 conducts the internal analog channels which correspond to the analog-to-digital converter 1 and are collectively marked as CH5, and the analog multiplexer 2 conducts the internal analog channels which correspond to the analog-to-digital converter 2 and are collectively marked as CH 4; so that analog-to-digital converter 1 receives analog signals based on the corresponding CH5 and analog-to-digital converter 2 receives analog signals based on the corresponding CH 4. Analog-to-digital converter 1 and analog-to-digital converter 2 output analog-to-digital conversion results, respectively, each of which includes a signal path identification (AMSEL [0:8 ]) and a result of converting an analog signal into a digital signal (SAR [0:11 ]). Wherein, the on signal can only include the internal analog channel identification.

Thus, according to the data processing method provided by the embodiment of the disclosure, the comparison table can be selected based on the pre-configured trigger event channel, and the analog channel identification corresponding to the trigger event is confirmed, so that the corresponding analog signal is automatically received based on the analog channel identification, the automatic switching of the analog channel based on the trigger event is realized, and the analog-to-digital conversion sampling triggered by the continuous event is realized.

Fig. 3 shows another alternative flow diagram of a data processing method according to an embodiment of the disclosure, which will be described according to the steps.

Step S401, based on the trigger event and the pre-configured trigger event channel selection comparison table, confirming the analog channel identification.

In some embodiments, the data processing apparatus confirms a simulated channel identification corresponding to a generated trigger event based on the trigger event, wherein the simulated channel identification may include at least one internal simulated channel identification and at least one external simulated channel identification.

In a specific implementation, if the trigger event is received by an analog-to-digital converter inside the chip, the analog channel identifier may include an internal analog channel identifier and an external analog channel identifier, or a plurality of internal analog channel identifiers and a plurality of external analog channel identifiers (the number of internal analog channel identifiers is the same as the number of external analog channel identifiers).

Step S402, based on the trigger event and the pre-configured trigger event channel selection comparison table, the analog multiplexer is confirmed.

In some embodiments, each analog-to-digital converter in the chip corresponds to an internal analog channel set, each internal analog channel set includes a plurality of internal analog channels, and the plurality of internal analog channels corresponding to different analog-to-digital converters may be coincident or not coincident; the internal analog channel identifier is used for representing a channel for receiving the analog signal in a plurality of internal analog channels in the chip, the internal analog channel identifier comprises a character string composed of binary characters, and each internal analog channel is concentrated in the chip, and the character string corresponding to each channel for receiving the analog signal is different; the internal analog channel identifier can be used for distinguishing different internal analog channels in one internal analog channel set and can also be used for distinguishing all internal analog channels in a chip.

In some embodiments, the apparatus may further confirm at least one of the first analog multiplexer and the second analog multiplexer corresponding to the analog channel identification based on the trigger event and the pre-configured trigger event channel selection lookup table. That is, the device requires an analog multiplexer that acknowledges receipt of the on signal.

The analog multiplexer comprises a first analog multiplexer and a second analog multiplexer, or at least one analog multiplexer and a second analog multiplexer. In some alternative embodiments, if the analog multiplexer includes a first analog multiplexer and a second analog multiplexer, the first analog multiplexer and the second analog multiplexer may be integrated. The at least one first analog multiplexer corresponds to at least one analog-to-digital converter corresponding to the trigger event.

For example, if the corresponding analog-to-digital converter is identified as analog-to-digital converter 1 based on the trigger event and its corresponding first analog multiplexer is first analog multiplexer 1, the device needs to identify the first analog multiplexer 1 based on the trigger event.

Step S403, receiving at least one analog signal based on the analog channel corresponding to the analog channel identifier.

In some embodiments, in response to the analog multiplexer including at least one first analog multiplexer and one second analog multiplexer, the apparatus sends a second on signal to the at least one first analog multiplexer and the second analog multiplexer based on the trigger event, so that the at least one first analog multiplexer turns on a first internal analog channel corresponding to an analog-to-digital converter corresponding to the second on signal based on the second on signal, and the second analog multiplexer turns on a first external analog channel included in an off-chip module corresponding to the second on signal based on the second on signal; an analog signal is received based on the first external analog channel and the first internal analog channel. The second on signal includes a first internal analog channel identification and a first external analog channel identification, and the device sends the second on signal to the at least one first analog multiplexer and the second analog multiplexer, respectively.

Wherein the first external analog channel comprises at least one external analog sub-channel and the first internal analog channel comprises at least one internal analog sub-channel.

In the implementation, if the chip is externally connected with a module to expand an external simulation channel, that is, the device confirms that the simulation channel identifier comprises a second internal simulation channel and a second external simulation channel based on the triggering event, a second conduction signal is sent to a first simulation multiplexer and a second simulation multiplexer corresponding to the triggering event respectively, so that the first simulation multiplexer conducts the second internal simulation channel based on the second conduction signal, and the second simulation multiplexer conducts the second external simulation channel; an analog-to-digital converter receives an analog signal based on the second internal analog channel and the second external analog channel. The second on signal includes a second internal analog channel identification and a second external analog channel identification, and the device sends the second on signal to the first analog multiplexer and the second analog multiplexer, respectively.

Or, in the implementation, if the chip is externally connected with more than two modules to expand external analog channels, that is, the device confirms a first analog multiplexer and a second analog multiplexer based on the trigger event, confirms that the analog channel identifier includes at least one internal analog channel identifier and at least one external analog channel identifier, and takes two as an example, a third internal analog channel identifier, a fourth internal analog channel identifier, a third external analog channel identifier and a fourth external analog channel identifier, the device sends second conducting signals to the at least one first analog multiplexer and the second analog multiplexer respectively, so that the at least one first analog multiplexer conducts the third internal analog channel corresponding to the third internal analog channel identifier and the fourth internal analog channel corresponding to the fourth internal analog channel identifier respectively, and the second analog multiplexer conducts the third external analog channel corresponding to the third external analog channel identifier and the fourth external analog channel corresponding to the fourth external analog channel identifier; the analog-to-digital converter receives analog signals based on the third internal analog channel, the fourth internal analog channel, the third external analog channel, and the fourth external analog channel. The third internal analog channel and the fourth internal analog channel are positioned in an internal analog channel set corresponding to the analog-to-digital converter, respectively receive analog signals transmitted by different chip external modules, and are respectively positioned in different chip external modules. The apparatus sends the second turn-on signal to at least one first analog multiplexer and a second analog multiplexer, respectively. The second conduction signal comprises a third internal analog channel identifier, a fourth internal analog channel identifier, a third external analog channel identifier and a fourth external analog channel identifier, and the device sends the second conduction signal to the first analog multiplexer and the second analog multiplexer respectively.

Or, in the implementation, if the chip is externally connected with more than two modules to expand the external analog channels, and the chip includes multiple analog-to-digital converters, that is, the device confirms at least one first analog multiplexer and at least one second analog multiplexer based on the trigger event, confirms that the analog channel identifier includes at least one internal analog channel identifier and at least one external analog channel identifier, and takes two as, for example, the fifth internal analog channel identifier, the sixth internal analog channel identifier, the fifth external analog channel identifier and the sixth external analog channel identifier, the device sends second conduction signals to the at least one first analog multiplexer and the second analog multiplexer, so that the at least one first analog multiplexer respectively conducts the fifth internal analog channel corresponding to the fifth internal analog channel identifier and the sixth internal analog channel corresponding to the sixth internal analog channel identifier, and the second analog multiplexer respectively conducts the fifth external analog channel corresponding to the fifth external analog channel identifier and the sixth external analog channel identifier; the analog-to-digital converter receives analog signals based on the fifth internal analog channel, the sixth internal analog channel, the fifth external analog channel, and the sixth external analog channel. The fifth internal analog channel and the sixth internal analog channel are respectively positioned in the internal analog channel sets corresponding to different analog-to-digital converters, respectively receive analog signals transmitted by different external chip modules, and are respectively positioned in different external chip modules. The second conduction signal comprises a fifth internal analog channel identifier, a sixth internal analog channel identifier, a fifth external analog channel identifier and a sixth external analog channel identifier; the device sends the second conducting signal to at least one first analog multiplexer and one second analog multiplexer, and in this embodiment, taking 2 first analog multiplexers and 1 second analog multiplexer as examples, the device sends a fifth sub-signal included in the second conducting signal to the first analog multiplexer 1, where the fifth sub-signal includes a fifth internal analog channel identifier and a fifth external analog channel identifier; transmitting a sixth sub-signal included in the second on signal to the first analog multiplexer 2, the sixth sub-signal including a sixth internal analog channel identifier and a sixth external analog channel identifier; the fifth sub-signal and the sixth sub-signal are respectively transmitted to the second analog multiplexer.

Or, in the implementation, if the chip is externally connected with more than two modules to expand external analog channels, and the chip includes a plurality of analog-to-digital converters, when receiving analog signals, the number of internal analog channels used is greater than the number of external analog channels, that is, the device confirms at least one first analog multiplexer and one second analog multiplexer based on the triggering event, and confirms that the analog channel identification includes at least one internal analog channel identification and at least one external analog channel identification, and the number of at least one internal analog channel identification is greater than the number of at least one external analog channel identification; taking three internal analog channel identifiers and two external analog channel identifiers as examples, such as a seventh internal analog channel identifier, an eighth internal analog channel identifier, a ninth internal analog channel identifier, a seventh external analog channel identifier and an eighth external analog channel identifier; the device sends a second conducting signal to the at least one first analog multiplexer and the second analog multiplexer respectively, so that the at least one first analog multiplexer conducts a seventh internal analog channel corresponding to a seventh internal analog channel identifier, conducts a eighth internal analog channel corresponding to an eighth internal analog channel identifier and a ninth internal analog channel corresponding to a ninth internal analog channel identifier, and enables the second analog multiplexer to conduct a seventh external analog channel corresponding to a seventh external analog channel identifier and an eighth external analog channel corresponding to an eighth external analog channel identifier; the analog-to-digital converter receives analog signals based on a seventh internal analog channel, an eighth internal analog channel, a ninth internal analog channel, a seventh external analog channel, and an eighth external analog channel. The seventh internal analog channel, the eighth internal analog channel and the ninth internal analog channel are respectively located in the internal analog channel sets corresponding to different analog-to-digital converters, the seventh internal analog channel and the eighth internal analog channel respectively receive analog signals transmitted by different external chip modules, and the seventh external analog channel and the eighth external analog channel are respectively located in different external chip modules. The second conduction signal comprises a seventh internal analog channel identifier, an eighth internal analog channel identifier, a ninth internal analog channel identifier, a seventh external analog channel identifier and an eighth external analog channel identifier; the device sends the second conducting signal to at least one first analog multiplexer and one second analog multiplexer, and in this embodiment, taking 3 first analog multiplexers and 1 second analog multiplexer as examples, the device sends a seventh sub-signal included in the second conducting signal to the first analog multiplexer 1, where the seventh sub-signal includes a seventh internal analog channel identifier and a seventh external analog channel identifier; transmitting an eighth sub-signal included in the second on signal to the first analog multiplexer 2, the eighth sub-signal including an eighth internal analog channel identifier and an eighth external analog channel identifier; transmitting a ninth sub-signal included in the second on signal to the first analog multiplexer 3, the ninth sub-signal including a ninth internal analog channel identifier; the seventh sub-signal and the eighth sub-signal are respectively transmitted to the second analog multiplexer.

That is, the plurality of analog-to-digital converters inside the chip receive analog signals based on the ninth internal analog channel, the seventh internal analog channel, and the seventh external analog channel, and the eighth internal analog channel and the eighth external analog channel, respectively.

In other embodiments, in response to the analog multiplexer including a first analog multiplexer and a second analog multiplexer, the first analog multiplexer and the second analog multiplexer may be integrated, the apparatus may send a second on signal to the analog multiplexer based on the trigger event to cause the analog multiplexer to turn on a second internal analog channel and a first external analog channel based on the second on signal; an analog signal is received based on the first external analog channel and the second internal analog channel.

Wherein the first external analog channel comprises at least one external analog sub-channel and the second internal analog channel comprises at least one internal analog sub-channel, the number of external analog sub-channels being less than or equal to the number of internal analog sub-channels.

In the implementation, if the chip is externally connected with a module to expand an external analog channel, that is, the device confirms that the analog channel identifier comprises a second internal analog channel and a second external analog channel based on the trigger event, a second conducting signal is sent to an analog multiplexer corresponding to the trigger event respectively, so that a first analog multiplexer comprising the analog multiplexer conducts the second internal analog channel based on the second conducting signal, and the second analog multiplexer comprising the analog multiplexer conducts the second external analog channel; an analog-to-digital converter receives an analog signal based on the second internal analog channel and the second external analog channel. The second on signal includes a second internal analog channel identification and a second external analog channel identification, the second internal analog channel identification being independently transmittable to the first analog multiplexer, and the second external analog channel identification being independently transmittable to the second analog multiplexer.

Or, in the implementation, if the chip is externally connected with more than two modules, expansion of an external analog channel is performed, but a signal is received by an analog-to-digital converter; that is, the analog-digital converter has centralized corresponding internal analog channels, and different internal analog channels receive analog signals of different external modules of the chip; however, the internal analog channels cannot simultaneously receive analog signals of different external modules of the chip, that is, the analog-to-digital converter can only receive analog signals of one internal analog channel at the same time. Because each analog-to-digital converter corresponds to only one analog multiplexer, in this embodiment, a second on signal with different contents needs to be sent to the analog multiplexer, for example, a third on sub signal is sent first, so that the first analog multiplexer included in the analog multiplexer conducts a third internal analog channel corresponding to a third internal analog channel identifier, and the second analog multiplexer included in the analog multiplexer conducts a third external analog channel corresponding to a third external analog channel identifier; then, a fourth conduction sub-signal is sent again, so that a first analog multiplexer included in the analog multiplexer conducts a fourth internal analog channel corresponding to a fourth internal analog channel identifier, and a second analog multiplexer included in the analog multiplexer conducts a fourth external analog channel corresponding to a fourth external analog channel identifier; the third on sub-signal comprises a third internal analog channel identifier and a third external analog channel identifier, wherein the third internal analog channel identifier can be independently sent to the first analog multiplexer, and the third external analog channel identifier can be independently sent to the second analog multiplexer; the fourth on sub-signal includes a fourth internal analog channel identifier and a fourth external analog channel identifier, where the fourth internal analog channel identifier may be separately sent to the first analog multiplexer, and the fourth external analog channel identifier may be separately sent to the second analog multiplexer.

Or in the implementation, if the chip is externally connected with more than two modules to expand the external analog channel, and the chip includes multiple analog-to-digital converters, that is, the device confirms at least one analog multiplexer based on the trigger event, confirms that the analog channel identifier includes at least one internal analog channel identifier and at least one external analog channel identifier, and takes two as examples, for example, the fifth internal analog channel identifier, the sixth internal analog channel identifier, the fifth external analog channel identifier and the sixth external analog channel identifier, the device sends second conduction signals to the at least one analog multiplexer respectively, so that the first analog multiplexer included in the at least one analog multiplexer respectively conducts the fifth internal analog channel corresponding to the fifth internal analog channel identifier and the sixth internal analog channel corresponding to the sixth internal analog channel identifier, and the second analog multiplexer included in the at least one analog multiplexer respectively conducts the fifth external analog channel corresponding to the fifth external analog channel identifier and the sixth external analog channel corresponding to the sixth external analog channel identifier; the at least one analog-to-digital converter receives analog signals based on the fifth internal analog channel, the sixth internal analog channel, the fifth external analog channel, and the sixth external analog channel. The fifth internal analog channel and the sixth internal analog channel are respectively positioned in the internal analog channel sets corresponding to different analog-to-digital converters, respectively receive analog signals transmitted by different external chip modules, and are respectively positioned in different external chip modules. The second conduction signal comprises a fifth conduction sub-signal and a sixth conduction sub-signal, the fifth conduction sub-signal can comprise a fifth internal analog channel identifier and a fifth external analog channel identifier, the fifth internal analog channel identifier can be independently sent to the first analog multiplexer, and the fifth external analog channel identifier can be independently sent to the second analog multiplexer; the sixth on sub-signal includes a sixth internal analog channel identifier and a sixth external analog channel identifier, where the sixth internal analog channel identifier may be separately sent to the first analog multiplexer, and the sixth external analog channel identifier may be separately sent to the second analog multiplexer.

Or, in the implementation, if the chip is externally connected with more than two modules to expand external analog channels, and the chip internally comprises a plurality of analog-to-digital converters, when receiving analog signals, the number of internal analog channels used is greater than the number of external analog channels, that is, the device confirms at least one analog multiplexer based on the trigger event, and confirms that the analog channel identification comprises at least one internal analog channel identification and at least one external analog channel identification, and the number of at least one internal analog channel identification is greater than the number of at least one external analog channel identification; taking three internal analog channel identifiers and two external analog channel identifiers as examples, such as a seventh internal analog channel identifier, an eighth internal analog channel identifier, a ninth internal analog channel identifier, a seventh external analog channel identifier and an eighth external analog channel identifier; the device respectively conducts a seventh internal analog channel corresponding to a seventh internal analog channel identifier and a seventh external analog channel corresponding to a seventh external analog channel identifier to the at least one analog multiplexer, conducts an eighth internal analog channel corresponding to an eighth internal analog channel identifier and an eighth external analog channel corresponding to an eighth external analog channel identifier, and conducts a ninth internal analog channel corresponding to a ninth internal analog channel identifier; the analog-to-digital converter receives analog signals based on a seventh internal analog channel, an eighth internal analog channel, a ninth internal analog channel, a seventh external analog channel, and an eighth external analog channel. The seventh internal analog channel, the eighth internal analog channel and the ninth internal analog channel are respectively located in the internal analog channel sets corresponding to different analog-to-digital converters, the seventh internal analog channel and the eighth internal analog channel respectively receive analog signals transmitted by different external chip modules, and the seventh external analog channel and the eighth external analog channel are respectively located in different external chip modules. The second on signal may include a seventh on sub-signal, an eighth on sub-signal, and a ninth on sub-signal; the seventh on sub-signal comprises a seventh internal analog channel identifier and a seventh external analog channel identifier, which are respectively sent to a first analog multiplexer and a second analog multiplexer included in an analog multiplexer corresponding to the seventh internal analog channel; the eighth on sub-signal comprises an eighth internal analog channel identifier and an eighth external analog channel identifier, which are respectively sent to a first analog multiplexer and a second analog multiplexer which are included in an analog multiplexer corresponding to the eighth internal analog channel; the ninth conduction sub-signal comprises a ninth internal analog channel identifier, and the ninth conduction sub-signal is sent to a first analog multiplexer included in an analog multiplexer corresponding to the ninth internal analog channel.

Step S404, performing analog-to-digital conversion on the at least one path of analog signal to obtain an analog-to-digital conversion result.

In some embodiments, the device performs analog-to-digital conversion on the at least one analog signal based on an analog-to-digital converter to obtain an analog-to-digital conversion result.

The analog-to-digital conversion result comprises a signal path identifier corresponding to the at least one path of analog signals and a result of converting the at least one path of analog signals into digital signals; the signal path identifier comprises at least one internal analog channel identifier and an external analog channel identifier.

Fig. 4 shows a second alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure.

Fig. 4 shows the case where the analog multiplexer includes at least a first analog multiplexer for controlling the conduction or the closure of each internal analog channel in the internal analog channel set and a second analog multiplexer for controlling the conduction or the closure of each external analog channel in the external module, only one analog-to-digital converter is involved in fig. 4, so that the number of the first analog multiplexer is the same as the number of the second analog multiplexers. In fig. 4, each analog-to-digital converter corresponds to one first analog multiplexer, but only 1 second analog multiplexer is included in the chip.

As shown in fig. 4, the chip includes an analog-to-digital converter and an internal analog channel set corresponding to the analog-to-digital converter, the chip is externally connected with a module, the module includes 8 external analog channels (Y0 to Y7), the module receives the on signals sent by the second analog multiplexer based on A0, A1 and A2, and the analog signals received by the external analog channels are transmitted to the internal analog channel set based on the ports.

In some embodiments, in response to generating a trigger event, the apparatus identifies a first analog multiplexer, an internal analog channel identification (e.g., CH 0), a second analog multiplexer, and an external analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table; and sending a second conduction signal to the first analog multiplexer and the second analog multiplexer, so that the first analog multiplexer conducts the internal analog channels with the internal analog channels being intensively marked as CH0, and the second analog multiplexer conducts the external analog channels corresponding to the external analog channel marks in the external chip module. The analog-to-digital converter receives an analog signal based on the external analog channel identification and CH0, and ADC1 performs analog-to-digital conversion on the analog signal, and outputs an analog-to-digital conversion result including a signal path identification (AMSEL [0:8 ]) and a result of converting the analog signal into a digital signal (SAR [0:11 ]). The second conduction signal comprises an internal analog channel identifier and an external channel identifier, the second conduction signal received by the first analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time, and the second conduction signal received by the second analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time.

In some alternative embodiments, the apparatus may send the second on signal to the first analog multiplexer and the second analog multiplexer, respectively, to configure the first analog multiplexer and the second analog multiplexer, respectively. Specifically, the second conduction signal sent by the device to the first analog multiplexer comprises an internal analog channel identifier and an external analog channel identifier; the second conducting signal sent by the device to the second analog multiplexer may only include the external analog channel identifier, and the part of the internal analog channel identifier, i.e., AMSEL [0:5], may be any character. In fig. 4, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

In some embodiments, in the analog-to-digital conversion result, the signal path identification AMSEL [0:8], AMSEL [8:6] is the same as the external analog channel identification.

Fig. 5 shows a third alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure.

Fig. 5 shows a case where the analog multiplexer includes a first analog multiplexer and a second analog multiplexer. In fig. 5, each analog-to-digital converter corresponds to an analog multiplexer, and the analog multiplexer is used for controlling the on or off of the internal analog channels in the corresponding internal analog channel set, and the on or off of the external analog channels included in the corresponding external module, and a plurality of analog multiplexers may be included in the chip.

As shown in fig. 5, the chip includes an analog-to-digital converter and an internal analog channel set corresponding to the analog-to-digital converter, the chip is externally connected with a module, the module includes 8 external analog channels (Y0 to Y7), the module receives the on signals sent by the second analog multiplexer based on A0, A1 and A2, and the analog signals received by the external analog channels are transmitted to the internal analog channel set based on the ports.

In some embodiments, in response to generating a trigger event, the apparatus validates the analog multiplexer, the internal analog channel identification (e.g., CH 0), the external analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table; and sending a second conduction signal to the analog multiplexer so that the first analog multiplexer conducts the internal analog channels with the internal analog channel centralized identifier of CH0, and the second analog multiplexer conducts the external analog channels corresponding to the external analog channel identifier in the external chip module. The analog-to-digital converter receives an analog signal based on the external analog channel identification and CH0, and ADC1 performs analog-to-digital conversion on the analog signal, and outputs an analog-to-digital conversion result including a signal path identification (AMSEL [0:8 ]) and a result of converting the analog signal into a digital signal (SAR [0:11 ]). The second conducting signal comprises an internal analog channel identifier and an external analog channel identifier, but the conducting signal received by the first analog multiplexer only comprises the internal analog channel identifier, and the conducting signal received by the second analog multiplexer only comprises the external analog channel identifier.

In some alternative embodiments, the apparatus may send the second on signal to the first analog multiplexer and the second analog multiplexer, respectively, to configure the first analog multiplexer and the second analog multiplexer, respectively. Specifically, the device includes an internal analog channel identifier in a second conduction signal sent to the first analog multiplexer; the second conducting signal sent by the device to the second analog multiplexer only comprises an external analog channel identifier, and the part of the internal analog channel identifier, namely AMSEL [0:5], can be any character. In fig. 5, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

Further, expanding the scheme of fig. 5, the chip includes a plurality of analog-to-digital converters, each corresponding to an analog multiplexer, an internal analog channel set, and an external module; correspondingly, the chip internally comprises a plurality of analog multiplexers, a plurality of internal analog channel sets and a plurality of external modules; each analog multiplexer is used for controlling the on or off of the internal analog channels in the corresponding internal analog channel set and the on or off of the external analog channels included in the corresponding external module.

Fig. 6 shows a fourth alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure.

As shown in fig. 6, the chip includes 3 analog-to-digital converters, 3 internal analog channel sets corresponding to the 3 analog-to-digital converters, the chip is externally connected with 3 modules, each chip external module includes 8 external analog channels (Y0 to Y7), the 3 chip external modules each receive the on signal sent by the second analog multiplexer based on A0, A1 and A2, and the analog signal received by the external analog channels is transmitted to the internal analog channel sets based on the ports. Those skilled in the art will appreciate that 2 or more analog-to-digital converters may also be included in the chip, with 3 being merely exemplary in this disclosure and not intended to limit the disclosure.

In some embodiments, each analog-to-digital converter can expand the external analog channels respectively (i.e., each analog-to-digital converter can expand the external analog channels by means of a module externally connected to the chip), and each analog-to-digital converter can expand the external analog channels by means of a plurality of modules externally connected simultaneously (after expansion, the number of external analog channels is 8×n, n is the number of modules externally connected to the chip, and 8 is the number of external analog channels included in each external module of the chip). Each trigger event can trigger one analog-to-digital converter independently or trigger a plurality of analog-to-digital converters, and correspondingly, when triggering one analog-to-digital converter, the conditions of conducting one internal analog channel, conducting one internal analog channel and one external analog channel and conducting one internal analog channel and a plurality of external analog channels are included; when the plurality of analog-to-digital converters are triggered, including the case of switching on the plurality of internal analog channels and the plurality of external analog channels, the plurality of analog-to-digital converters are switched on as an example.

In some embodiments, in response to generating a trigger event, the apparatus identifies at least one analog multiplexer (e.g., analog multiplexer 1, analog multiplexer 2, and analog multiplexer 3 of fig. 6), an internal analog channel identification (e.g., CH0, CH1, and CH 2), and an external analog channel identification based on the trigger event and a preconfigured trigger event channel selection look-up table; and sending a second conduction signal to the at least one analog multiplexer to enable the at least one analog multiplexer to conduct the internal analog channels with the internal analog channels being marked as CH0, CH1 and CH2 in a centralized manner, specifically, enable the analog multiplexer 1 to conduct the internal analog channels with the corresponding internal analog channels being marked as CH0 in a centralized manner and the corresponding external analog channels in the external module 1, enable the analog multiplexer 2 to conduct the internal analog channels with the corresponding internal analog channels being marked as CH1 in a centralized manner and the corresponding external analog channels in the external module 2, and enable the analog multiplexer 3 to conduct the internal analog channels with the corresponding internal analog channels being marked as CH2 in a centralized manner and the corresponding external analog channels in the external module 3. The analog-to-digital converter receives analog signals based on 3 external analog channel identifiers, CH0, CH1 and CH2, specifically, the ADC1 receives analog signals based on an internal analog channel identified as CH0 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the ADC2 receives analog signals based on an internal analog channel marked as CH1 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the ADC3 receives analog signals based on an internal analog channel marked as CH2 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the analog-to-digital conversion results each include a signal path identification (AMSEL [0:8 ]) and a result of converting an analog signal into a digital signal (SAR [0:11 ]). The second conduction signal comprises an internal analog channel identifier and an external channel identifier, the second conduction signal received by the first analog multiplexer comprises the internal analog channel identifier, and the second conduction signal received by the second analog multiplexer comprises the external analog channel identifier.

In some alternative embodiments, the apparatus may send the second on signal to at least one analog multiplexer, respectively, to configure at least one first analog multiplexer and at least one second analog multiplexer, respectively. Specifically, the second conduction signal sent by the device to at least one analog multiplexer includes an internal analog channel identifier and an external analog channel identifier, where the internal analog channel identifier includes CH0, CH1, and CH2. In fig. 6, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

In some embodiments, the chip may be externally connected with two or more external modules, but performs analog-to-digital conversion based on only one analog-to-digital converter; optionally, the first analog multiplexer may be used to control the on or off of the internal analog channels in the internal analog channel set, and the second analog multiplexer may be used to control the on or off of the external analog channels included in the external module; the on or off of the internal analog channels in the set of internal analog channels and the on or off of the external analog channels comprised by the external module may also be controlled based on the analog multiplexer.

Fig. 7 shows a fifth alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure.

Fig. 7 shows a scenario in which two or more external modules are connected to a chip, and the internal analog channels in the internal analog channel set can be controlled to be turned on or turned off based on the first analog multiplexer, and the external analog channels included in the external modules can be controlled to be turned on or turned off based on the second analog multiplexer, respectively. Those skilled in the art will appreciate that the number of the external modules in fig. 7 is only an example, and may be 3 or more. In fig. 7, the case where the analog multiplexer includes at least a first analog multiplexer and a second analog multiplexer only involves one analog-to-digital converter in fig. 7, so the number of the first analog multiplexer is the same as the number of the second analog multiplexer. In fig. 7, each analog-to-digital converter corresponds to one first analog multiplexer, but only 1 second analog multiplexer is included in the chip.

As shown in fig. 7, the chip includes an analog-to-digital converter and an internal analog channel set corresponding to the analog-to-digital converter, the chip is externally connected with two modules, the modules include 8 external analog channels (Y0 to Y7), the two external chip modules each receive the on signal sent by the second analog multiplexer based on A0, A1 and A2, and the analog signal received by the external analog channel is transmitted to the internal analog channel set based on the port.

In some embodiments, in response to generating a trigger event, the apparatus identifies a first analog multiplexer, an internal analog channel identification (e.g., CH 0), a second analog multiplexer, and an external analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table; and sending a second conduction signal to the first analog multiplexer and the second analog multiplexer, so that the first analog multiplexer conducts the internal analog channels with the internal analog channels being marked as CH0 and CH1 in a centralized way, and the second analog multiplexer conducts two external analog channels corresponding to the external analog channel marks in the external chip module. The analog-to-digital converter receives analog signals based on two external analog channel identifications, CH0 and CH1, and ADC1 performs analog-to-digital conversion on the analog signals, and outputs analog-to-digital conversion results, respectively, each of which includes a signal path identification (AMSEL [0:8 ]) and a result (SAR [0:11 ]) of converting the analog signals into digital signals. The second conduction signal comprises an internal analog channel identifier and an external channel identifier, the second conduction signal received by the first analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time, and the second conduction signal received by the second analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time.

In some alternative embodiments, the apparatus may send the second on signal to the first analog multiplexer and the second analog multiplexer, respectively, to configure the first analog multiplexer and the second analog multiplexer, respectively. Specifically, the second conduction signal sent by the device to the first analog multiplexer comprises an internal analog channel identifier and an external analog channel identifier, wherein the internal analog channel identifier comprises CH1 and CH0; the second conducting signal sent by the device to the second analog multiplexer may only include an external analog channel identifier (alternatively, the external analog channel identifiers of the external analog channels to be conducted in the two external chip modules are the same), and the part of the internal analog channel identifier, that is, AMSEL [0:5], may be any character. In fig. 7, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

In some embodiments, in the analog-to-digital conversion result, the signal path identification AMSEL [0:8], AMSEL [8:6] is the same as the external analog channel identification. The results of analog-to-digital conversion of analog signals received based on different external analog channel identifications and different internal analog channel identifications are shown in table 1.

TABLE 1

As shown in table 1, when the device sends a turn-on signal to the second analog multiplexer to configure the second analog multiplexer, only the identifier of the external analog channel is sent, the identifier of the internal analog channel is not sent, or the identifier of the internal analog channel is not active; and when sending a turn-on signal to the first analog multiplexer to configure the first analog multiplexer, both the external analog channel identification and the internal analog channel identification are involved. The final analog-to-digital conversion result includes a signal path identifier (an external analog channel identifier and an internal analog channel identifier) and a result of converting the analog signal into a digital signal.

Fig. 8 shows a sixth alternative schematic diagram of a data processing method provided by an embodiment of the disclosure.

Fig. 8 corresponds to fig. 7, and fig. 8 shows a scenario in which two or more external modules are externally connected to a chip, and the conduction or closure of an internal analog channel in the internal analog channel set and the conduction or closure of an external analog channel included in the external module can be controlled based on an analog multiplexer. Those skilled in the art will appreciate that the number of the external modules in fig. 8 is only an example, and may be 3 or more.

Fig. 8 shows the case where the analog multiplexer includes a first analog multiplexer and a second analog multiplexer. In fig. 8, each analog-to-digital converter corresponds to an analog multiplexer.

As shown in fig. 8, the chip includes an analog-to-digital converter and an internal analog channel set corresponding to the analog-to-digital converter, the chip is externally connected with two modules, the modules include 8 external analog channels (Y0 to Y7), the two external chip modules each receive the on signal sent by the second analog multiplexer based on A0, A1 and A2, and the analog signal received by the external analog channel is transmitted to the internal analog channel set based on the port.

In some embodiments, in response to generating a trigger event, the apparatus validates the analog multiplexer, the internal analog channel identification (e.g., CH 0), and the external analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table; and sending a second conduction signal to the analog multiplexer so that the analog multiplexer conducts an internal analog channel with the internal analog channel being intensively marked as CH0 or CH1 and two external analog channels corresponding to the external analog channel mark in the external chip module. The analog-to-digital converter receives analog signals based on two external analog channel identifications, CH0 and CH1, and ADC1 performs analog-to-digital conversion on the analog signals, and outputs analog-to-digital conversion results, respectively, each of which includes a signal path identification (AMSEL [0:8 ]) and a result (SAR [0:11 ]) of converting the analog signals into digital signals. The second conduction signal comprises an internal analog channel identifier and an external channel identifier, the conduction signal received by the first analog multiplexer comprises the internal analog channel identifier, and the conduction signal received by the second analog multiplexer comprises the external analog channel identifier. Optionally, when the chip is externally connected with 3 or more than 3 external modules, 3 or more than 3 internal analog channels are respectively conducted; that is, the number of internal analog channels that are turned on may be determined according to the number of external modules.

In some alternative embodiments, the apparatus may send the second on signal to the first analog multiplexer and the second analog multiplexer, respectively, to configure the first analog multiplexer and the second analog multiplexer, respectively. Specifically, the second conducting signal sent by the device to the first analog multiplexer comprises an internal analog channel identifier, and the internal analog channel identifier comprises CH1 or CH0; the second conducting signal sent by the device to the second analog multiplexer comprises an external analog channel identifier (optionally, the external analog channel identifiers of the external analog channels to be conducted in the two external chip modules are the same), and the part of the internal analog channel identifier, namely AMSEL [0:5], can be any character. In fig. 8, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

The analog-to-digital converter can only receive analog signals sent by the same internal analog channel at the same time, and the device needs to send different conducting signals to the analog multiplexer, for example, CH0 and the corresponding external analog channel are conducted first, CH1 and the corresponding external analog channel are conducted second, and when the conducted signal paths are different, the content of the conducting signals is also different.

In some embodiments, in the analog-to-digital conversion result, the signal path identification AMSEL [0:8], AMSEL [8:6] is the same as the external analog channel identification. The results of analog-to-digital conversion of the analog signals received based on the different external analog channel identifications and the different internal analog channel identifications are shown in table 2.

TABLE 2

As shown in table 2, when the device sends a turn-on signal to the analog multiplexer to configure the analog multiplexer, only the identifier of the external analog channel is sent to the second analog multiplexer, and the identifier of the internal analog channel is not sent; and a turn-on signal is sent to the analog multiplexer to configure the first analog multiplexer, only the internal analog channel identification is involved. The final analog-to-digital conversion result includes a signal path identifier (an external analog channel identifier and an internal analog channel identifier) and a result of converting the analog signal into a digital signal.

In some embodiments, the switching on or off of the external analog channel of one external module can be controlled by the analog multiplexer or the second analog multiplexer; the connection or the closure of the external analog channels of all external modules can be controlled by an analog multiplexer or a second analog multiplexer; fig. 9 and 10 show the scenario in which the analog multiplexer, or the second analog multiplexer, controls the on or off of the external analog channels of all the external modules, and the analog multiplexer, or the first analog multiplexer, respectively controls the on or off of the internal analog channels in the corresponding internal analog channel set.

Fig. 9 shows a seventh alternative schematic diagram of a data processing method provided by an embodiment of the present disclosure.

FIG. 9 shows an analog multiplexer including at least a first analog multiplexer and a second analog multiplexer, the second analog multiplexer controlling the conduction or closure of the external analog channels included in all external modules, each first analog multiplexer controlling the conduction or closure of the internal analog channels in an internal analog channel set, respectively. It should be understood by those skilled in the art that any number of external modules, such as 2 or more than 4, may be externally connected in fig. 9, and that the external 3 external modules in fig. 9 are only examples and are not intended to limit the disclosure, and in addition, no matter how many external modules are controlled by the second analog multiplexer.

As shown in fig. 9, the chip includes 3 analog-to-digital converters, 3 internal analog channel sets corresponding to the 3 analog-to-digital converters, the chip is externally connected with 3 modules, each of the chip external modules includes 8 external analog channels (Y0 to Y7), the 3 chip external modules each receive the on signal sent by the second analog multiplexer based on A0, A1 and A2, and the analog signal received by the external analog channels is transmitted to the internal analog channel sets based on the ports.

In some embodiments, in response to generating a trigger event, the apparatus identifies at least one first analog multiplexer (e.g., first analog multiplexer 1, first analog multiplexer 2, and first analog multiplexer 3 in fig. 9), an internal analog channel identification (e.g., CH0, CH1, and CH 2), a second analog multiplexer, and an external analog channel identification based on the trigger event and a preconfigured trigger event channel selection look-up table; sending a second conducting signal to the at least one first analog multiplexer and the second analog multiplexer, so that the at least one first analog multiplexer conducts the internal analog channels with the internal analog channels being centrally marked as CH0, CH1 and CH2 respectively, specifically, the first analog multiplexer 1 conducts the internal analog channels with the corresponding internal analog channels being centrally marked as CH0, the first analog multiplexer 2 conducts the internal analog channels with the corresponding internal analog channels being centrally marked as CH1, and the first analog multiplexer 3 conducts the internal analog channels with the corresponding internal analog channels being centrally marked as CH 2; and enabling the second analog multiplexer to conduct 3 external analog channels corresponding to the external analog channel identifiers in the 3 chip external modules. The analog-to-digital converter receives analog signals based on 3 external analog channel identifiers, CH0, CH1 and CH2, specifically, the ADC1 receives analog signals based on an internal analog channel identified as CH0 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the ADC2 receives analog signals based on an internal analog channel marked as CH1 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the ADC3 receives analog signals based on an internal analog channel marked as CH2 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the analog-to-digital conversion results each include a signal path identification (AMSEL [0:8 ]) and a result of converting an analog signal into a digital signal (SAR [0:11 ]). The second conduction signal comprises an internal analog channel identifier and an external channel identifier, the second conduction signal received by the first analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time, and the second conduction signal received by the second analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time.

In some alternative embodiments, the apparatus may send the second on signal to at least one first analog multiplexer and second analog multiplexer, respectively, to configure the at least one first analog multiplexer and second analog multiplexer, respectively. Specifically, the second conduction signal sent by the device to at least one first analog multiplexer includes an internal analog channel identifier and an external analog channel identifier, where the internal analog channel identifier includes CH0, CH1 and CH2; the second conducting signal sent by the device to the second analog multiplexer may only include an external analog channel identifier (alternatively, the external analog channel identifiers of the external analog channels to be conducted in the two external chip modules are the same), and the part of the internal analog channel identifier, that is, AMSEL [0:5], may be any character. In fig. 9, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

Fig. 10 shows an eighth alternative schematic diagram of a data processing method provided by an embodiment of the disclosure.

FIG. 10 shows an analog multiplexer including at least one analog multiplexer, wherein one analog multiplexer controls the on or off of the external analog channels included in all external modules, and each analog multiplexer controls the on or off of the internal analog channels in an internal analog channel set, respectively. It should be understood by those skilled in the art that any number of external modules, such as 2 or more than 4, may be externally connected in fig. 10, and that 3 external modules are only examples in fig. 10, and are not intended to limit the disclosure, and in addition, no matter how many external modules are controlled by one analog multiplexer.

As shown in fig. 10, the chip includes 3 analog-to-digital converters, 3 internal analog channel sets corresponding to the 3 analog-to-digital converters, the chip is externally connected with 3 modules, each of the chip external modules includes 8 external analog channels (Y0 to Y7), the 3 chip external modules each receive the on signal sent by the second analog multiplexer based on A0, A1 and A2, and the analog signal received by the external analog channels is transmitted to the internal analog channel sets based on the ports.

In some embodiments, in response to generating a trigger event, the apparatus identifies at least one analog multiplexer (e.g., first analog multiplexer 1, first analog multiplexer 2, and first analog multiplexer 3 in fig. 10), an internal analog channel identification (e.g., CH0, CH1, and CH 2), an analog multiplexer controlling an external analog channel, and an external analog channel identification based on the trigger event and a preconfigured trigger event channel selection look-up table; sending a second conducting signal to the at least one analog multiplexer, so that the at least one analog multiplexer conducts the internal analog channels with the internal analog channel set identifier of CH0, CH1 and CH2 and the external analog channel respectively, specifically, the first analog multiplexer 1 conducts the internal analog channel with the corresponding internal analog channel set identifier of CH0, the first analog multiplexer 2 conducts the internal analog channel with the corresponding internal analog channel set identifier of CH1, and the first analog multiplexer 3 conducts the internal analog channel with the corresponding internal analog channel set identifier of CH 2; the analog multiplexer is enabled to conduct 3 external analog channels corresponding to the external analog channel identifiers in the 3 chip external modules. The analog-to-digital converter receives analog signals based on 3 external analog channel identifiers, CH0, CH1 and CH2, specifically, the ADC1 receives analog signals based on an internal analog channel identified as CH0 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the ADC2 receives analog signals based on an internal analog channel marked as CH1 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the ADC3 receives analog signals based on an internal analog channel marked as CH2 and a corresponding external analog channel, and performs analog-to-digital conversion to obtain an analog-to-digital conversion result; the analog-to-digital conversion results each include a signal path identification (AMSEL [0:8 ]) and a result of converting an analog signal into a digital signal (SAR [0:11 ]). The second conduction signal comprises an internal analog channel identifier and an external channel identifier, the second conduction signal received by the first analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time, and the second conduction signal received by the second analog multiplexer comprises the internal analog channel identifier and the external analog channel identifier at the same time.

In some alternative embodiments, the apparatus may send the second on signal to the at least one analog multiplexer, respectively, to configure the at least one analog multiplexer, respectively. Specifically, the second conduction signal sent by the device to at least one analog multiplexer includes an internal analog channel identifier and an external analog channel identifier, where the internal analog channel identifier includes CH0, CH1 and CH2; the second conducting signal sent by the device to the analog multiplexer (analog multiplexer 1 in fig. 10) for controlling the external analog channel may only include the external analog channel identifier (optionally, the external analog channel identifiers of the external analog channels to be conducted in the two external chip modules are the same), and the part of the internal analog channel identifier, i.e., AMSEL [0:5], may be any character. In fig. 10, mux1.Ams_1, mux1.Ams_2, mux1.Ams_3 are external strobe signals. It should be noted that, 3 external strobe signals in the present disclosure are merely examples, and the external strobe signals may be any number greater than or equal to 1, which is not particularly limited in the present disclosure.

In this way, through the data processing method provided by the embodiment of the disclosure, firstly, through an external expansion interface, each analog-to-digital converter can expand a plurality of external analog channels and can realize that a plurality of analog-to-digital converters expand external analog channels simultaneously by combining an internal analog channel set corresponding to each analog-to-digital converter in the chip; secondly, through a trigger event and a pre-configured trigger event channel selection comparison table, analog channel identification, a first analog multiplexer and a second analog multiplexer corresponding to the trigger event can be automatically confirmed, and automatic continuous sampling of the analog-to-digital converter is realized; thirdly, the plurality of analog-to-digital converters expand external analog channels respectively, so that each analog-to-digital converter can be controlled independently, and synchronous sampling can be triggered simultaneously by the plurality of analog-to-digital converters; finally, the analog-to-digital conversion result comprises an external analog channel identifier, and has a vital role in screening signal sources during large data acquisition.

Fig. 11 is a schematic diagram showing an alternative configuration of a data processing apparatus provided in an embodiment of the present disclosure, and will be described in terms of the respective sections.

In some embodiments, the data processing apparatus 700 comprises an acknowledgement unit 701, a reception unit 702, and an analog-to-digital conversion unit 703.

The confirmation unit 701 is configured to confirm a simulation channel identifier based on a trigger event and a pre-configured trigger event channel selection comparison table, where the simulation channel identifier includes at least one internal simulation channel identifier;

the receiving unit 702 is configured to receive at least one analog signal based on an analog channel corresponding to the analog channel identifier;

the analog-to-digital conversion unit is used for performing analog-to-digital conversion on the at least one path of analog signals to obtain an analog-to-digital conversion result;

The confirmation unit 701 is specifically configured to confirm, from a plurality of analog multiplexers in the chip, an analog multiplexer and an analog channel identifier corresponding to the trigger event based on the trigger event and a pre-configured trigger event channel selection comparison table;

The analog multiplexer comprises at least one first analog multiplexer and at least one second analog multiplexer, the at least one first analog multiplexer corresponds to the chip-internal analog-to-digital converter one by one, the second analog multiplexer corresponds to the chip-external module, the chip-internal analog-to-digital converter corresponds to the at least one internal analog channel, and the chip-external module comprises at least one external analog channel.

In some embodiments, the internal analog channel identifier is used for characterizing channels for receiving the analog signals in a plurality of channels in the chip, the internal analog channel identifier includes at least six character strings composed of binary characters, and the character string corresponding to each channel for receiving the analog signals in the chip is different; the external analog channel identifier is used for representing a channel for receiving analog signals in a plurality of channels included in a module externally connected with the chip, the external analog channel identifier comprises at least three character strings composed of binary characters, and the character strings corresponding to each channel in the module for receiving the analog signals are different.

The confirmation unit 701 is specifically configured to confirm at least one internal analog channel identifier based on the trigger event and a pre-configured trigger event channel selection comparison table if the analog signal corresponding to the trigger event is received based on the internal analog channel of the chip.

The receiving unit 702 is configured to send a first on signal to at least one first analog multiplexer based on the trigger event, so that the at least one first analog multiplexer turns on at least one internal analog channel corresponding to an analog-to-digital converter corresponding to the first on signal based on the first on signal; an analog signal is received based on the at least one internal analog channel.

In some embodiments, the analog channel identifier further includes at least one external analog channel identifier, and the confirmation unit 701 is specifically configured to confirm at least one internal analog channel identifier and at least one external analog channel identifier based on the trigger event and a pre-configured trigger event channel selection lookup table if an analog signal corresponding to the trigger event is received based on an external analog channel of the chip.

The receiving unit 702 is specifically configured to send a second conducting signal to at least one first analog multiplexer and a second analog multiplexer based on the trigger event, so that the at least one first analog multiplexer conducts at least one internal analog channel corresponding to an analog-to-digital converter corresponding to the second conducting signal based on the second conducting signal, and the second analog multiplexer conducts at least one external analog channel included in an external chip module corresponding to the second conducting signal based on the second conducting signal;

An analog signal is received based on the at least one external analog channel and the at least one internal analog channel, wherein the number of the at least one internal analog channel is greater than or equal to the number of the at least one external analog channel.

In an embodiment of the disclosure, the chip includes at least one analog-to-digital converter (ADC), each corresponding to a first analog multiplexer, and a plurality of internal analog channels; each analog-to-digital converter receives an analog signal based on one or more internal analog channels in a plurality of corresponding analog channels, and the first analog multiplexer is used for conducting the internal analog channels in the plurality of analog channels and used for receiving the analog signal; optionally, the chip may be further externally connected to at least one module, where each of the externally connected modules includes a plurality of external analog channels; the chip can also comprise a second analog multiplexer which is used for conducting one or more external analog channels included in the external chip module. The analog signals are received based on the conducted external analog channel and the internal analog channel, transmitted to the analog-to-digital converter, and sampled by the analog-to-digital converter.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

Fig. 12 shows a schematic block diagram of an example electronic device 800 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 11, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM802, and the RAM803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in electronic device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 800 via the ROM802 and/or the communication unit 809. When a computer program is loaded into RAM803 and executed by computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data processing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of data processing, the method comprising:

2. The method of claim 1, wherein the validating the analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table comprises:

based on a trigger event and a pre-configured trigger event channel selection comparison table, confirming an analog multiplexer and an analog channel identifier corresponding to the trigger event from a plurality of analog multiplexers in a chip;

the analog multiplexer comprises a first analog multiplexer and a second analog multiplexer, the first analog multiplexer and the second analog multiplexer are in one-to-one correspondence with the chip internal analog-to-digital converter, the chip internal analog-to-digital converter corresponds to at least one internal analog channel, and the module externally connected with the chip comprises at least one external analog channel;

Or the analog multiplexer comprises at least one first analog multiplexer and at least one second analog multiplexer, the at least one first analog multiplexer corresponds to the chip-internal analog-to-digital converter one by one, the second analog multiplexer corresponds to the chip-external module, the chip-internal analog-to-digital converter corresponds to the at least one internal analog channel, and the chip-external module comprises at least one external analog channel.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

the internal analog channel identifier is used for representing channels for receiving the analog signals in a plurality of channels in the chip, the internal analog channel identifier comprises character strings composed of binary characters, and the character strings corresponding to each channel for receiving the analog signals in the chip are different;

the external analog channel identifier is used for representing a channel for receiving analog signals in a plurality of channels included in a module externally connected with the chip, the external analog channel identifier comprises character strings composed of binary characters, and the character strings corresponding to each channel for receiving the analog signals in the module are different.

4. The method of claim 3, wherein the validating the analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table comprises:

And if the analog signal corresponding to the trigger event is received based on the internal analog channel of the chip, confirming at least one internal analog channel identifier based on the trigger event and a pre-configured trigger event channel selection comparison table.

5. The method of claim 4, wherein receiving at least one analog signal based on the analog channel corresponding to the analog channel identifier comprises:

transmitting a first conduction signal to at least one analog multiplexer based on the trigger event, so that the at least one analog multiplexer conducts at least one internal analog channel corresponding to an analog-to-digital converter corresponding to the first conduction signal based on the first conduction signal;

an analog signal is received based on the at least one internal analog channel.

6. The method of claim 3, wherein the analog channel identification further comprises at least one external analog channel identification, wherein the validating the analog channel identification based on the trigger event and a pre-configured trigger event channel selection look-up table comprises:

and if the analog signal corresponding to the trigger event is received based on the external analog channel of the chip, confirming at least one internal analog channel identifier and at least one external analog channel identifier based on the trigger event and a pre-configured trigger event channel selection comparison table.

7. The method of claim 6, wherein the receiving at least one analog signal based on the analog channel corresponding to the analog channel identifier comprises:

transmitting a second conduction signal to at least one first analog multiplexer and a second analog multiplexer based on the trigger event, so that the at least one first analog multiplexer conducts at least one internal analog channel corresponding to an analog-to-digital converter corresponding to the second conduction signal based on the second conduction signal, and the second analog multiplexer conducts at least one external analog channel included in an external chip module corresponding to the second conduction signal based on the second conduction signal;

8. The method of claim 6, wherein the receiving at least one analog signal based on the analog channel corresponding to the analog channel identifier comprises:

transmitting a second conduction signal to at least one analog multiplexer based on the trigger event, so that the analog multiplexer conducts at least one internal analog channel and at least one external analog channel corresponding to an analog-to-digital converter corresponding to the second conduction signal based on the second conduction signal;

9. A data processing apparatus, the apparatus comprising:

10. An electronic device, comprising:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

11. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-8.