CN116073630A - Method, circuit and device for improving dynamic response speed of ultra-low power DCDC system - Google Patents

Method, circuit and device for improving dynamic response speed of ultra-low power DCDC system Download PDF

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Publication number
CN116073630A
CN116073630A CN202310209785.2A CN202310209785A CN116073630A CN 116073630 A CN116073630 A CN 116073630A CN 202310209785 A CN202310209785 A CN 202310209785A CN 116073630 A CN116073630 A CN 116073630A
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China
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error amplifier
threshold voltage
dynamic response
response speed
ultra
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甘戈
乐忠明
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Yutai Semiconductor Co ltd
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Yutai Semiconductor Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a method, a circuit and a device for improving the dynamic response speed of an ultra-low power DCDC system, wherein the method comprises the steps that an error amplifier gm collects output feedback voltage VFB; detecting whether the output feedback voltage VFB is smaller than a set minimum threshold voltage Vmin, and accelerating the output end voltage VC of the pull-up error amplifier gm when the output feedback voltage VFB is smaller than the set minimum threshold voltage Vmin; and/or detecting whether the output feedback voltage VFB is greater than the set maximum threshold voltage Vmax, and when the output feedback voltage VFB is greater than the set maximum threshold voltage Vmax, accelerating the pull-down of the output terminal voltage VC of the error amplifier gm. According to the invention, the two-way dynamic response speed of the DCDC system switched between light load and heavy load can be greatly improved through the two operational amplifiers and the two MOS switches; when the output feedback voltage VFB value is between Vmin and Vmax, the two MOS switches are not turned on, the control loop of the existing ultralow-power-consumption error amplifier gm is not influenced, the existing ultralow-power-consumption error amplifier gm can be maintained, and quick dynamic response can be realized.

Description

Method, circuit and device for improving dynamic response speed of ultra-low power DCDC system
Technical Field
The invention relates to the technical field of DCDC switching power supplies, in particular to a method, a circuit and a device for improving dynamic response speed of an ultra-low power consumption DCDC system.
Background
TWS (True Wireless Stereo) Bluetooth earphone, smart bracelet, smart watch and other portable and wearable electronic devices are becoming more popular, and meanwhile, the portable and smart electronic devices are becoming more portable and compact, and the corresponding capacity of the built-in battery is also lower, so that the working power consumption of circuits and chips arranged in the portable and wearable electronic devices is required to be low enough to maintain long standby and use time.
A simple method for minimizing the power consumption of the electronic equipment is to shut down a chip arranged in the electronic equipment, but the method greatly worsens the use experience, and causes the problems of long wakeup waiting time, incapability of monitoring external information in real time, incapability of displaying working states in real time and the like. Another possible solution is to keep the circuit in the electronic device in a standby state, but reduce the standby power consumption of the circuit itself, which is required to be sufficiently low when the DCDC system is used for the DCDC system while keeping the output voltage stable.
Currently, advanced DCDC systems have been able to reduce standby power consumption to 1uA, even 0.1uA, which is a tremendous advancement, but such low standby power consumption brings a new problem: the dynamic response speed is slow. As shown in fig. 1, which is a circuit structure diagram of a typical wearable electronic device, when a CPU module, a 5G module, etc. powered by DCDC needs to be quickly restored from a standby state to an active and full state, the output voltage of the DCDC may drop due to the failure of the DCDC to respond in time, and in an extreme case, system reset may be caused.
Fig. 2 shows a control loop of a typical DCDC system, in which an error amplifier gm is responsible for detecting the output feedback voltage VFB, amplifying the error between the output feedback voltage VFB and a reference voltage VREF, and performing Pulse Width Modulation (PWM) with a saw-tooth wave, and finally controlling the on duty ratio of the high-side transistor MOS switch MHi and the low-side transistor MOS switch MLo to regulate the power delivered to the output terminal, thereby forming a closed-loop stable output voltage Vout.
The DCDC system control mode shown in fig. 2 mentioned above is a PWM control mode, and is usually used in the case of heavy load; in the light load or even no load situation, in order to reduce the power consumption of the DCDC system, the DCDC system may operate in a PFM frequency conversion mode or a PSM frequency hopping mode, and the core of the PFM frequency conversion mode or the PSM frequency hopping mode is to reduce the operating frequency of the DCDC system. For the ultra-low power DCDC system of the sub-uA stage, simply reducing the operating frequency of the DCDC system itself is not enough to reach the target low standby power consumption level, and it is also necessary to shut down unnecessary circuit modules and reduce the power consumption of the necessary circuit modules such as the error amplifier gm.
Under the heavy load condition, the DCDC system works in a PWM control mode, the output end voltage VC (the voltage of a Vc node in fig. 2) of the error amplifier gm can be automatically modulated and stabilized to a certain stable value VC-PWM by the control loop, and the magnitude of the stable value VC-PWM can be changed according to different loads, but the magnitude can be between the intervals VC-PWM 0-VC-PWM 1. Under the light load condition, the DCDC system works in a PFM frequency conversion mode or a PSM frequency hopping mode, at the moment, the error amplifier gm is in an ultra-low power consumption state, the output end voltage VC is not controlled by a control loop any more, and if any Vc node is released, the value of VC can be 0V. When the light load is changed into heavy load, in order to provide enough power output for the output end in time, the output end voltage VC of the error amplifier gm is required to be adjusted to a stable value VC-PWM at the fastest speed, but as the capacitance value of the compensation capacitor Cc is generally tens of pF, the output current of gm with low power consumption is extremely small, a certain time is consumed for charging, the adjustment time of VC is further restricted, and the output voltage Vout of the DCDC system is obviously dropped when the light load is changed into heavy load.
In order to solve the problem, the voltage clamp can be performed on the Vc node, namely when the DCDC system is in the PFM frequency conversion mode or the PSM frequency hopping mode, the Vc is positioned on a clamp voltage Vc-clamp between the intervals Vc-PWM 0-Vc-PWM 1, so that when the heavy load arrives, the voltage amplitude that the Vc needs to be crossed is smaller, the time for adjusting the Vc to the stable value Vc-PWM is shorter, and the dynamic response speed is faster. However, this method has the following disadvantages: 1. it is difficult to manufacture a precise clamp voltage vc-clamp or more power consumption is required; 2. the arrival heavy load is different, the target stable value of VC is also different, and the VC cannot be in seamless connection with the clamping voltage VC-clamp.
Disclosure of Invention
In order to solve at least one of the technical problems, the invention provides a method, a circuit and a device for improving the dynamic response speed of an ultra-low power consumption DCDC system, which can improve the dynamic response speed on the basis of realizing the ultra-low power consumption of the DCDC system.
The first aspect of the present invention provides a method for improving the dynamic response speed of an ultra-low power DCDC system, comprising:
the error amplifier gm collects and outputs feedback voltage VFB;
detecting whether the output feedback voltage VFB is smaller than a set minimum threshold voltage Vmin, and accelerating the output end voltage VC of the pull-up error amplifier gm when the output feedback voltage VFB is smaller than the set minimum threshold voltage Vmin; and/or the number of the groups of groups,
and detecting whether the output feedback voltage VFB is larger than a set maximum threshold voltage Vmax, and accelerating the pull-down of the output end voltage VC of the error amplifier gm when the output feedback voltage VFB is larger than the set maximum threshold voltage Vmax.
Preferably, the first operational amplifier AMP1 has a positive input terminal connected to the output feedback voltage VFB and a negative input terminal connected to the minimum threshold voltage Vmin, so as to detect whether the output feedback voltage VFB collected by the error amplifier gm is smaller than the set minimum threshold voltage Vmin.
In any of the above schemes, preferably, the output terminal of the first operational amplifier AMP1 is connected to the gate of the first MOS switch M1, and the drain of the first MOS switch M1 is connected to the output terminal of the error amplifier gm, so as to control the first MOS switch M1 to be turned on when the output feedback voltage VFB collected by the detection error amplifier gm is smaller than the set minimum threshold voltage Vmin, thereby accelerating the pull-up of the output terminal voltage VC of the error amplifier gm.
In any of the above schemes, it is preferable that the second operational amplifier AMP2 has a positive input terminal connected to the output feedback voltage VFB and a negative input terminal connected to the maximum threshold voltage Vmax, so as to detect whether the output feedback voltage VFB collected by the error amplifier gm is greater than the set maximum threshold voltage Vmax.
In any of the above schemes, preferably, the output end of the second operational amplifier AMP2 is connected to the gate of the second MOS switch M2, and the drain of the second MOS switch M2 is connected to the output end of the error amplifier gm, so as to control the second MOS switch M2 to be turned on when the output feedback voltage VFB collected by the detection error amplifier gm is greater than the set maximum threshold voltage Vmax, thereby accelerating the pull-down of the output end voltage VC of the error amplifier gm.
In any of the above embodiments, preferably, the source of the first MOS switch M1 is connected to a supply voltage.
In any of the above embodiments, preferably, the source of the second MOS switch M2 is grounded.
In any of the above embodiments, it is preferable that the minimum threshold voltage Vmin has a value of VREF-Vd, and the maximum threshold voltage Vmax has a value of vref+vd, wherein VREF is a reference voltage of the error amplifier gm, and Vd is a constant.
In any of the above schemes, preferably, the positive input terminal of the error amplifier gm is connected to the reference voltage VREF, the negative input terminal is connected to the output feedback voltage VFB, the output terminal is further connected to the compensation resistor Rc and the compensation capacitor Cc in series, and the other end of the compensation capacitor Cc is grounded.
A second aspect of the present invention provides a circuit for improving a dynamic response speed of an ultra-low power DCDC system, comprising: the error amplifier gm further includes a first operational amplifier AMP1 and a first MOS switch M1, and/or a second operational amplifier AMP2 and a second MOS switch M2; the forward input end of the first operational amplifier AMP1 is connected with the output feedback voltage VFB, the reverse input end of the first operational amplifier AMP is connected with the minimum threshold voltage Vmin, the output end of the first operational amplifier AMP is connected with the grid electrode of the second MOS switch M2, and the drain electrode of the second MOS switch M2 is connected with the output end of the error amplifier gm; the positive input end of the second operational amplifier AMP2 is connected with the output feedback voltage VFB, the negative input end of the second operational amplifier AMP2 is connected with the maximum threshold voltage Vmax, the output end of the second operational amplifier AMP2 is connected with the gate of the second MOS switch M2, and the drain of the second operational amplifier AMP2 is connected with the output end of the error amplifier gm.
Preferably, the source of the first MOS switch M1 is connected to the supply voltage, and the source of the second MOS switch M2 is grounded.
In any of the above embodiments, it is preferable that the minimum threshold voltage Vmin has a value of VREF-Vd, and the maximum threshold voltage Vmax has a value of vref+vd, wherein VREF is a reference voltage of the error amplifier gm, and Vd is a constant.
In any of the above schemes, preferably, the positive input terminal of the error amplifier gm is connected to the reference voltage VREF, the negative input terminal is connected to the output feedback voltage VFB, the output terminal is further connected to the compensation resistor Rc and the compensation capacitor Cc in series, and the other end of the compensation capacitor Cc is grounded.
The third aspect of the invention provides a device for improving the dynamic response speed of an ultra-low power consumption DCDC system, which adopts the method for improving the dynamic response speed of the ultra-low power consumption DCDC system or comprises the circuit for improving the dynamic response speed of the ultra-low power consumption DCDC system.
The method, the circuit and the device for improving the dynamic response speed of the ultra-low power DCDC system have the following beneficial effects:
1. the two-way dynamic response speed of the DCDC system switched before light load and heavy load can be greatly improved through the two operational amplifiers and the two MOS switches, so that the DCDC system can adjust the output voltage to a required value more quickly;
2. when the output feedback voltage VFB value is between Vmin and Vmax, the two MOS switches are not turned on, the control loop of the existing ultralow-power-consumption error amplifier gm is not affected, the existing ultralow-power-consumption error amplifier gm can be maintained, and quick dynamic response can be realized under the condition that the compensation capacitance area is not increased.
Drawings
Fig. 1 is a schematic circuit diagram of a typical wearable electronic device.
Fig. 2 is a schematic diagram of a control loop of a typical DCDC system.
Fig. 3 is a flow chart of a preferred embodiment of a method for improving the dynamic response speed of an ultra-low power DCDC system according to the present invention.
Fig. 4 is a schematic structural diagram of a preferred embodiment of a circuit for improving the dynamic response speed of an ultra-low power DCDC system according to the present invention.
Fig. 5 is a comparison of the operational waveforms at load transitions before and after the circuit for improving the dynamic response speed of the ultra-low power DCDC system according to the present invention.
Fig. 6 shows the charge-discharge current contrast of the Vc node before and after the circuit for improving the dynamic response speed of the DCDC system with ultra-low power consumption according to the present invention.
Detailed Description
The invention will be described in more detail with reference to specific examples.
Examples
As shown in fig. 3, a method for improving the dynamic response speed of an ultra-low power DCDC system includes:
s1: the error amplifier gm collects and outputs feedback voltage VFB;
s2: detecting whether the output feedback voltage VFB is smaller than a set minimum threshold voltage Vmin, and accelerating the output end voltage VC of the pull-up error amplifier gm when the output feedback voltage VFB is smaller than the set minimum threshold voltage Vmin;
s3: and detecting whether the output feedback voltage VFB is larger than a set maximum threshold voltage Vmax, and accelerating the pull-down of the output end voltage VC of the error amplifier gm when the output feedback voltage VFB is larger than the set maximum threshold voltage Vmax.
As shown in fig. 4, a circuit for improving the dynamic response speed of an ultra-low power DCDC system includes: the error amplifier gm further includes a first operational amplifier AMP1 and a first MOS switch M1, a second operational amplifier AMP2 and a second MOS switch M2; the forward input end of the first operational amplifier AMP1 is connected with the output feedback voltage VFB, the reverse input end of the first operational amplifier AMP is connected with the minimum threshold voltage Vmin, the output end of the first operational amplifier AMP is connected with the grid electrode of the second MOS switch M2, and the drain electrode of the second MOS switch M2 is connected with the output end of the error amplifier gm; the positive input end of the second operational amplifier AMP2 is connected with the output feedback voltage VFB, the negative input end of the second operational amplifier AMP2 is connected with the maximum threshold voltage Vmax, the output end of the second operational amplifier AMP2 is connected with the gate of the second MOS switch M2, and the drain of the second operational amplifier AMP2 is connected with the output end of the error amplifier gm. The source electrode of the first MOS switch M1 is connected with a supply voltage, and the source electrode of the second MOS switch M2 is grounded; the value of the minimum threshold voltage Vmin is VREF-Vd, the value of the maximum threshold voltage Vmax is VREF+Vd, wherein VREF is the reference voltage of the error amplifier gm, and Vd is a constant; the positive input end of the error amplifier gm is connected with the reference voltage VREF, the negative input end of the error amplifier gm is connected with the output feedback voltage VFB, the output end of the error amplifier gm is also sequentially connected with a compensation resistor Rc and a compensation capacitor Cc which are connected in series, and the other end of the compensation capacitor Cc is grounded.
The method for improving the dynamic response speed of the ultra-low power consumption DCDC system can be realized by the circuit for improving the dynamic response speed of the ultra-low power consumption DCDC system.
In step S2, the first operational amplifier AMP1 has a forward input terminal connected to the output feedback voltage VFB and a reverse input terminal connected to the minimum threshold voltage Vmin, so as to detect whether the output feedback voltage VFB collected by the error amplifier gm is smaller than the set minimum threshold voltage Vmin; the output end of the first operational amplifier AMP1 is connected to the gate of the first MOS switch M1, and the drain of the first MOS switch M1 is connected to the output end of the error amplifier gm, so as to control the first MOS switch M1 to be turned on when the output feedback voltage VFB collected by the detection error amplifier gm is smaller than the set minimum threshold voltage Vmin, thereby accelerating the voltage VC of the output end of the error amplifier gm.
In step S3, the second operational amplifier AMP2 has a forward input terminal connected to the output feedback voltage VFB and a reverse input terminal connected to the maximum threshold voltage Vmax, so as to detect whether the output feedback voltage VFB collected by the error amplifier gm is greater than the set maximum threshold voltage Vmax; the output end of the second operational amplifier AMP2 is connected to the gate of the second MOS switch M2, and the drain of the second MOS switch M2 is connected to the output end of the error amplifier gm, so as to control the second MOS switch M2 to be turned on when the output feedback voltage VFB collected by the detection error amplifier gm is greater than the set maximum threshold voltage Vmax, thereby accelerating the pull-down of the output end voltage VC of the error amplifier gm.
Specifically, the circuit for improving the dynamic response speed of the ultra-low power DCDC system increases the AMP1\M1 and the AMP2\M2 on the basis of the original error amplifier gm and the complementary network Rc/Cc. AMP1 is responsible for detecting whether the output feedback voltage VFB collected by the error amplifier gm is less than a set minimum threshold voltage Vmin, that is, VREF-Vd, and if so, AMP1 acts and turns on M1 to accelerate VC build-up in the heavy load direction, thereby more quickly adjusting the PWM duty cycle and pulling the output voltage back to the target value. Similarly, AMP2 is responsible for detecting whether the output feedback voltage VFB collected by the error amplifier gm is greater than the set maximum threshold voltage Vmax, that is, vref+vd, and if so, accelerating VC to build up in the light load direction, thereby timely reducing the output power and avoiding further overshoot of the output voltage. When the output feedback voltage VFB collected by the error amplifier gm is between VREF-Vd and VREF+Vd, neither M1 nor M2 will be turned on, so that the slower gm loop operation is not affected. Therefore, the gm with ultra-low power consumption can be maintained, and quick dynamic response can be realized without increasing the cost of compensating the network area.
Fig. 5 shows comparison of working waveforms before and after the circuit for improving the dynamic response speed of the ultra-low power DCDC system is adopted, wherein a solid line is the working waveform before the circuit is adopted, and a dotted line is the working waveform after the circuit is adopted. At the rising edge of the output load Iout, the instantaneous step of light load is heavy load, the output voltage Vout starts to drop, gm responds independently before Vout reaches Vout-Vod, and VC is pulled up slowly; once Vout touches Vout-Vod, AMP1 participates in the response, starting to pull up VC quickly; since the bitline trend of the inductor current Isw (i.e. the current flowing through the inductor L in fig. 2) follows VC, the faster the VC rises, the faster the Isw rises, i.e. the more timely the current required by the load is complemented, and Vout is prevented from dropping further. Similarly, at the falling edge of the output load Iout, the instantaneous step of heavy load is light load, the output voltage Vout starts to be up-rushed, gm is independently responded before Vout reaches Vout+Vod, and VC is pulled down slowly; once Vout touches vout+vod, AMP2 participates in the response, starting to pull VC low quickly; because the bitline trend in the inductive current Isw follows VC, the faster the VC is reduced, the faster the Isw is reduced, namely, the more timely the unnecessary energy for load removal is eliminated, and the further up-rushing of Vout is avoided. It can be seen that the response speed of the dotted line is significantly faster than that of the solid line, and that the ripple of the output voltage Vout falling and overshooting is smaller.
Fig. 6 shows the charge-discharge current contrast of the Vc node before and after the circuit for improving the dynamic response speed of the DCDC system with ultra-low power consumption, wherein the output capability of the low power consumption gm is implemented, and the dashed lines are the output capabilities of AMP1 and AMP 2. The VFB-VREF is within the range of +/-Vd, gm is independently responded, the advantage of gm low power consumption is fully exerted in a steady state, and a large-area compensation capacitor is not needed to be adopted to maintain the constant bandwidth gm/Cc; VFB-VREF is out of the range of + -Vd, AMP1 and AMP2 intervene, so that the charge-discharge current of Vc nodes is greatly increased to respond to the jump of the load in time.
It should be noted that, the value of Vd depends on two factors, namely, the degree of dynamic response is to be improved, if the value of Vd is infinite, the circuit has no improvement effect on the dynamic response speed of the DCDC system; secondly, frequent participation of the AMP 1/M1 and the AMP 2/M2 in inherent loop regulation of the DCDC system should be avoided, and if the Vd value is infinitesimal, the circuit is always in a working state, and the power consumption and the stability of the DCDC system are deteriorated. When the DCDC system is not added with the circuit, 1) the maximum value of falling and overshoot which can be achieved by the output feedback voltage VFB is Vdmax, 2) the output ripple value of the DCDC system in the steady-state operation in the full load range is Vdmin, and Vdmin is not less than Vd and not more than Vdmax.
It should be further noted that, there is a k-time proportional relationship between the output feedback voltage VFB and the output voltage Vout, k is a resistor voltage division coefficient, vd is based on VFB, and Vod is based on Vout, so that Vd and Vod also have a k-time proportional relationship.
Examples
Unlike embodiment 1, the method includes only step S1 and step S2, and accordingly, the circuit includes only the error amplifier gm, the first operational amplifier AMP1, and the first MOS switch M1. The method and the circuit of the embodiment can only improve the dynamic response speed of the DCDC system when the DCDC system is stepped from light load to heavy load.
Examples
Unlike embodiment 1, the method includes only step S1 and step S3, and accordingly, the circuit includes only the error amplifier gm, the second operational amplifier AMP2, and the second MOS switch M2. The method and the circuit of the embodiment can only improve the dynamic response speed of the DCDC system when the DCDC system is stepped from heavy load to light load.
Examples
The device for improving the dynamic response speed of the ultra-low power consumption DCDC system adopts the method for improving the dynamic response speed of the ultra-low power consumption DCDC system or comprises the circuit for improving the dynamic response speed of the ultra-low power consumption DCDC system.
Examples
Unlike the foregoing embodiment, in the present embodiment, the error amplifier gm captures the output feedback voltage VFB by the circuit configuration shown in fig. 2, and pulse width modulation PWM is performed using the circuit configuration shown in fig. 2.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; while the foregoing embodiments are illustrative of the present invention in detail, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents, which do not depart from the scope of the technical scheme of the present invention.

Claims (10)

1. A method for improving dynamic response speed of an ultra-low power DCDC system comprises the following steps: the error amplifier gm collects and outputs feedback voltage VFB; characterized by further comprising:
detecting whether the output feedback voltage VFB is smaller than a set minimum threshold voltage Vmin, and accelerating the output end voltage VC of the pull-up error amplifier gm when the output feedback voltage VFB is smaller than the set minimum threshold voltage Vmin; and/or the number of the groups of groups,
and detecting whether the output feedback voltage VFB is larger than a set maximum threshold voltage Vmax, and accelerating the pull-down of the output end voltage VC of the error amplifier gm when the output feedback voltage VFB is larger than the set maximum threshold voltage Vmax.
2. The method for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 1, wherein: the forward input end of the first operational amplifier AMP1 is connected with the output feedback voltage VFB, the reverse input end of the first operational amplifier AMP is connected with the minimum threshold voltage Vmin, and whether the output feedback voltage VFB collected by the error amplifier gm is smaller than the set minimum threshold voltage Vmin or not is detected; the output end of the first operational amplifier AMP1 is connected to the gate of the first MOS switch M1, and the drain of the first MOS switch M1 is connected to the output end of the error amplifier gm, so as to control the first MOS switch M1 to be turned on when the output feedback voltage VFB collected by the detection error amplifier gm is smaller than the set minimum threshold voltage Vmin, thereby accelerating the voltage VC of the output end of the error amplifier gm.
3. The method for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 1, wherein: the positive input end of the second operational amplifier AMP2 is connected with the output feedback voltage VFB, the negative input end is connected with the maximum threshold voltage Vmax, and whether the output feedback voltage VFB collected by the error amplifier gm is larger than the set maximum threshold voltage Vmax or not is detected; the output end of the second operational amplifier AMP2 is connected to the gate of the second MOS switch M2, and the drain of the second MOS switch M2 is connected to the output end of the error amplifier gm, so as to control the second MOS switch M2 to be turned on when the output feedback voltage VFB collected by the detection error amplifier gm is greater than the set maximum threshold voltage Vmax, thereby accelerating the pull-down of the output end voltage VC of the error amplifier gm.
4. The method for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 1, wherein: the minimum threshold voltage Vmin has a value of VREF-Vd, the maximum threshold voltage Vmax has a value of VREF+Vd, VREF is the reference voltage of the error amplifier gm, and Vd is a constant.
5. The method for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 1, wherein: the positive input end of the error amplifier gm is connected with the reference voltage VREF, the negative input end of the error amplifier gm is connected with the output feedback voltage VFB, the output end of the error amplifier gm is also sequentially connected with a compensation resistor Rc and a compensation capacitor Cc which are connected in series, and the other end of the compensation capacitor Cc is grounded.
6. A circuit for improving the dynamic response speed of an ultra-low power DCDC system, comprising: error amplifier gm, its characterized in that: further comprising a first operational amplifier AMP1 and a first MOS switch M1, and/or a second operational amplifier AMP2 and a second MOS switch M2; the forward input end of the first operational amplifier AMP1 is connected with the output feedback voltage VFB, the reverse input end of the first operational amplifier AMP is connected with the minimum threshold voltage Vmin, the output end of the first operational amplifier AMP is connected with the grid electrode of the second MOS switch M2, and the drain electrode of the second MOS switch M2 is connected with the output end of the error amplifier gm; the positive input end of the second operational amplifier AMP2 is connected with the output feedback voltage VFB, the negative input end of the second operational amplifier AMP2 is connected with the maximum threshold voltage Vmax, the output end of the second operational amplifier AMP2 is connected with the gate of the second MOS switch M2, and the drain of the second operational amplifier AMP2 is connected with the output end of the error amplifier gm.
7. The circuit for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 6, wherein: the source electrode of the first MOS switch M1 is connected with the power supply voltage, and the source electrode of the second MOS switch M2 is grounded.
8. The circuit for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 6, wherein: the minimum threshold voltage Vmin has a value of VREF-Vd, the maximum threshold voltage Vmax has a value of VREF+Vd, VREF is the reference voltage of the error amplifier gm, and Vd is a constant.
9. The circuit for improving the dynamic response speed of the ultra-low power consumption DCDC system according to claim 6, wherein: the positive input end of the error amplifier gm is connected with the reference voltage VREF, the negative input end of the error amplifier gm is connected with the output feedback voltage VFB, the output end of the error amplifier gm is also sequentially connected with a compensation resistor Rc and a compensation capacitor Cc which are connected in series, and the other end of the compensation capacitor Cc is grounded.
10. The utility model provides a device for improving ultra-low power consumption DCDC system dynamic response speed which characterized in that: a method for improving the dynamic response speed of an ultra-low power consumption DCDC system according to any one of claims 1 to 5, or a circuit for improving the dynamic response speed of an ultra-low power consumption DCDC system according to any one of claims 6 to 9.
CN202310209785.2A 2023-03-07 2023-03-07 Method, circuit and device for improving dynamic response speed of ultra-low power DCDC system Pending CN116073630A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548453A (en) * 1992-10-30 1996-08-20 Sony Corporation Reproducing circuit for magneto-resistive head having an initial amplifying stage, a differential amplifying stage, and means for controlling the time of operation thereof
CN103268134A (en) * 2013-06-03 2013-08-28 上海宏力半导体制造有限公司 Low-dropout voltage adjuster capable of improving transient response
CN104377958A (en) * 2014-11-27 2015-02-25 电子科技大学 Transient response intensifier circuit for switching power supply
CN113595385A (en) * 2020-04-30 2021-11-02 圣邦微电子（北京）股份有限公司 Circuit for improving transient response speed in DCDC
CN115603569A (en) * 2021-07-08 2023-01-13 圣邦微电子（北京）股份有限公司（Cn） Switch converter and control circuit thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548453A (en) * 1992-10-30 1996-08-20 Sony Corporation Reproducing circuit for magneto-resistive head having an initial amplifying stage, a differential amplifying stage, and means for controlling the time of operation thereof
CN103268134A (en) * 2013-06-03 2013-08-28 上海宏力半导体制造有限公司 Low-dropout voltage adjuster capable of improving transient response
CN104377958A (en) * 2014-11-27 2015-02-25 电子科技大学 Transient response intensifier circuit for switching power supply
CN113595385A (en) * 2020-04-30 2021-11-02 圣邦微电子（北京）股份有限公司 Circuit for improving transient response speed in DCDC
CN115603569A (en) * 2021-07-08 2023-01-13 圣邦微电子（北京）股份有限公司（Cn） Switch converter and control circuit thereof

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Application publication date: 20230505