CN116072552A - Wafer level packaging structure and packaging method - Google Patents

Wafer level packaging structure and packaging method Download PDF

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Publication number
CN116072552A
CN116072552A CN202111239938.5A CN202111239938A CN116072552A CN 116072552 A CN116072552 A CN 116072552A CN 202111239938 A CN202111239938 A CN 202111239938A CN 116072552 A CN116072552 A CN 116072552A
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China
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layer
dielectric layer
bonding
semiconductor
pad
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CN202111239938.5A
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强力
张京晶
赵娅俊
槐宝
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202111239938.5A priority Critical patent/CN116072552A/en
Publication of CN116072552A publication Critical patent/CN116072552A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The application provides a wafer level packaging structure and a packaging method, wherein the structure comprises the following steps: the semiconductor adapter plate is provided with a first bonding welding pad on the first surface; the packaging chips are arranged according to design requirements and are positioned on the first surface of the semiconductor adapter plate, and a top layer welding pad is arranged on one surface, close to the semiconductor adapter plate, of each packaging chip; the second bonding welding pad is electrically connected with the top layer welding pad through a first interlayer metal connection wire, and the first bonding welding pad corresponds to the second bonding welding pad; the semiconductor adapter plate and the packaging chips are bonded with the first bonding pads through the second bonding pads; and the injection molding layer is positioned among the plurality of packaging chips. The wafer level packaging structure and the packaging method can simplify the process of the semiconductor adapter plate, reduce the overall warpage of packaging, improve the packaging lead density of chips and improve the performance of the chips.

Description

Wafer level packaging structure and packaging method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a wafer level package structure and a packaging method.
Background
With the continuous development of applications such as 5G, artificial intelligence and sensors, chips integrated with multiple functions often need to be packaged together for effective integration. Therefore, wafer level packaging technology is emerging in the field of chip packaging. In the wafer level packaging technology, different chips are connected and packaged together through a silicon interposer (Si interposer) and solder bumps (bump, u-bump).
At present, the system level package of a packaging factory can only realize the electric connection among the chips on a relatively basic basis due to the limitation of a bulb process. With the rapid development of chip (chip) technology nowadays, the requirements for electrical connection of various chips are increasing, and the requirements and complexity of packaging are increasing, so that the development of packaging modes meeting the requirements of the present day is required. The chip foundry has the advantages of uniformly coordinating advanced packaging and chip manufacturing, adjusting device characteristics and the like due to higher process precision, and has more opportunities in wafer level 3D packaging.
However, currently, for the connection between chips, the connection between the chip and the silicon interposer mainly adopts the bump technology. But the bulb technology mainly has the following problems: the process nodes of the bulb are larger, the bulb is often in the order of tens of micrometers, and the latest u-bulb technology also has the order of micrometers, so that the number of I/Os of the chip is limited, and the improvement of the performance of the chip is not facilitated; because the number of the bulb of the silicon adapter plate and the chip is obviously higher than that of the bulb of the silicon adapter plate and the PCB below, the whole package has larger warpage, and the yield is affected. Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The wafer level packaging structure and the packaging method can simplify the process of the semiconductor adapter plate, reduce the overall warpage of packaging, improve the packaging lead density of chips and improve the chip performance.
One aspect of the present application provides a wafer level packaging method, including: providing a third carrier wafer, wherein a plurality of chips to be packaged which are arranged according to design requirements are assembled on the third carrier wafer, a first protection layer is formed on the surface of the chips to be packaged, which is far away from the third carrier wafer, and a top layer welding pad is formed under the first protection layer; forming an injection molding layer on the surface of the third carrier wafer and the surface of the first protection layer, and then grinding the injection molding layer and the first protection layer until the top layer welding pad is exposed; forming a second bonding pad above the top layer bonding pad, wherein the second bonding pad is electrically connected with the top layer bonding pad through a first interlayer metal wire; providing a semiconductor adapter plate, wherein a first bonding welding pad is formed on the first surface of the semiconductor adapter plate, and the first bonding welding pad corresponds to the second bonding welding pad; aligning and bonding the first bonding pad and the second bonding pad; and removing the third carrier wafer, and plastic packaging the chip to be packaged.
In some embodiments of the present application, the second side of the semiconductor interposer includes solder bumps and a second carrier wafer connected by the solder bumps and carrying the semiconductor interposer, and the packaging method further includes: removing the second carrier wafer and exposing the solder bumps; the weld stud is welded to the substrate.
In some embodiments of the present application, the substrate comprises any one of a printed wiring board, a copper-clad board, or a flexible circuit board.
In some embodiments of the present application, a method of forming the semiconductor interposer includes: providing a semiconductor substrate, a composite dielectric layer positioned on a first surface of the semiconductor substrate and a through silicon via, wherein one part of the through silicon via is positioned in the semiconductor substrate, the other part of the through silicon via extends into the composite dielectric layer, and a plurality of layers of metal interconnection structures are formed in the composite dielectric layer and electrically connected with an active device formed in the semiconductor substrate and the through silicon via; forming a second protective layer covering the surface of the metal interconnection structure and the surface of the composite dielectric layer; bonding the second protective layer with the first carrier wafer; thinning the second surface of the semiconductor substrate to enable the through silicon via to protrude out of the second surface of the semiconductor substrate; forming a third dielectric layer on the second surface of the semiconductor substrate, wherein the surface of the third dielectric layer is coplanar with the surface of the through silicon via; forming a third protective layer on the third dielectric layer, and forming a welding bump directly and electrically connected with the through silicon via on the through silicon via; electrically connecting the semiconductor substrate and the second carrier wafer through the solder bumps; removing the first carrier wafer; and forming a first bonding pad electrically connected with the metal interconnection structure above the second protection layer.
In some embodiments of the present application, a method of forming the first bonding pad includes: thinning the second protective layer and forming a fourth dielectric layer on the surface of the second protective layer; forming a second groove and a second through hole which is communicated with the bottom of the second groove and penetrates through the second protective layer to expose the metal interconnection structure in the fourth dielectric layer; and filling metal materials in the second through holes to form second interlayer metal connection lines, and filling metal materials in the second grooves to form first bonding pads.
In some embodiments of the present application, the method of bonding the second protective layer to the first carrier wafer is bonding the second protective layer to the first carrier wafer using a temporary bonding glue.
In some embodiments of the present application, a method of thinning a second side of the semiconductor substrate such that the through silicon via protrudes from the second surface of the semiconductor substrate includes: polishing the second surface of the semiconductor substrate using a chemical mechanical polishing process to expose the through silicon via; and etching the second surface of the semiconductor substrate to the second surface of the through silicon via protruding out of the semiconductor substrate by using an etching process.
In some embodiments of the present application, the method of removing the first carrier wafer, removing the second carrier wafer, and removing the third carrier wafer respectively includes: laser dissociation or mechanical dissociation.
In some embodiments of the present application, a method for forming a second bonding pad on the top layer pad, the second bonding pad being electrically connected to the top layer pad through a first interlayer metal wire includes: forming an interlayer dielectric layer on the surface of the top layer welding pad; forming a first groove and a first through hole which is communicated with the bottom of the first groove and penetrates through the interlayer dielectric layer to expose the top layer welding pad in the interlayer dielectric layer; and filling metal materials in the first through holes to form the first interlayer metal connection lines, and filling metal materials in the first grooves to form second bonding pads.
Another aspect of the present application also provides a wafer level package structure, including: the semiconductor adapter plate is provided with a first bonding welding pad on the first surface; the packaging chips are arranged according to design requirements and are positioned on the first surface of the semiconductor adapter plate, and a top layer welding pad is arranged on one surface, close to the semiconductor adapter plate, of each packaging chip; the second bonding welding pad is electrically connected with the top layer welding pad through a first interlayer metal connection wire, and the first bonding welding pad corresponds to the second bonding welding pad; the semiconductor adapter plate and the packaging chips are bonded with the first bonding pads through the second bonding pads; and the injection molding layer is positioned among the plurality of packaging chips.
In some embodiments of the present application, the second side of the semiconductor interposer includes solder bumps and a substrate connected to and carrying the semiconductor interposer by the solder bumps.
In some embodiments of the present application, the substrate comprises any one of a printed wiring board, a copper-clad board, or a flexible circuit board.
In some embodiments of the present application, the semiconductor interposer includes: the semiconductor device comprises a semiconductor substrate, a composite dielectric layer positioned on a first surface of the semiconductor substrate and a through silicon via, wherein one part of the through silicon via is positioned in the semiconductor substrate, the other part of the through silicon via extends into the composite dielectric layer, a plurality of layers of metal interconnection structures are further formed in the composite dielectric layer, and the metal interconnection structures are electrically connected with an active device formed in the semiconductor substrate and the through silicon via; the second protective layer covers the surface of the metal interconnection structure and the surface of the composite dielectric layer; the first bonding pad is positioned on the second protection layer and is electrically connected with the metal interconnection structure; the third dielectric layer is positioned on the second surface of the semiconductor substrate, and the surface of the third dielectric layer is coplanar with the surface of the through silicon via; and the third protection layer is positioned on the surface of the third dielectric layer, and welding salient points which are directly and electrically connected with the silicon through holes are arranged in the third protection layer.
In some embodiments of the present application, a fourth dielectric layer is disposed on the surface of the second protective layer, and the fourth dielectric layer is provided with the first bonding pad and a second interlayer metal connection line located below the first bonding pad and electrically connecting the first bonding pad and the metal interconnection structure.
In some embodiments of the present application, an interlayer dielectric layer is disposed on the surface of the top layer bonding pad, and the interlayer dielectric layer is provided with the second bonding pad and a first interlayer metal wire located above the second bonding pad and electrically connecting the second bonding pad and the top layer bonding pad.
The wafer level packaging structure and the packaging method have the advantages that the chip and the semiconductor adapter plate are bonded through the first bonding pad and the second bonding pad, the technical feature size of packaging can be improved, the chip and the semiconductor adapter plate are communicated at high density, the performance of the chip is improved, and parasitic resistance between the chip and the semiconductor adapter plate is reduced; the semiconductor adapter plate and the chip are connected without welding convex points, so that the process of the semiconductor adapter plate can be simplified, the whole package warpage is reduced, and the packaging lead density of the chip is improved.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 to 21 are schematic structural diagrams illustrating steps in a wafer level packaging method according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
Fig. 1 to 21 are schematic structural diagrams illustrating steps in a wafer level packaging method according to an embodiment of the present application. The wafer level packaging method according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a third carrier wafer 300 is provided, a plurality of chips 310 to be packaged arranged according to design requirements are assembled on the third carrier wafer 300, a first protection layer 340 is formed on a surface of the chips 310 to be packaged away from the third carrier wafer 300, and a top layer bonding pad 330 is formed under the first protection layer 340.
The third carrier wafer 300 may be a semiconductor wafer (e.g., a silicon wafer) or a glass wafer, etc. The third carrier wafer 300 is used for fixing and carrying the plurality of chips 310 to be packaged.
In the wafer level packaging process, chips integrated with a plurality of functions need to be packaged together for effective integration. Referring to fig. 1, the chips 310 to be packaged are chips having different functions, such as logic chips, memory chips, etc. The plurality of chips 310 to be packaged are arranged and mounted on the third carrier wafer 300 according to design requirements. The design requirement refers to that the chips 310 to be packaged are not arranged in a fixed manner, but are designed in a targeted manner according to the requirement of the customer.
It should be noted that, for the sake of brevity, only two chips 310 to be packaged are shown in fig. 1, but it should be understood that the number of chips 310 to be packaged is not limited, and the number may be greater.
With continued reference to fig. 1, the plurality of chips 310 to be packaged are mounted on the third carrier wafer in the following manner: the chips 310 to be packaged are adhered to the third wafer by an adhesive 301. Specifically, the adhesive 301 is coated on the third carrier wafer 300, and then the chips 310 to be packaged are adhered to the adhesive 301 according to a designed arrangement mode. The third carrier wafer 300 is only used to temporarily carry the plurality of chips 310 to be packaged for processing. Therefore, the third carrier wafer 300 and the chips 310 to be packaged need to be easily separated in the subsequent process. The third carrier wafer 300 may be removed in a subsequent process by adhering the plurality of chips 310 to be packaged to the third carrier wafer 300 through the adhesive 301.
With continued reference to fig. 1, top-layer bonding pads 330 are formed on the surfaces of the chips 310 to be packaged, and the top-layer bonding pads 330 are formed in the top-layer dielectric layer 320. The top-level bonding pad 330 is used to electrically connect active devices (not shown in the figure) in the plurality of chips 310 to be packaged. The material of the top dielectric layer 320 includes a dielectric material such as silicon oxide or silicon nitride. The top bonding pad 330 is made of a metal material such as copper or aluminum.
The top dielectric layer 320 and the top pad 330 are further formed with a first protective layer 340. The first protection layer 340 is used to protect the top bonding pad 330 from being damaged in the subsequent process. The material of the first protection layer 340 is, for example, silicon nitride.
Referring to fig. 2, an injection molding layer 350 is formed on the surface of the third carrier wafer 300 and the surface of the first protection layer 330. The method of forming the injection layer 350 is, for example, an injection molding process. The material of the injection molding layer 350 is, for example, epoxy resin or the like. The injection molding layer 350 is used for further fixing and molding the plurality of chips 310 to be packaged and filling the gaps between the plurality of chips 310 to be packaged.
The first protection layer 340 may protect the top dielectric layer 320 and the top pad 330 from damage during the injection molding process.
Referring to fig. 3, the injection molding layer 350 and the first protective layer 340 are then polished until the top layer pad 330 is exposed. The method of polishing the injection molding layer 350 and the first protection layer 340 is, for example, a chemical mechanical polishing process.
Referring to fig. 4 to 6, a second bonding pad 380 is formed over the top layer pad 330, the second bonding pad 380 being electrically connected to the top layer pad 330 through a first interlayer metal connection 370.
Referring to fig. 4, an interlayer dielectric layer 360 is formed on the surface of the top pad 330. The material of the interlayer dielectric layer 360 includes a dielectric material such as silicon oxide or silicon nitride. The method of forming the interlayer dielectric layer 360 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 5, a first trench 361 and a first via 362 communicating with the bottom of the first trench 361 and penetrating the interlayer dielectric layer 360 to expose the top layer pad 330 are formed in the interlayer dielectric layer 360.
In some embodiments of the present application, the method for forming the first trench 361 and the first via 362 is, for example: etching a first groove 361 on the surface of the interlayer dielectric layer 360; the first via 362 is etched at the bottom of the first trench 361. The etching may be a conventional photolithography process, and will not be described herein.
Referring to fig. 6, the first via 362 is filled with a metal material to form the first interlayer metal line 370, and the first trench 361 is filled with a metal material to form the second bonding pad 380. The steps of forming the first interlayer metal line 370 and forming the second bonding pad 380 may be synchronized.
Referring to fig. 18, a semiconductor interposer 200 is provided, and a first surface of the semiconductor interposer 200 is formed with first bonding pads 194, and the first bonding pads 194 correspond to the second bonding pads 380. The correspondence refers to the number and positions of the first bonding pads 194 and the second bonding pads 380. A method of forming the semiconductor interposer 200 is described in detail below with reference to fig. 7 through 18.
Referring to fig. 7, a semiconductor substrate 100, a composite dielectric layer 110 on a first surface of the semiconductor substrate 100, and a through silicon via 120 are provided, wherein a part of the through silicon via 120 is located in the semiconductor substrate 100, another part extends into the composite dielectric layer 110, a plurality of metal interconnection structures 130 are further formed in the composite dielectric layer 110, and the metal interconnection structures 130 electrically connect active devices formed in the semiconductor substrate 100 and the through silicon via 120.
In some embodiments of the present application, the semiconductor substrate 100 is, for example, a silicon substrate.
With continued reference to fig. 7, the composite dielectric layer 110 includes a first dielectric layer 111 and a second dielectric layer 112. For the sake of brevity, only two composite dielectric layers are exemplified in fig. 7. It should be understood that the composite dielectric layer 110 may also include more dielectric layers.
With continued reference to fig. 7, the first dielectric layer 111 may include a plurality of silicon nitride layers and silicon oxide layers (not shown) stacked in sequence. The through silicon via 120 extends into the first dielectric layer 111 and penetrates through the first dielectric layer 111. The second dielectric layer 112 may include a plurality of silicon nitride layers and silicon oxide layers stacked in sequence. The second dielectric layer 112 has a plurality of metal interconnect structures 130 formed therein. The metal interconnect structures 130 electrically connect the through silicon vias 120 and active devices formed in the semiconductor substrate 100, respectively.
The active devices include, for example, capacitive devices, logic devices, and the like. The embodiments of the present application use capacitive devices as examples only. Referring to fig. 7, the plurality of metal interconnect structures 130 further electrically connect active device capacitor devices 140 formed in the semiconductor substrate 100. The capacitive device 140 includes a first dielectric layer 141, an insulating layer 142, a second dielectric layer 143, and a contact structure 144 electrically connecting the first dielectric layer 141 and the second dielectric layer 143, respectively.
Referring to fig. 8, a second protective layer 101 is formed to cover the surface of the metal interconnection structure 130 and the surface of the composite dielectric layer 110. The second protection layer 101 is used to protect the metal interconnection structure 130 and the composite dielectric layer 110 in a subsequent process.
In some embodiments of the present application, the method of forming the second protection layer 101 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The material of the second protection layer 101 is, for example, silicon nitride.
Referring to fig. 9, the second protective layer 101 is bonded to the first carrier wafer 150. The first carrier wafer 150 may be a semiconductor wafer (e.g., a silicon wafer) or a glass wafer, etc. The first carrier wafer 150 is used for fixing and carrying the semiconductor substrate 100 and structures on the semiconductor substrate 100.
With continued reference to fig. 9, the method for bonding the second protection layer 101 to the first carrier wafer 150 includes: the second protective layer 101 is bonded to the first carrier wafer 150 using a temporary bonding glue 151.
In some embodiments of the present application, the temporary bonding glue 151 is, for example, a Brewer Science T1107 glue.
Referring to fig. 10 and 11, the second surface of the semiconductor substrate 100 is thinned such that the through silicon vias 120 protrude from the second surface of the semiconductor substrate 100. It should be noted that, for the sake of brevity, the reference numerals on the capacitor structure 140 are omitted in the following figures. It should be appreciated that the detailed structure of the capacitive structure 140 may be known in conjunction with the previous figures 7-9.
Referring to fig. 10, the second surface of the semiconductor substrate 100 is polished using a chemical mechanical polishing process until the through silicon vias 120 are exposed. Referring to fig. 11, the second surface of the semiconductor substrate 100 is etched using an etching process to the through silicon vias 120 protruding from the second surface of the semiconductor substrate 100.
Referring to fig. 12, a third dielectric layer 113 is formed on the second surface of the semiconductor substrate 100, and the surface of the third dielectric layer 113 is coplanar with the surface of the through silicon via 120.
In some embodiments of the present application, the method for forming the third dielectric layer 113 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The third dielectric layer 113 may include a silicon nitride layer and a silicon oxide layer formed in sequence.
Referring to fig. 13, a third protective layer 160 is formed on the third dielectric layer 113, and a solder bump 170 directly electrically connected to the through silicon via 120 is formed on the through silicon via 120. The solder bump 170 includes a solder ball 172 and a pad 171 surrounding the solder ball 172. The process of forming the solder bump 170 is a conventional solder bump process (bump process), and will not be described herein.
Referring to fig. 14, the semiconductor substrate 100 and the second carrier wafer 180 are electrically connected by the solder bumps 170. The second carrier wafer 180 may be a semiconductor wafer (e.g., a silicon wafer) or a glass wafer, etc. The second carrier wafer 180 is used to fix and carry the semiconductor substrate 100 and structures on the semiconductor substrate 100.
With continued reference to fig. 14, the method of electrically connecting the semiconductor substrate 100 and the second carrier wafer 180 by the solder bumps 170 is as follows: first, the second carrier wafer 180 is connected with the solder bump 170; and then injecting a fixing glue 181 between the third protection layer 160 and the second carrier wafer 180, and curing the fixing glue 181 to fixedly connect the second carrier wafer 180 and the solder bump 170.
Referring to fig. 15, the first carrier wafer 150 is removed. In some embodiments of the present application, the method of removing the first carrier wafer 150 includes: firstly, inactivating the temporary bonding glue 151 by a laser dissociation or mechanical dissociation mode to lose bonding function; the temporary bonding glue 151 and the first carrier wafer 150 are removed using a wet cleaning process.
Referring to fig. 16 to 19, a first bonding pad electrically connected to the metal interconnection structure 130 is formed over the second protective layer 101.
Referring to fig. 16, the second protective layer 101 is thinned and a fourth dielectric layer 190 is formed on the surface of the second protective layer 101. The material of the fourth dielectric layer 190 includes a dielectric material such as silicon oxide or silicon nitride. The method of forming the fourth dielectric layer 190 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 17, a second trench 191 and a second via 192 communicating with the bottom of the second trench 191 and penetrating the second protection layer 101 to expose the metal interconnection structure 130 are formed in the fourth dielectric layer 190.
In some embodiments of the present application, the method for forming the second trench 191 and the second via 192 is, for example: etching a second groove 191 on the surface of the fourth dielectric layer 190; the second through hole 192 is etched at the bottom of the second trench 191.
Referring to fig. 18, a second interlayer metal line 193 is formed by filling a metal material in the second via hole 192, and a first bonding pad 194 is formed by filling a metal material in the second trench 191. The steps of forming the second interlayer metal line 193 and the first bonding pad 194 may be synchronized. The structure shown in fig. 18 is a semiconductor interposer 200.
Referring to fig. 19, the first bonding pad 194 and the second bonding pad 380 are aligned and bonded (i.e. the semiconductor interposer 200 shown in fig. 18 is bonded to the structure of the chip to be packaged shown in fig. 6), and the bonding process is conventional fusion bonding, which is not described herein.
In a conventional wafer level packaging process, the chip and the semiconductor interposer are electrically connected by solder bumps (i.e., bump process). However, the process node using the welding convex points is larger, the welding convex points are often in the order of tens of micrometers, the I/O quantity of the chip is limited, and the improvement of the chip performance is not facilitated. And the number of the welding convex points of the semiconductor adapter plate and the chip is obviously higher than that of the semiconductor adapter plate and the substrate, so that the whole package has larger warpage and the yield is influenced. In the technical scheme of the application, the chip 310 to be packaged is bonded with the semiconductor adapter plate 200 through the first bonding pad 194 and the second bonding pad 380, so that the technical feature size of the package can be improved, the chip and the semiconductor adapter plate are communicated at high density, the performance of the chip is improved, and the parasitic resistance between the chip and the semiconductor adapter plate is reduced; and the semiconductor adapter plate and the chip are connected without using welding convex points, so that the process of the semiconductor adapter plate can be simplified, and the whole warping of the package is reduced.
Referring to fig. 20, the third carrier wafer 300 is removed, and the chip 310 to be packaged is encapsulated. In some embodiments of the present application, the method for removing the third carrier wafer 300 includes: firstly, inactivating the adhesive glue 301 by a laser dissociation or mechanical dissociation mode to lose the adhesive function; the adhesive 301 and the third carrier wafer 300 are removed using a wet cleaning process.
In some embodiments of the present application, the method of molding the chip 310 to be packaged is to form a molding layer 390 on the chip 310 to be packaged and the injection molding layer 350 using an injection molding process. The material of the plastic layer 390 is, for example, epoxy resin or the like. The plastic layer 390 is used for further fixing and plastic packaging the plurality of chips 310 to be packaged and protecting the plurality of chips 310 to be packaged.
Referring to fig. 21, the second carrier wafer 180 is removed and the solder bumps 170 are exposed; the solder bump 170 is soldered to the substrate 210. After the packaging is completed, the chip 310 to be packaged becomes a packaged chip 311.
In some embodiments of the present application, the method of removing the second carrier wafer 180 includes: firstly, inactivating the fixing glue 181 by a laser dissociation or mechanical dissociation mode to lose the adhesion function; the fixing glue 181 and the second carrier wafer 180 are removed by a wet cleaning process.
With continued reference to fig. 21, the method of soldering the solder bump 170 to the substrate 210 is as follows: first, the substrate 210 is connected with the solder bump 170; and then injecting a connection adhesive 211 between the third protection layer 160 and the substrate 210, and curing the connection adhesive 211 to fixedly connect the substrate 210 and the solder bump 170.
In some embodiments of the present application, the substrate 210 includes any one of a printed wiring board, a copper-clad board, or a flexible circuit board.
According to the wafer level packaging method, the chip and the semiconductor adapter plate are bonded through the first bonding pad and the second bonding pad, so that the technical feature size of packaging can be improved, the chip and the semiconductor adapter plate are communicated at high density, the performance of the chip is improved, and parasitic resistance between the chip and the semiconductor adapter plate is reduced; the semiconductor adapter plate and the chip are connected without using welding convex points, so that the process of the semiconductor adapter plate can be simplified, and the whole warping of the package is reduced.
The embodiment of the present application further provides a wafer level package structure, as shown in fig. 21, including: a first bonding pad 194 is disposed on the first surface of the semiconductor interposer 200; the package chips 311 are arranged according to design requirements and are positioned on the first surface of the semiconductor adapter plate 200, and a top layer welding pad 330 is arranged on one surface of the package chips 311, which is close to the semiconductor adapter plate 200; a second bonding pad 380, wherein the second bonding pad 380 is electrically connected with the top layer pad 330 through a first interlayer metal connection, and the first bonding pad 194 corresponds to the second bonding pad 380; wherein, the semiconductor interposer 200 and the plurality of package chips 311 are bonded with the first bonding pads 194 through the second bonding pads 380; and the injection molding layer 350 is positioned among the packaging chips 311.
With continued reference to fig. 21, the semiconductor interposer 200 includes: the semiconductor device comprises a semiconductor substrate 100, a composite dielectric layer 110 and a through silicon via 120, wherein the composite dielectric layer 110 is arranged on the first surface of the semiconductor substrate 100, one part of the through silicon via 120 is arranged in the semiconductor substrate 100, the other part of the through silicon via extends into the composite dielectric layer 110, a plurality of layers of metal interconnection structures 130 are further formed in the composite dielectric layer 110, and the metal interconnection structures 130 are electrically connected with active devices formed in the semiconductor substrate 100 and the through silicon via 120.
In some embodiments of the present application, the semiconductor substrate 100 is, for example, a silicon substrate.
With continued reference to fig. 21, the composite dielectric layer 110 includes a first dielectric layer 111 and a second dielectric layer 112. For the sake of brevity, only two composite dielectric layers are exemplified in fig. 21. It should be understood that the composite dielectric layer 110 may also include more dielectric layers.
With continued reference to fig. 21, the first dielectric layer 111 may include a plurality of silicon nitride layers and silicon oxide layers (not shown) stacked in sequence. The through silicon via 120 extends into the first dielectric layer 111 and penetrates through the first dielectric layer 111. The second dielectric layer 112 may include a plurality of silicon nitride layers and silicon oxide layers stacked in sequence. The second dielectric layer 112 has a plurality of metal interconnect structures 130 formed therein. The metal interconnect structures 130 electrically connect the through silicon vias 120 and active devices formed in the semiconductor substrate 100, respectively.
The active devices include, for example, capacitive devices, logic devices, and the like. The embodiments of the present application use capacitive devices as examples only. Referring to fig. 7, the plurality of metal interconnect structures 130 further electrically connect active device capacitor devices 140 formed in the semiconductor substrate 100. The capacitive device 140 includes a first dielectric layer 141, an insulating layer 142, a second dielectric layer 143, and a contact structure 144 electrically connecting the first dielectric layer 141 and the second dielectric layer 143, respectively.
With continued reference to fig. 21, the semiconductor interposer 200 further includes a second protective layer 101 covering the surface of the metal interconnection structure 130 and the surface of the composite dielectric layer 110.
In some embodiments of the present application, the material of the second protection layer 101 is, for example, silicon nitride.
With continued reference to fig. 21, the semiconductor interposer 200 further includes a first bonding pad 194 located on the second protective layer 101 and electrically connected to the metal interconnect structure 130.
In some embodiments of the present application, a fourth dielectric layer 190 is disposed on the surface of the second protective layer 101, and the first bonding pad 194 and a second interlayer metal wire 193 located below the first bonding pad 194 and electrically connecting the first bonding pad 194 and the metal interconnection structure 130 are disposed in the fourth dielectric layer 190.
In some embodiments of the present application, the material of the fourth dielectric layer 190 includes a dielectric material such as silicon oxide or silicon nitride.
With continued reference to fig. 21, the semiconductor interposer 200 further includes a third dielectric layer 113 disposed on the second surface of the semiconductor substrate 100, where a surface of the third dielectric layer 113 is coplanar with a surface of the through silicon via 120.
In some embodiments of the present application, the third dielectric layer 113 may include a silicon nitride layer and a silicon oxide layer that are sequentially formed.
Referring to fig. 21, the semiconductor interposer 200 further includes a third protective layer 160 disposed on the surface of the third dielectric layer 113, where a solder bump 170 directly electrically connected to the through silicon via 120 is disposed in the third protective layer 160. The solder bump 170 includes a solder ball 172 and a pad 171 surrounding the solder ball 172.
With continued reference to fig. 21, the second side of the semiconductor interposer 200 includes solder bumps 170 and a substrate 210 connected to and carrying the semiconductor interposer 200 by the solder bumps 170.
In some embodiments of the present application, the substrate 210 includes any one of a printed wiring board, a copper-clad board, or a flexible circuit board.
With continued reference to fig. 21, a plurality of packaged chips 311 arranged according to design requirements are disposed on the first surface of the semiconductor interposer 200.
In the wafer level package structure, chips integrated with a plurality of functions need to be packaged together for effective integration. Referring to fig. 21, the plurality of packaged chips 311 are chips having different functions, such as logic chips, memory chips, and the like. The above-mentioned design requirements refer to that the plurality of packaged chips 311 are not arranged in a fixed manner, but are designed in a targeted manner according to the requirements of customers.
It should be noted that, for the sake of brevity, only two packaged chips 311 are shown in fig. 21, but it should be understood that the number of the packaged chips 311 is not limited, and the number may be greater.
With continued reference to fig. 21, a top layer bonding pad 330 is disposed on a surface of the packaged chip 311 adjacent to the semiconductor interposer 200. The top layer pad 330 is formed in the top dielectric layer 320. The top-level bonding pad 330 is used to electrically connect active devices (not shown in the figure) in the plurality of chips 310 to be packaged. The material of the top dielectric layer 320 includes a dielectric material such as silicon oxide or silicon nitride. The top bonding pad 330 is made of a metal material such as copper or aluminum.
With continued reference to fig. 21, an injection molding layer 350 is disposed between the plurality of packaged chips 311. The material of the injection molding layer 350 is, for example, epoxy resin or the like. The injection molding layer 350 is used for further fixing and molding the plurality of packaged chips 311 and filling gaps between the plurality of packaged chips 311.
With continued reference to fig. 21, a molding layer 390 is disposed over the packaged chip 311 and the injection molding layer 350. The material of the plastic layer 390 is, for example, epoxy resin or the like. The plastic layer 390 is used for further fixing and plastic packaging the plurality of chips 310 to be packaged and protecting the plurality of chips 310 to be packaged.
With continued reference to fig. 21, a second bonding pad 380 is disposed under the top layer pad 330, the second bonding pad 380 is electrically connected to the top layer pad 330 through a first interlayer metal connection, and the first bonding pad 194 corresponds to the second bonding pad 380. The correspondence refers to the number and positions of the first bonding pads 194 and the second bonding pads 380.
In some embodiments of the present application, an interlayer dielectric layer 360 is disposed on the surface of the top layer pad 330, and the second bonding pad 380 and the first interlayer metal wire 370 disposed above the second bonding pad 380 and electrically connecting the second bonding pad 380 and the top layer pad 330 are disposed in the interlayer dielectric layer 360. The material of the interlayer dielectric layer 360 includes a dielectric material such as silicon oxide or silicon nitride.
The semiconductor interposer 200 and the plurality of packaged chips 311 are bonded together with the first bonding pads 194 through the second bonding pads 380.
In a conventional wafer level package structure, the chip and the semiconductor interposer are electrically connected by solder bumps (i.e., bump process). However, the process node using the welding convex points is larger, the welding convex points are often in the order of tens of micrometers, the I/O quantity of the chip is limited, and the improvement of the chip performance is not facilitated. And the number of the welding convex points of the semiconductor adapter plate and the chip is obviously higher than that of the semiconductor adapter plate and the substrate, so that the whole package has larger warpage and the yield is influenced. In the technical scheme of the application, the packaging chip 311 and the semiconductor adapter plate 200 are bonded through the first bonding pad 194 and the second bonding pad 380, so that the technical feature size of packaging can be improved, the chip and the semiconductor adapter plate are communicated at high density, the performance of the chip is improved, and the parasitic resistance between the chip and the semiconductor adapter plate is reduced; and the semiconductor adapter plate and the chip are connected without using welding convex points, so that the process of the semiconductor adapter plate can be simplified, and the whole warping of the package is reduced.
The wafer level packaging structure and the packaging method have the advantages that the chip and the semiconductor adapter plate are bonded through the first bonding pad and the second bonding pad, the technical feature size of packaging can be improved, the chip and the semiconductor adapter plate are communicated at high density, the performance of the chip is improved, and parasitic resistance between the chip and the semiconductor adapter plate is reduced; the semiconductor adapter plate and the chip are connected without using welding convex points, so that the process of the semiconductor adapter plate can be simplified, and the whole warping of the package is reduced.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (15)

1. A wafer level packaging method, comprising:
providing a third carrier wafer, wherein a plurality of chips to be packaged which are arranged according to design requirements are assembled on the third carrier wafer, a first protection layer is formed on the surface of the chips to be packaged, which is far away from the third carrier wafer, and a top layer welding pad is formed under the first protection layer;
forming an injection molding layer on the surface of the third carrier wafer and the surface of the first protection layer, and then grinding the injection molding layer and the first protection layer until the top layer welding pad is exposed;
forming a second bonding pad above the top layer bonding pad, wherein the second bonding pad is electrically connected with the top layer bonding pad through a first interlayer metal wire;
providing a semiconductor adapter plate, wherein a first bonding welding pad is formed on the first surface of the semiconductor adapter plate, and the first bonding welding pad corresponds to the second bonding welding pad;
aligning and bonding the first bonding pad and the second bonding pad;
and removing the third carrier wafer, and plastic packaging the chip to be packaged.
2. The wafer level packaging method of claim 1, wherein the second side of the semiconductor interposer includes solder bumps and a second carrier wafer connected by the solder bumps and carrying the semiconductor interposer, the packaging method further comprising: removing the second carrier wafer and exposing the solder bumps; the weld stud is welded to the substrate.
3. The wafer level packaging method of claim 2, wherein the substrate comprises any one of a printed wiring board, a copper-clad board, or a flexible circuit board.
4. The wafer level packaging method of claim 2, wherein the method of forming the semiconductor interposer comprises:
providing a semiconductor substrate, a composite dielectric layer positioned on a first surface of the semiconductor substrate and a through silicon via, wherein one part of the through silicon via is positioned in the semiconductor substrate, the other part of the through silicon via extends into the composite dielectric layer, and a plurality of layers of metal interconnection structures are formed in the composite dielectric layer and electrically connected with an active device formed in the semiconductor substrate and the through silicon via;
forming a second protective layer covering the surface of the metal interconnection structure and the surface of the composite dielectric layer;
bonding the second protective layer with the first carrier wafer;
thinning the second surface of the semiconductor substrate to enable the through silicon via to protrude out of the second surface of the semiconductor substrate;
forming a third dielectric layer on the second surface of the semiconductor substrate, wherein the surface of the third dielectric layer is coplanar with the surface of the through silicon via;
Forming a third protective layer on the third dielectric layer, and forming a welding bump directly and electrically connected with the through silicon via on the through silicon via;
electrically connecting the semiconductor substrate and the second carrier wafer through the solder bumps;
removing the first carrier wafer;
and forming a first bonding pad electrically connected with the metal interconnection structure above the second protection layer.
5. The wafer level packaging method of claim 4, wherein forming the first bond pad comprises:
thinning the second protective layer and forming a fourth dielectric layer on the surface of the second protective layer;
forming a second groove and a second through hole which is communicated with the bottom of the second groove and penetrates through the second protective layer to expose the metal interconnection structure in the fourth dielectric layer;
and filling metal materials in the second through holes to form second interlayer metal connection lines, and filling metal materials in the second grooves to form first bonding pads.
6. The wafer level package method of claim 4, wherein bonding the second protective layer to the first carrier wafer is by bonding the second protective layer to the first carrier wafer using a temporary bonding glue.
7. The wafer level packaging method of claim 4, wherein thinning the second side of the semiconductor substrate to protrude the through silicon via from the second surface of the semiconductor substrate comprises:
polishing the second surface of the semiconductor substrate using a chemical mechanical polishing process to expose the through silicon via;
and etching the second surface of the semiconductor substrate to the second surface of the through silicon via protruding out of the semiconductor substrate by using an etching process.
8. The wafer level packaging method of claim 4, wherein the methods of removing the first carrier wafer, removing the second carrier wafer, and removing the third carrier wafer each comprise: laser dissociation or mechanical dissociation.
9. The wafer level packaging method of claim 1, wherein forming a second bond pad on the top layer pad, the second bond pad being electrically connected to the top layer pad by a first inter-layer metal connection, comprises:
forming an interlayer dielectric layer on the surface of the top layer welding pad;
forming a first groove and a first through hole which is communicated with the bottom of the first groove and penetrates through the interlayer dielectric layer to expose the top layer welding pad in the interlayer dielectric layer;
And filling metal materials in the first through holes to form the first interlayer metal connection lines, and filling metal materials in the first grooves to form second bonding pads.
10. A wafer level package structure, comprising:
the semiconductor adapter plate is provided with a first bonding welding pad on the first surface;
the packaging chips are arranged according to design requirements and are positioned on the first surface of the semiconductor adapter plate, and a top layer welding pad is arranged on one surface, close to the semiconductor adapter plate, of each packaging chip;
the second bonding welding pad is electrically connected with the top layer welding pad through a first interlayer metal connection wire, and the first bonding welding pad corresponds to the second bonding welding pad;
the semiconductor adapter plate and the packaging chips are bonded with the first bonding pads through the second bonding pads;
and the injection molding layer is positioned among the plurality of packaging chips.
11. The wafer level package structure of claim 10, wherein the second side of the semiconductor interposer includes solder bumps and a substrate connected by the solder bumps and carrying the semiconductor interposer.
12. The wafer level package structure of claim 11, wherein the substrate comprises any one of a printed wiring board, a copper-clad board, or a flexible circuit board.
13. The wafer level package structure of claim 11, wherein the semiconductor interposer comprises:
the semiconductor device comprises a semiconductor substrate, a composite dielectric layer positioned on a first surface of the semiconductor substrate and a through silicon via, wherein one part of the through silicon via is positioned in the semiconductor substrate, the other part of the through silicon via extends into the composite dielectric layer, a plurality of layers of metal interconnection structures are further formed in the composite dielectric layer, and the metal interconnection structures are electrically connected with an active device formed in the semiconductor substrate and the through silicon via;
the second protective layer covers the surface of the metal interconnection structure and the surface of the composite dielectric layer;
the first bonding pad is positioned on the second protection layer and is electrically connected with the metal interconnection structure;
the third dielectric layer is positioned on the second surface of the semiconductor substrate, and the surface of the third dielectric layer is coplanar with the surface of the through silicon via;
and the third protection layer is positioned on the surface of the third dielectric layer, and welding salient points which are directly and electrically connected with the silicon through holes are arranged in the third protection layer.
14. The wafer level package structure of claim 13, wherein a fourth dielectric layer is disposed on the surface of the second protective layer, and the first bonding pad and a second interlayer metal wire disposed under the first bonding pad and electrically connecting the first bonding pad and the metal interconnection structure are disposed in the fourth dielectric layer.
15. The wafer level package structure of claim 10, wherein an interlayer dielectric layer is disposed on a surface of the top layer bonding pad, and the second bonding pad and a first interlayer metal wire disposed above the second bonding pad and electrically connecting the second bonding pad and the top layer bonding pad are disposed in the interlayer dielectric layer.
CN202111239938.5A 2021-10-25 2021-10-25 Wafer level packaging structure and packaging method Pending CN116072552A (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

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CN116072552A true CN116072552A (en) 2023-05-05

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