CN116072163A - Reading system and method - Google Patents
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- CN116072163A CN116072163A CN202111292923.5A CN202111292923A CN116072163A CN 116072163 A CN116072163 A CN 116072163A CN 202111292923 A CN202111292923 A CN 202111292923A CN 116072163 A CN116072163 A CN 116072163A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
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Abstract
The utility model provides a reading system and method, the register unit stores the trouble address of the memory cell that breaks down, the comparison unit compares the trouble address of the memory cell that breaks down that is stored in the register unit with the read operation address that the controller takes place, and produce the comparison result, and when the comparison result indicates that read operation address is unanimous with trouble address, take place the comparison result to redundant address generator, make redundant address generator produce redundant address and send redundant address to the controller, make the controller read corresponding memory cell according to redundant address. In this way, by comparing the read operation address with the fault address stored in the register, it is determined whether the storage unit corresponding to the read operation address can perform the read operation, and when the storage unit corresponding to the read operation address cannot perform the read operation, the redundant address is used to replace the read operation address, so that the controller can acquire data in time, and the read efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a reading system and a reading method.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is an internal memory for directly exchanging data with the CPU, and can read and write data at any time.
The DRAM has millions of memory cells, and when a certain memory cell fails, the data of the memory cell cannot be read out in time, which affects the reading efficiency.
Disclosure of Invention
The application provides a reading system and a reading method, which are used for solving the problem that a storage unit cannot be read out in time when the storage unit fails.
According to some embodiments, a first aspect of the present disclosure provides a reading system comprising:
a register unit for storing a failure address of the failed memory unit;
the comparing unit is connected with the registering unit and the controller and is used for comparing the fault address stored in the registering unit with the read operation address sent by the controller and generating a comparison result;
and the redundant address generator is connected with the comparison unit and is used for generating a redundant address when the comparison result indicates that the read operation address and the fault address are consistent, so that the controller reads the corresponding storage unit according to the redundant address.
Optionally, the comparing unit is further configured to output the read operation address when the comparison result indicates that the read operation address and the failure address are inconsistent, so that the controller reads a storage unit corresponding to the read operation address.
Optionally, the register unit includes a plurality of registers, the comparison unit includes a plurality of comparators, and the registers are in one-to-one correspondence with the comparators;
each register is specifically used for storing the fault address of one storage unit with faults;
each comparator is specifically configured to compare the read operation address with a failure address stored in a corresponding register.
Optionally, the redundant address generator is specifically configured to generate a redundant address according to an address corresponding to a comparator that generates the comparison result when the comparison result indicates that the read operation address and the failure address are consistent.
Optionally, the redundant address generator is specifically configured to generate a redundant address and a matching instruction when the comparison result indicates that the read operation address and the failure address are consistent.
Optionally, the system further comprises:
and the data selector is connected with the redundant address generator and the controller and is used for sending the redundant address to the controller when receiving the redundant address sent by the redundant address generator.
Optionally, the data selector is specifically configured to send the redundant address to the controller when receiving the redundant address and the matching instruction sent by the redundant address generator.
Optionally, the system further comprises:
and the verification unit is used for verifying the writing data written into each storage unit and the reading data read from each storage unit.
Optionally, the verification unit includes a first verifier, where the first verifier is configured to perform a first verification on the write data written into each storage unit.
Optionally, the system further comprises:
the first latch is connected with the first checker and is used for storing the writing data, and after receiving a verification success signal sent by the first checker, the writing data is written into a corresponding storage unit.
Optionally, the first checker is specifically configured to send a first warning signal after the first check fails on the write data.
Optionally, the verification unit includes a second checker for performing a second check on the read data read from each storage unit.
Optionally, the system further comprises:
and the second latch is connected with the second checker and is used for storing the read data read from each storage unit and outputting the read data after receiving a verification success signal generated by the second checker.
Optionally, the second checker is specifically configured to issue a second warning signal after the second check on the read data fails.
According to some embodiments, a second aspect of the present disclosure provides a reading method applied to a comparing unit connected to a registering unit, the comparing unit further connected to a redundant address generator, the comparing unit further connected to a controller, the method comprising:
comparing the fault address stored in the register unit with a read operation address sent by the controller, and generating a comparison result;
and if the comparison result indicates that the read operation address is consistent with the fault address, the redundant address generator is activated to generate a redundant address so that the controller reads the corresponding storage unit according to the redundant address.
Optionally, the method further comprises:
and outputting the read operation address when the comparison result indicates that the read operation address is inconsistent with the fault address, so that the controller reads the corresponding storage unit according to the read operation address.
The reading system provided by the application comprises: the device comprises a registering unit, a comparing unit connected with the registering unit and the controller, and a redundant address generator connected with the comparing unit. The comparison unit compares the fault address of the faulty storage unit stored in the register unit with the read operation address generated by the controller, generates a comparison result, and generates the comparison result to the redundant address generator when the comparison result indicates that the read operation address is consistent with the fault address, so that the redundant address generator generates a redundant address and sends the redundant address to the controller, and the controller reads the corresponding storage unit according to the redundant address. In this way, the read operation address is compared with the fault address stored in the register to judge whether the storage unit corresponding to the read operation address can perform the read operation, and when the storage unit corresponding to the read operation address cannot perform the read operation, the redundant address is used for replacing the read operation address, so that the controller can acquire data in time, and the read efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a reading system according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a reading system according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a reading system according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a reading system according to an embodiment of the present disclosure;
fig. 5 is a flowchart of a reading method according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The random access memory (Random Access Memory, RAM) is an internal memory for directly exchanging data with the CPU, and can write or read data from any one of the designated memory cells, and has data volatility, i.e., the stored data is lost upon power failure. The Random Access Memory includes a Static Random-Access Memory (SRAM) and a dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) according to the operation principle of the Memory cell.
A dynamic random access memory is a semiconductor memory, and mainly uses the magnitude of stored charges in a capacitor to represent whether a binary bit (bit) is 1 or 0. The dynamic random access memory includes a plurality of memory cells, one memory cell, that is, one binary bit, which includes one transistor and one capacitor. When the dynamic random access memory performs a read operation, a Bit Line (BL) is charged to half of an operation voltage, a transistor is turned on to enable the bit line and a capacitor to generate a charge sharing phenomenon, if a stored value is 1, a voltage of the bit line is raised to be higher than half of the operation voltage, if the stored value is 0, the voltage of the bit line is pulled down to be lower than half of the operation voltage, and then the stored value can be judged to be 1 or 0 according to the voltage of the bit line. When the dynamic random access memory is used for writing, the transistor is turned on, if 1 is to be written, the voltage of the bit line is raised to the operating voltage so that the operating voltage is stored on the capacitor, and if 0 is to be written, the voltage of the bit line is reduced to zero so that no charge exists in the capacitor.
Typically, before a memory cell in a dynamic random access memory is read, the memory cell is read and verified to determine whether the memory cell can be read. And before performing a write operation on a memory cell in the dynamic random access memory, performing a write check on the memory cell to determine whether the memory cell can perform the write operation. For example, DDR4-SDRAM (Double Data Rate Synchronous Dynamic Random-access Memory) supports the verification of write data, DDR5-SDRAM supports the verification of write data and read data.
However, after the conventional method performs reading verification on the storage unit to determine that the storage unit cannot perform reading operation, there is no effective method for repairing the storage unit effectively, so that the storage unit cannot be read in time, and the reading efficiency is affected.
To this end, the present application proposes a reading system comprising: the device comprises a registering unit, a comparing unit connected with the registering unit and the controller, and a redundant address generator connected with the comparing unit. The register unit stores the fault address of the faulty storage unit, the comparison unit compares the fault address of the faulty storage unit stored in the register unit with the read operation address generated by the controller, generates a comparison result, and when the comparison result indicates that the read operation address is consistent with the fault address, generates the comparison result to the redundant address generator, so that the redundant address generator generates a redundant address and sends the redundant address to the controller, and the controller reads the corresponding storage unit according to the redundant address. In this way, the read operation address is compared with the fault address stored in the register to judge whether the storage unit corresponding to the read operation address can perform the read operation, and when the storage unit corresponding to the read operation address cannot perform the read operation, the redundant address is used for replacing the read operation address, so that the controller can acquire data in time, and the read efficiency is improved.
The technical scheme of the present application is described in detail below with specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Fig. 1 shows a schematic structural diagram of a reading system according to an embodiment of the present application. The system of the present embodiment includes:
a register unit 101 for storing a failure address of a failed memory unit;
a comparing unit 102 connected to the registering unit 101 and the controller 103, for comparing the failure address stored in the registering unit 101 with the read operation address transmitted by the controller 103, and generating a comparison result;
and a redundant address generator 104 connected to the comparing unit 102 for generating a redundant address when the comparison result indicates that the read operation address and the fail address are identical, so that the controller 103 reads the corresponding memory cell according to the redundant address.
The memory includes a plurality of memory cells, each memory cell having an address including a row address (word line address) and a column address (bit line address), the row address or the column address being an integer code. For example, the memory includes 128 memory cells, and the row address is 0-127 and the column address is 0-127.
A Register Or Fuse (ROF) 101 is used to store a fault address (damage address), which may be understood as an address or a row address of a memory cell that fails to be checked when a read-verify is performed on the memory cell, and a memory cell that fails to be understood as a memory cell that fails to be checked. Since the memory includes a plurality of memory cells, each memory cell can perform a read check, there may be a plurality of memory cells failing to check, i.e. there may be a plurality of failure addresses to be stored in the register unit 101. Thus, the register unit 101 may comprise a plurality of registers, each storing a faulty address. Each register comprises a plurality of triggers with a storage function, one trigger is used for storing 1-bit binary codes, and the registers for storing n-bit binary codes are formed by n triggers.
A comparison unit (compare) 102 is connected to the register unit 101 and the controller 103, compares a read operation address transmitted from the controller (controller) 103 with a failure address stored in the register unit 101, and generates a comparison result. When the memory cell needs to be read, the controller 103 sends the address of the memory cell, that is, the read operation address, to the comparing unit 102. The comparing unit 102 compares the read operation address transmitted from the controller 103 with the failure address stored in the registering unit 101. If the failure address is the address of the memory cell, the comparing unit 102 compares the read operation address generated by the controller 103 with the failure address stored in the registering unit 101, and if the failure address is the row address of the memory cell, the comparing unit 102 compares the row address of the read operation address generated by the controller 103 with the failure address stored in the registering unit 101. If the read addresses are consistent, it is indicated that the register unit 101 stores the read addresses, that is, the memory unit corresponding to the read addresses cannot be read. If the read addresses are inconsistent, it indicates that the register unit 101 does not store the read addresses, that is, the memory unit corresponding to the read addresses may be read.
It will be appreciated that if the read address is stored in the register unit 101, it indicates that the memory cell corresponding to the read address is verified and fails to verify before comparing the read address with the failure address. If the register unit 101 does not store the read operation address, it indicates that the memory cell corresponding to the read operation address is verified and verified successfully, or the memory cell corresponding to the read operation address is not verified before comparing the read operation address with the failure address.
In some embodiments of the present disclosure, after comparing the read operation address with the failure address, if the read operation address is inconsistent with the failure address, the read verification may be performed on the storage unit corresponding to the read operation address, after the read verification is successful, the storage unit corresponding to the read operation address is directly read, if the verification fails, it indicates that the storage unit corresponding to the read operation address is not verified before the verification, and the read operation address may be stored in the register unit 101.
The comparison unit 102 compares the read operation address and the failure address, and generates a comparison result. When the comparison result indicates that the read operation address is consistent with the fault address, the comparison unit 102 sends the comparison result to the redundant address generator 104, so that the redundant address generator 104 generates a redundant address according to the comparison result, and the controller 103 reads a storage unit corresponding to the redundant address, so that the controller 103 can timely acquire the storage unit with the fault, and the reading efficiency is improved. When the comparison result indicates that the read operation address and the failure address are not consistent, the comparison unit 102 outputs the read operation address so that the controller 103 reads the memory cell corresponding to the read operation address.
In some embodiments of the present disclosure, when the comparison result indicates that the read operation address and the failure address are inconsistent, the read operation address is read and verified by the verification unit, and after the read and verification fails, a redundant address generating instruction is sent to the redundant address generator (redundancy address generator) 104, so that the redundant address generator 104 generates a redundant address according to the redundant address generating instruction.
In some embodiments of the present disclosure, the comparing unit 102 may include a plurality of comparators, one comparator corresponding to each register, one register storing a fault address, each comparator comparing the read operation address sent by the controller 103 with the fault address in the corresponding register, each comparator being capable of generating a comparison result including that the read operation address is consistent with the fault address, or that the read operation address is inconsistent with the fault address. When the comparison result of one of the comparators indicates that the read operation address is consistent with the fault address, the storage unit corresponding to the read operation address cannot normally perform read operation, and when the comparison result of any one of the comparators indicates that the read operation address is inconsistent with the fault address, the storage unit corresponding to the read operation address can perform read operation.
For example, referring to fig. 2, the comparing unit 102 includes a first comparator 121, a second comparator 122, a third comparator 123, a fourth comparator 124, a fifth comparator 125, and a sixth comparator 126, and the registering unit 101 includes a first register 111, a second register 112, a third register 113, a fourth register 114, a fifth register 115, and a sixth register 116, in which one failure address is stored in each of the first register 111, the second register 112, the third register 113, the fourth register 114, the fifth register 115, and the sixth register 116. The first comparator 121 corresponds to the first register 111, the second comparator 122 corresponds to the second register 112, the third comparator 123 corresponds to the third register 113, the fourth comparator 124 corresponds to the fourth register 114, the fifth comparator 125 corresponds to the fifth register 115, and the sixth comparator 126 corresponds to the sixth register 116. The first comparator 121 is configured to compare the read operation address with the failure address stored in the first register 111, and generate a first comparison result. The second comparator 122 is configured to compare the read operation address with the failure address stored in the second register 112, and generate a second comparison result. The third comparator 123 is configured to compare the read operation address with the failure address stored in the third register 113, and generate a third comparison result. The fourth comparator 124 is configured to compare the read operation address with the failure address stored in the fourth register 114, and generate a fourth comparison result. The fifth comparator 125 is configured to compare the read operation address with the failure address stored in the fifth register 115, and generate a fifth comparison result. The sixth comparator 126 is configured to compare the read operation address with the failure address stored in the sixth register 116, and generate a sixth comparison result. If one of the six comparison results indicates that the read operation address is consistent with the fault address, the storage unit corresponding to the read operation address cannot normally perform the read operation. And when the six comparison results indicate that the read operation address is inconsistent with the fault address, the storage unit corresponding to the read operation address can perform read operation.
The redundant address generator 104 is connected to the comparing unit 102, and is configured to generate a redundant address when the comparison result indicates that the read operation address and the failure address are consistent, so that the controller 103 reads the corresponding memory cell according to the redundant address. The redundant address generator 104 may be further configured to generate the redundant address after receiving the check unit transmit the redundant address generation instruction.
In some embodiments of the present disclosure, the redundant address generator 104 may generate the redundant address according to the location of the comparator generating the comparison result after receiving the comparison result. Each comparator corresponds to an address, each comparator generates a comparison result, and the address corresponding to the comparator, of which the comparison result shows that the read operation address is consistent with the fault address, can be used as a redundant address.
In some embodiments of the present disclosure, the redundant address generator 104 may generate a match (hit) instruction at the same time as generating the redundant address, and send the redundant address and the match instruction to the controller 103, and after receiving the match instruction and the redundant address, the controller 103 reads a storage unit corresponding to the redundant address. The controller 103 can read the storage unit corresponding to the redundant address after receiving the matching instruction and the redundant address, thereby ensuring the accuracy of the redundant address and further ensuring the accuracy of data reading.
In some embodiments of the present disclosure, further comprising: a data selector (MUX) 105 connected to the redundant address generator 104 and the controller 103, the data selector 105 being configured to transmit the redundant address to the controller 103 upon receiving the redundant address transmitted from the redundant address generator 104, as shown with reference to fig. 3. The data selector 105 is a device having a selection function for switching signals, and may transmit an operation address or a redundant address to the controller 103 in any one of an active, precharge, read, write, etc., the operation address being an address of a memory cell to be activated, an address of a memory cell to be precharged, an address of a memory cell to be read, or an address of a memory cell to be written, and the redundant address being a replacement address of the operation address. When the read operation address is a fail address, the data selector 105 may automatically generate a redundant address to the controller 103 to improve the operation efficiency. The data selector 105 may further send the redundant address to the controller 103 after receiving the redundant address and the matching instruction, so as to ensure accuracy of the read operation address and the redundant address.
The reading system may further include a verification unit that verifies the write data written to each memory cell and the read data read from each memory cell using the verification unit. And verifying the written data written into each storage unit, ensuring the reliability and accuracy of the data written into the storage units, and verifying the read data read from each storage unit, and ensuring the reliability and accuracy of the read data.
In some embodiments of the present disclosure, the verification unit includes a first verifier 201 (check 1), and referring to fig. 4, the first verifier 201 is configured to perform a first verification on write data written to each storage unit, so as to ensure accuracy and reliability of the write data written to each storage unit. The write data written to each memory cell may be verified, for example, by Parity Check (Parity Check).
Parity refers to adding one bit in addition to each byte as a parity bit. After storing data in a certain byte, the data stored on its 8 bits is fixed, and since the bits have only two states, assuming that the stored data is marked with bits 1, 0, 1, each bit is added 1+1+1+0+0+1+0+1=5, with the result being an odd number. For even parity, the parity bit is defined as 1, and for odd parity, the parity bit is defined as 0.
For example, 11001110 needs to be transmitted, the data includes 5 1 s, the odd parity bit is 0, and 110011100 is transmitted to the receiving party, the receiving party calculates parity again after receiving the data, 110011100 still includes 5 1 s, and the odd parity bit calculated by the receiving party is also 0, and is consistent with the transmitting party, which indicates that no error occurs in the data transmission. For example, 11001110 needs to be transmitted, the data includes 5 1 even check bits, and 110011100 is transmitted to the receiving party, the receiving party calculates parity again after receiving the data, 110011100 still includes 5 1 even check bits, and the calculated even check bits of the receiving party are consistent with the transmitting party, which indicates that no error occurs in the data transmission. For example, 11101110 needs to be transmitted, the data includes 6 1 s, the odd parity bit is 1, and 11101110 is transmitted to the receiving party, the receiving party calculates parity again after receiving the data, 11101110 still includes 6 1 s, and the odd parity bit calculated by the receiving party is 1, and is consistent with the transmitting party, which indicates that no error occurs in this data transmission. For example, 11101110 needs to be transmitted, the data includes 6 1 even check bits, 0 even check bits, and 11101110 is transmitted to the receiving party, the receiving party calculates parity again after receiving the data, 11101110 still includes 6 1 even check bits, and the calculated even check bits of 0 even check bits are consistent with the transmitting party, which indicates that no error occurs in the data transmission.
In other embodiments of the present disclosure, the first latch 202 (data latch 1) connected to the first checker 201 may be used to store the write data, where the first latch 202 functions as a transfer station for the write data, i.e., the write data is temporarily stored in the first latch 202 before the write data is written into the memory cell, the first checker 201 performs a first check on the write data in the first latch 202, and if the first check is successful, sends a first check success signal to the first latch 202, so that the first latch 202 writes the write data into the memory cell, and if the first check fails, sends a first warning signal so that the first latch 202 cannot write the write data into the memory cell.
In some embodiments of the present disclosure, the verification unit includes a second verifier 203 (check 2), and referring to fig. 4, the second verifier 203 is configured to perform a second verification on the read data read in each memory cell, so as to ensure accuracy and reliability of the read data read from each memory cell. When the second checker performs the second check on the read data, if the second check is successful, the read data in the storage unit is normally read, and if the second check is failed, the address of the storage unit with the failed second check is sent to the register unit 101, so that the register unit 101 stores the address of the storage unit with the failed second check.
In some embodiments of the present disclosure, after a second check is performed on the memory cells and the second check fails, the failure address needs to be stored in a register. The storing method may be to detect whether the register stores the fault address, and if not, directly store the fault address in the register. If so, continuing to detect whether the next register stores the fault address or not until the register which does not store the fault address is detected, and storing the fault address in the register. For example, when the register unit 101 includes a plurality of registers, after a second check of a certain memory unit fails, it is possible to detect whether each register stores a faulty address at the same time, and store the address of the memory unit in a register that does not store the faulty address; each register may be sequentially detected, and when a register in which a faulty address is not stored is detected, the faulty address is stored in the register.
In other embodiments of the present disclosure, the second latch (data latch 2) 204 connected to the second checker 203 may be used to store the read data read from each storage unit, where the second latch 204 plays a role of a transfer station for the read data, that is, before the read data is normally read, the second latch 204 is temporarily used to store the read data, after the second checker 203 performs the second check on the read data in the second latch 204, if the second check is successful, the read data of the storage unit is normally read, and if the second check is failed, a second warning signal is sent, so that the data cannot be read from the second latch 204, and at the same time, the address of the storage unit that is failed in check is sent to the register unit 101, so that the register unit 101 stores the address, that is, the failure address, of the storage unit that is failed in check.
The reading system provided by the embodiment of the application is described in detail above, by comparing the reading operation address with the fault address stored in the register, whether the storage unit corresponding to the reading operation address can perform the reading operation is judged, and when the storage unit corresponding to the reading operation address cannot perform the reading operation, the redundant address is used for replacing the reading operation address, so that the controller can acquire data in time, and the reading efficiency is improved.
An embodiment of the present application further provides a reading method, and referring to fig. 5, fig. 5 shows a flowchart of a reading method provided in an embodiment of the present application. The method of the present embodiment is used for a comparing unit, the comparing unit is connected with a registering unit, the comparing unit is also connected with a redundant address generator, the comparing unit is also connected with a controller, and the method may include the following steps:
s101, comparing the fault address stored in the register unit with a read operation address sent by the controller, and generating a comparison result.
And the comparison unit compares the read operation address with the fault address stored in the register unit after receiving the read operation address sent by the controller, and generates a comparison result. For example, the comparing unit may include a plurality of comparators, the registering unit includes a plurality of registers, each register corresponds to one of the comparators, each register stores one of the fail addresses, each of the comparators may compare the read operation address with the fail address in the corresponding register, and each of the comparators may generate one of the comparison results.
When the comparison result indicates that the read operation address and the failure address are identical, step S102 is executed, and when the comparison result indicates that the read operation address and the failure address are not identical, step S103 is executed.
S102, exciting a redundant address generator to generate a redundant address so that the controller reads a corresponding storage unit according to the redundant address.
S103, outputting a read operation address, so that the controller reads the corresponding storage unit according to the read operation address.
According to the reading method, the reading operation address is compared with the fault address stored in the register to judge whether the storage unit corresponding to the reading operation address can perform reading operation or not, and when the storage unit corresponding to the reading operation address cannot perform reading operation, the redundant address is used for replacing the reading operation address, so that the controller can acquire data in time, and the reading efficiency is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. Such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (16)
1. A reading system, the system comprising:
a register unit for storing a failure address of the failed memory unit;
the comparing unit is connected with the registering unit and the controller and is used for comparing the fault address stored in the registering unit with the read operation address sent by the controller and generating a comparison result;
and the redundant address generator is connected with the comparison unit and is used for generating a redundant address when the comparison result indicates that the read operation address and the fault address are consistent, so that the controller reads the corresponding storage unit according to the redundant address.
2. The system of claim 1, wherein the comparing unit is further configured to output the read operation address to cause the controller to read a memory cell corresponding to the read operation address when the comparison result indicates that the read operation address and the failure address are not identical.
3. The system according to claim 1 or 2, wherein the registering unit includes a plurality of registers, and the comparing unit includes a plurality of comparators, the registers being in one-to-one correspondence with the comparators;
each register is specifically used for storing the fault address of one storage unit with faults;
each comparator is specifically configured to compare the read operation address with a failure address stored in a corresponding register.
4. A system according to claim 3, wherein the redundant address generator is configured to generate a redundant address based on an address corresponding to a comparator generating a comparison result when the comparison result indicates that the read operation address and the failure address agree.
5. The system according to claim 1, wherein the redundant address generator is specifically configured to generate a redundant address and a match instruction when the comparison result indicates that the read operation address and the failed address agree.
6. The system of claim 5, wherein the system further comprises:
and the data selector is connected with the redundant address generator and the controller and is used for sending the redundant address to the controller when receiving the redundant address sent by the redundant address generator.
7. The system of claim 6, wherein the data selector is specifically configured to send the redundant address to the controller upon receipt of the redundant address and the match instruction sent by the redundant address generator.
8. The system of claim 1, wherein the system further comprises:
and the verification unit is used for verifying the writing data written into each storage unit and the reading data read from each storage unit.
9. The system of claim 8, wherein the verification unit comprises a first verifier to perform a first verification of the write data written to each memory cell.
10. The system of claim 9, wherein the system further comprises:
the first latch is connected with the first checker and is used for storing the writing data, and after receiving a verification success signal sent by the first checker, the writing data is written into a corresponding storage unit.
11. The system of claim 10, wherein the first checker is configured to issue a first warning signal after a first check failure of the write data.
12. The system of claim 8, wherein the verification unit includes a second verifier for performing a second verification of the read data read from each memory cell.
13. The system of claim 12, wherein the system further comprises:
and the second latch is connected with the second checker and is used for storing the read data read from each storage unit and outputting the read data after receiving a verification success signal generated by the second checker.
14. The system according to claim 13, wherein the second checker is configured to issue a second warning signal upon failure of the second check on the read data.
15. A reading method, characterized in that the method is applied to a comparison unit, which is connected to a register unit, which is further connected to a redundant address generator, which is further connected to a controller, the method comprising:
comparing the fault address stored in the register unit with a read operation address sent by the controller, and generating a comparison result;
and if the comparison result indicates that the read operation address is consistent with the fault address, the redundant address generator is activated to generate a redundant address so that the controller reads the corresponding storage unit according to the redundant address.
16. The method of claim 15, wherein the method further comprises:
and outputting the read operation address when the comparison result indicates that the read operation address is inconsistent with the fault address, so that the controller reads the corresponding storage unit according to the read operation address.
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| CN202111292923.5A CN116072163A (en) | 2021-11-03 | 2021-11-03 | Reading system and method |
| PCT/CN2022/073215 WO2023077681A1 (en) | 2021-11-03 | 2022-01-21 | Reading system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117453146A (en) * | 2023-12-22 | 2024-01-26 | 芯能量集成电路(上海)有限公司 | Data reading method, system, eFlash controller and storage medium |
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| JP2002117696A (en) * | 2000-10-10 | 2002-04-19 | Nec Corp | Memory tester |
| US20090154270A1 (en) * | 2007-12-18 | 2009-06-18 | Barth Jr John E | Failing address register and compare logic for multi-pass repair of memory arrays |
| CN107678879A (en) * | 2016-08-01 | 2018-02-09 | 北京同方微电子有限公司 | A kind of apparatus and method verified in real time for bus and memory cell data block |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117453146A (en) * | 2023-12-22 | 2024-01-26 | 芯能量集成电路(上海)有限公司 | Data reading method, system, eFlash controller and storage medium |
| CN117453146B (en) * | 2023-12-22 | 2024-04-05 | 芯能量集成电路(上海)有限公司 | Data reading method, system, eFlash controller and storage medium |
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