CN116069715A

CN116069715A - Storage device sharing system and storage device sharing method

Info

Publication number: CN116069715A
Application number: CN202111299210.1A
Authority: CN
Inventors: 詹钧杰; 黄伟伦; 林佳芬
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2021-11-04
Filing date: 2021-11-04
Publication date: 2023-05-05

Abstract

The invention discloses a storage device sharing system and a storage device sharing method. The memory device sharing system comprises a memory device, a first chip and a second chip. The first chip and the second chip enter an alternating control mode and an arbitration control mode. In the alternate control mode, the first chip as the master periodically controls the arbitration potential to be a first control potential and a second control potential, and communicates with the memory device when the arbitration potential is the first control potential, and the second chip as the slave communicates with the memory device when the arbitration potential is the second control potential. In the arbitration control mode, the first chip or the second chip which has the priority communication event adjusts the arbitration potential from the first arbitration potential to the second arbitration potential, communicates with the memory device, and adjusts the arbitration potential to the first arbitration potential after the communication is completed.

Description

Storage device sharing system and storage device sharing method

Technical Field

The present invention relates to a memory sharing system and a memory sharing method, and more particularly, to a memory sharing system and a memory sharing method capable of reducing area usage and power consumption.

Background

Many consumer products, such as notebook computers, computer screens, televisions, etc., today have multiple identical input or output interfaces, such as multiple USB ports or multiple HDMI ports, and may use multiple chips with identical functions, respectively.

In addition, the speed of various input or output interfaces is increasing, and the demand for chips with signal enhancement functions, such as retimers (retimers) and redrivers (redrivers), is increasing. The firmware used by these multiple signal enhancement chips with the same interface is the same, and in the prior art, a Non-volatile random access memory (NVRAM) is usually allocated to each chip on the system to store the firmware.

In this architecture, the number of NVRAM used is large, which results in disadvantages such as increased cost and increased PCB area. In addition, as power consumption is increasingly emphasized, most products will need to pass power consumption test certification of Energy Star (ES) 8.0, and using more NVRAM will also result in increased power consumption.

Disclosure of Invention

The invention aims to solve the technical problem of providing a storage device sharing system and a storage device sharing method aiming at the defects of the prior art.

In order to solve the above technical problems, one of the technical solutions adopted in the present invention is to provide a memory device sharing system, which includes a memory device, a first chip and a second chip. The first chip is connected to the memory device and has a first arbitration terminal. The second chip is connected to the memory device and has a second arbitration terminal. The second arbitration terminal is connected to the first arbitration terminal and has an arbitration potential. Wherein the first chip and the second chip are configured to enter an alternating control mode, wherein: the first chip is used as a master and is configured to periodically control the arbitration potential to be a first control potential and a second control potential through the first arbitration terminal and communicate with the storage device when the arbitration potential is the first control potential; the second chip is used as a first controlled party and is configured to communicate with the storage device when the arbitration potential is a second control potential; the first chip or the second chip with the priority communication event is configured to enter an arbitration control mode so as to adjust the arbitration potential from the first arbitration potential to the second arbitration potential, communicate with the storage device and adjust the arbitration potential to the first arbitration potential when the communication is completed.

In order to solve the above technical problem, another technical solution adopted by the present invention is to provide a storage device sharing method, which is applicable to a storage device sharing system, and includes a storage device, a first chip and a second chip, wherein the storage device sharing method includes: connecting the first chip to the memory device, wherein the first chip has a first arbitration terminal; connecting the second chip to the memory device, wherein the second chip has a second arbitration terminal connected to the first arbitration terminal and having an arbitration potential; configuring the first chip and the second chip to enter an alternate control mode includes: the first chip is configured as a master to periodically control the arbitration potential to be a first control potential and a second control potential through the first arbitration terminal, and to communicate with the memory device when the arbitration potential is the first control potential; the second chip is configured as a first controlled party to communicate with the storage device when the arbitration potential is the second control potential; the storage device sharing method further includes: the first chip or the second chip with the priority communication event is configured to enter an arbitration control mode so as to adjust the arbitration potential from the first arbitration potential to the second arbitration potential, communicate with the storage device, and adjust the arbitration potential to the first arbitration potential when the communication is completed.

The memory device sharing system and the memory device sharing method have the advantages that the memory device sharing system and the memory device sharing method adopt a structure that a plurality of chips share a single memory device, and because the number of the memory devices is small, the power consumption, the use area of a circuit board and the like can be reduced, so that the cost is reduced.

In addition, the storage device sharing system and the storage device sharing method provided by the invention are suitable for various existing storage devices and various communication interfaces, have wide application range and provide higher flexibility.

For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.

Drawings

Fig. 1 is a schematic diagram of a memory device sharing system according to a first embodiment of the invention applied between a main chip and a plurality of electronic devices.

Fig. 2 is a circuit configuration diagram of a memory device sharing system according to a first embodiment of the present invention.

Fig. 3 is a flowchart of an alternate control mode according to a first embodiment of the present invention.

Fig. 4 is a signal timing diagram in an alternate control mode according to a first embodiment of the present invention.

Fig. 5 is a flowchart of an arbitration control mode according to a first embodiment of the present invention.

FIG. 6 is a timing diagram of signals in an arbitration control mode according to a first embodiment of the present invention.

Fig. 7 is a circuit configuration diagram of a memory device sharing system according to a second embodiment of the present invention.

Fig. 8 is a signal timing diagram in an alternate control mode according to a second embodiment of the present invention.

Detailed Description

The following specific embodiments are presented to illustrate the embodiments of the present invention related to a storage device sharing system and a storage device sharing method, and those skilled in the art will appreciate the advantages and effects of the present invention from the disclosure herein. The invention is capable of other and different embodiments and its several details are capable of modification and variation in various respects, all from the point of view and application, all without departing from the spirit of the present invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention. In addition, the term "or" as used herein shall include any one or combination of more of the associated listed items as the case may be.

First embodiment

Fig. 1 is a schematic diagram of a memory device sharing system according to a first embodiment of the present invention applied between a main chip and a plurality of electronic devices, and fig. 2 is a circuit configuration diagram of the memory device sharing system according to the first embodiment of the present invention.

As shown in fig. 1 and 2, a first embodiment of the present invention provides a memory device sharing system 1, which includes a memory device 10, a first chip 11 and a second chip 12. The memory device 10 may be, for example, but not limited to, a memory device such as a nonvolatile random access memory (nonvolatile random access memory), a flash memory (flash memory), an Electrically Erasable Programmable Read Only Memory (EEPROM), or a one time programmable read only memory (One Time Programmable Read Only Memory, OTPROM).

As shown in fig. 1, the first chip 11 may be connected between the electronic device 01 and the main chip 2, and the second chip 12 may be connected between the electronic device 02 and the main chip 2. In some embodiments, the first chip 11 and the second chip 12 may be, for example, but not limited to, USB Type-C port control chips, or high-definition multimedia interface (High Definition Multimedia Interface, HDMI) control chips, and have interfaces for connecting the electronic device 01 and the electronic device 02, respectively, however, the invention is not limited thereto.

In addition, the memory device 10 stores one or more firmware for implementing the first chip 11 and the second chip 12, and when the first chip 11 and the second chip 12 are to perform part of the functions, the corresponding firmware needs to be obtained from the memory device 10.

The first chip 11 is connected to the memory device 10 through a first input/output interface 110, and has a first master/slave determination terminal MS1 and a first arbitration terminal A1. The first input/output interface 110 may be, for example, but not limited to, a serial peripheral interface (Serial Peripheral Interface, SPI), an integrated circuit bus (Inter-Integrated Circuit, I2C) interface, a display data channel (Display Data Channel, DDC), or the like. The first chip 11 may for example comprise a controller, a microcontroller or a processor, which is arranged to communicate with the electronic device 01 and the main chip 2, and which is also arranged to perform the functions mentioned in the following embodiments of the invention.

As shown in fig. 2, taking the first input/output interface 110 as an SPI as an example, the first input/output interface 110 may include pins SCLK1, SS1, MOSI1, and MISO1. Pin SCLK1 is used to transmit a Serial Clock (SCLK) signal sent by an SPI Master (Master), pin SS1 is used to transmit a Slave Select (SS) signal sent by the SPI Master, pin MOSI1 is used to transmit a Master output Slave input (Master Output Slave Input, MOSI) signal (data sent by the SPI Master), and pin MISO1 is used to transmit a Master input Slave output (Master Input Slave Output, MISO) signal (data sent by the SPI Slave).

In addition, the memory device 10 may be, for example, a memory with an SPI interface, and the pins SCLK1, SS1, MOSI1 and MISO1 may be connected to the pins SCLK0, SS0, MOSI0 and MISO0 of the memory device 10, respectively, to transmit the SCLK signal, SS signal, MOSI signal and MISO signal, respectively, for accessing the memory device 10.

On the other hand, the second chip 12 is connected to the memory device 10 through the second input/output interface 120, and has a second master/slave determination terminal MS1 and a second arbitration terminal A2. Similarly, taking the second input/output interface 120 as the SPI, the second input/output interface 120 can include pins SCLK2, SS2, MOSI2, and MISO2, which are connected to pins SCLK0, SS0, MOSI0, and MISO0, respectively, of the memory device 10. Pin SCLK2 is used to transmit the SCLK signal, pin SS2 is used to transmit the SS signal, pin MOSI2 is used to transmit the MOSI signal, and pin MISO2 is used to transmit the MISO signal.

In this embodiment, the first master slave determination terminal MS1, the first arbitration terminal A1, the second master slave determination terminal MS2, and the second arbitration terminal A2 may be General-purpose input/output (GPIO) pins, for example. Under the architecture that a plurality of SPI hosts (e.g., the first chip 11 and the second chip 12) share a single SPI slave (e.g., the memory device 10), the first master-slave determining terminal MS1, the first arbitration terminal A1, the second master-slave determining terminal MS2, and the second arbitration terminal A2 are configured to implement communication between the plurality of SPI hosts, so as to achieve control timing of the plurality of SPI hosts corresponding to the single SPI slave.

As shown in fig. 2, the second arbitration terminal A2 is connected to the first arbitration terminal A1 and has the same arbitration potential AP as the first arbitration terminal A1. The first master-slave determination terminal MS1 and the second master-slave determination terminal MS2 are configured to define the first chip 11 and the second chip 12 as a master and a slave, respectively. In more detail, the first master-slave determining terminal MS1 and the second master-slave determining terminal MS2 are used for defining which of the plurality of SPI hosts is the most dominant SPI host (i.e. master), which has the right to control the arbitration potential AP.

For example, the definition may be directly performed by pull-up and pull-down resistors on the circuit board. For example, in fig. 2, the first master-slave determining terminal MS1 is connected to the first voltage source VDD1 through the pull-up resistor RH1, and the second master-slave determining terminal MS2 is connected to the ground terminal through the pull-down resistor RL1, so that it can determine how the first chip 11 and the second chip 12 are allocated as the master and the slave by determining the electric potential levels of the first master-slave determining terminal MS1 and the second master-slave determining terminal MS 2. Whereas in the configuration of fig. 2 the first chip 11 is defined as the master and the second chip 12 is defined as the slave.

On the other hand, the arbitration potential AP can be set to an initial potential of the arbitration potential AP by connecting the first arbitration terminal A1 and the second arbitration terminal A2 to a pull-up resistor or a pull-down resistor on the circuit board, and the pins of the first arbitration terminal A1 and the second arbitration terminal A2 are set to an open-drain (open-drain) mode. Taking fig. 2 as an example, the first arbitration terminal A1 and the second arbitration terminal A2 can be connected to the second voltage source VDD2 through the pull-up resistor RH 2.

In the embodiment of the present invention, two control modes, i.e., an arbitration control mode (Arbitration Control Mode) and an alternate control mode (Toggle Control Mode), are provided, and the first chip 11 and the second chip 12 can be dynamically switched into either mode.

The alternating control mode is explained first below. In the initialization phase, for example, when the power of the memory device sharing system 1 is turned on, since all the chips need to read the initialized firmware content from the memory device 10 again at this time, the first chip 11 and the second chip can enter the alternating control mode preferentially. Referring to fig. 3 and 4, fig. 3 is a flowchart of an alternate control mode according to a first embodiment of the present invention, and fig. 4 is a signal timing diagram in the alternate control mode according to the first embodiment of the present invention.

As shown in fig. 3, the alternate control mode includes configuring the first chip 11 to perform the steps of:

step S300: whether to communicate with the storage device 10 (i.e. to store or read with the storage device 10) is determined, if yes, step S301 is entered, and if no, step S300 is repeated.

Step S301: the potential of the first master-slave judging terminal MS1 is judged to be high or low.

Since the first chip 11 is defined as the master by connecting the first master-slave determination terminal MS1 to the pull-up resistor RH1 in the present embodiment, if the potential of the first master-slave determination terminal MS1 is high, the first chip 11 is confirmed to be the master, and the process proceeds to step S302: the arbitration potential AP is periodically controlled to the first control potential Vc1 and the second control potential Vc2 through the first arbitration terminal A1. For example, as shown in the arbitration potential AP of fig. 4, the arbitration potential AP is controlled to be the first control potential Vc1 and the second control potential Vc2 in the period TP.

If the potential of the first master-slave determination terminal MS1 is low, the first chip 11 is defined as the controlled terminal, and the process corresponding to the second chip 12 in the present embodiment is executed, for example, step S312.

Step S303: the arbitration potential AP is determined to be the first control potential Vc1 or the second control potential Vc2.

In response to determining that the arbitration potential AP is the first control potential Vc1, step S304 is entered: communicate with the memory device 10 until the arbitration potential AP is converted from the first control potential Vc1 to the second control potential Vc2. In this step, the first chip 11 communicates the operation SS signal, the SCLK signal, the MOSI signal and the MISO signal with the memory device 10, as shown in fig. 4.

If it is determined in step S303 that the arbitration potential AP is the second control potential Vc2, step S303 is repeated until the arbitration potential AP is converted from the second control potential Vc2 to the first control potential Vc1.

Continuing with fig. 3, the alternate control mode further includes configuring the second chip 12 to perform the following steps:

step S310: whether to communicate with the storage device 10 is determined, if yes, step S311 is performed, and if no, step S310 is repeated.

Step S311: the potential of the second master-slave judging terminal MS2 is judged to be high or low.

Since the second chip 12 is defined as the controlled by connecting the second master-slave determination terminal MS2 to the pull-down resistor in the present embodiment, if the potential of the second master-slave determination terminal MS2 is low, the second chip 12 is confirmed as the controlled, and the process proceeds to step S312: the arbitration potential AP is determined to be the first control potential Vc1 or the second control potential Vc2.

If the potential of the second master-slave determination terminal MS2 is high, the second chip 12 is defined as the master, and the process corresponding to the first chip 11 in this embodiment is executed, for example, step S303.

In response to the judgment in step S312 that the arbitration potential AP is the second control potential Vc2, the process proceeds to step S313: communicate with the memory device 10 until the arbitration potential AP is converted from the second control potential Vc2 to the first control potential Vc1. If it is determined in step S312 that the arbitration potential AP is the first control potential Vc1, step S312 is repeated until the arbitration potential AP is converted from the first control potential Vc1 to the second control potential Vc2.

The first chip 11 with the high level of the first master-slave determining terminal MS1 communicates with the memory device 10 when the arbitration level AP is the first control level Vc1 (low level), and the second chip 12 with the low level of the second master-slave determining terminal MS2 communicates with the memory device 10 when the arbitration level AP is the second control level Vc2 (high level), so as to operate the SS signal, the SCLK signal, the MOSI signal, and the MISO signal. In addition, in fig. 2, at the end of the communication with the memory device 10, the first chip 11 and the second chip 12 both operate the SS, SCLK, MOSI, MISO signal to the Idle state, as shown in the Idle times clk_idle and ss_idle of fig. 4.

Therefore, the flow of the alternate control mode is simple, and the first chip 11 and the second chip 12 can communicate with the memory device 10 in an average time-sharing manner. However, the period TP may be adjusted according to the requirement, and is not limited to a fixed and average allocation.

The arbitration control mode will be described again. When the chip has a priority communication event, the chip can switch to the arbitration control mode, so that the chip can communicate with the memory device 10 and read the required firmware with higher instantaneity. The preferential communication event may be, for example, a chip detecting a connection to the electronic device, or a chip triggering a current or voltage protection function.

In addition, when the chip has communication information which needs to be replied or processed to the connected electronic device, the chip also enters an arbitration control mode. For example, when the chip has the USB Type-C port controller function, different Power Delivery (PD) requests may be received at any time, and instant communication with the storage device 10 is required to obtain the corresponding firmware.

Alternatively, the arbitration control mode is entered when an Interrupt (Interrupt) event of the chip's microcontroller is triggered. For example, when the chip is an interface re-timer, the interrupt flow may need to be entered for immediate processing due to abnormal data transmission.

Referring to fig. 5 and 6, fig. 5 is a flowchart of an arbitration control mode according to a first embodiment of the present invention, and fig. 6 is a signal timing diagram in the arbitration control mode according to the first embodiment of the present invention.

The first chip 11 and the second chip 12 are respectively configured to perform the following steps:

step S50: judging whether a priority communication event occurs. The priority communication event is entered into the arbitration control mode.

Step S51: the arbitration potential AP is determined to be the first arbitration potential AP1 or the second arbitration potential AP2. As shown in fig. 6, the first arbitration potential AP1 and the second arbitration potential AP2 are respectively a high potential and a low potential, which are opposite, due to the pull-up resistor RH 2. In the present embodiment, the first arbitration potential AP1 and the second control potential Vc2 are the same potential (high potential), and the second arbitration potential AP2 and the first control potential Vc1 are the same potential (low potential), but the present invention is not limited thereto.

In response to the arbitration potential AP being the first arbitration potential AP1, step S52 is entered: the arbitration potential AP is adjusted to the second arbitration potential AP2 and communicates with the memory device 10. In response to the arbitration potential AP being the second arbitration potential AP2, which represents that other chips may be communicating with the memory device 10, step S51 is repeated until the arbitration potential AP is converted to the first arbitration potential AP1.

In response to the completion of the communication with the storage device 10, the process proceeds to step S53: the arbitration potential AP is adjusted to the first arbitration potential AP1, and the process returns to step S50.

In response to determining that the priority communication event is excluded in step S50, the flow proceeds to step S54: the first chip 11 and the second chip 12 enter an alternating control mode.

As shown in fig. 5 and 6, step S52 further includes:

step S520: the arbitration potential AP is adjusted to the second arbitration potential AP2 and waits for the first predetermined time tAL.

Step S521: the arbitration potential AP is determined to be the first arbitration potential AP1 or the second arbitration potential AP2.

In response to the arbitration potential AP being the second arbitration potential AP2, step S522 is entered: communication with the memory device is initiated. Otherwise, go back to step S520.

In other words, the arbitration potential AP is operated at the low potential at time t1, and reaches time t2 after the first predetermined time tAL, and the SS signal, SCLK signal, MOSI signal, MISO signal are operated to communicate with the memory device 10 after confirming that the arbitration potential AP is at the low potential again.

Step S53 further includes:

step S530: in response to completing communication with the storage device 10, a second predetermined time tAT is waited.

Step S531: the arbitration potential AP is adjusted to the first arbitration potential AP1.

In other words, after the communication with the memory device 10 is completed, the SS signal, the SCLK signal, the MOSI signal, and the MISO signal are first operated to the Idle state, as shown in time t3, idle time clk_idle, and ss_idle of fig. 6. The arbitration potential AP is then held at a low potential for a period of time, such as a second predetermined time tAT, to time t4 of fig. 6.

The first predetermined time tAL is for avoiding that a plurality of SPI master devices initiate communication with an SPI slave device at the same time, and the second predetermined time tAT is for ensuring that the SPI slave device has stably read the SS, SCLK, MOSI, MISO signal and returns to an idle state, so that other SPI master devices can communicate with the SPI slave device. Although the control flow of the arbitration control mode is more complex, the chip can communicate with the storage device in a higher instantaneity.

Second embodiment

Fig. 7 is a circuit configuration diagram of a memory device sharing system according to a second embodiment of the present invention. The present embodiment adopts a similar structure to the first embodiment, and duplicate description is omitted.

The difference between the present embodiment and the first embodiment is that the storage device sharing system 1 further includes a third chip 13, which is connected to the storage device 10 through a third input/output interface 130, and has a third master/slave determination terminal MS3 and a third arbitration terminal A3. The number of chips in the memory device sharing system 1 is not limited to three in this embodiment, and can be extended and applied according to the manner of this embodiment.

The third arbitration terminal A3 is connected to the first arbitration terminal A1 and the second arbitration terminal A2, and also has an arbitration potential AP. The third master-slave determination terminal MS3 is similarly configured to define the third chip 13 as another controlled terminal with respect to the first chip 11 and the second chip 12 defined as the master and the controlled terminal. The third input/output interface 130 may include pins SCLK3, SS3, MOSI3, and MISO3, which are respectively connected to pins SCLK0, SS0, MOSI0, and MISO0 of the memory device 10 and used for transmitting signals SCLK, SS, MOSI and MISO.

In this embodiment, the SPI master (i.e. the first chip 11) as the master needs to replace the first arbitration terminal A1 with the voltage control circuit 111 from the GPIO in the previous embodiment, so as to serve as an arbitration potential generator to output multi-gear voltages, so as to determine the time for which the first chip 11, the second chip 12 and the third chip 13 can access the memory device 10 in three stages in the alternate control mode.

In the present embodiment, the first chip 11, the second chip 12 and the third chip 13 can execute the arbitration control mode by adopting the same flow as the first embodiment, and thus the description thereof is omitted. The SPI slaves (i.e. the second chip 12 and the third chip 13) to be controlled need to replace the second arbitration terminal A2 and the third arbitration terminal A3 with the

signal converters

121 and 131 capable of reading three-stage (or multi-stage) potentials by the GPIO in the above embodiment, and may, for example, use Analog-to-Digital Converter (ADC).

It should be noted that the alternate control mode is different from the first embodiment. The differences are described below with reference to fig. 8, based on fig. 3. Fig. 8 is a signal timing diagram in an alternate control mode according to a second embodiment of the present invention. In step S302, the difference is that the first chip 11 further periodically controls the arbitration potential AP to the first control potential Vc1, the second control potential Vc2 and the third control potential Vc3 through the voltage control circuit and the first arbitration terminal.

The difference from step S303 is that the first chip 11 determines that the arbitration potential AP is the first control potential Vc1, the second control potential Vc2, or the third control potential Vc3.

In response to determining that the arbitration potential AP is the first control potential Vc1, the memory device 10 is communicated with, and if the arbitration potential AP is the second control potential Vc2 or the third control potential Vc3, the memory device waits until the arbitration potential AP is converted into the first control potential Vc1, as shown in the signal timing of the pin MOSI1 in fig. 8.

The difference between the second chip 12 is that in step S312, the second chip 12 determines the arbitration potential AP to be the first control potential Vc1, the second control potential Vc2 or the third control potential Vc3 through the signal converter 121. In response to determining that the arbitration potential AP is the second control potential Vc2, the memory device 10 is communicated with, and if the arbitration potential AP is the first control potential Vc1 or the third control potential Vc3, the memory device waits until the arbitration potential AP is converted into the second control potential Vc2, as shown in the signal timing of the pin MOSI2 in fig. 8.

Similar to the second chip 12, the third chip 13 determines that the arbitration potential AP is the first control potential Vc1, the second control potential Vc2, or the third control potential Vc3 through the signal converter 131. In response to determining that the arbitration potential AP is the third control potential Vc3, the memory device 10 is communicated with, and if the arbitration potential AP is the first control potential Vc1 or the second control potential Vc2, the memory device waits until the arbitration potential AP is converted into the third control potential Vc3, as shown in the signal timing of the pin MOSI3 in fig. 8.

Advantageous effects of the embodiments

The above disclosure is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention, so all technical equivalents which may be used in the specification and drawings of the present invention are included in the claims of the present invention.

Reference numerals illustrate:

01. 02: electronic device

1: storage device sharing system

2: main chip

10: storage device

11: first chip

12: second chip

13: third chip

110: first input/output interface

111: voltage control circuit

120: second input/output interface

121. 131: signal converter

130: third input/output interface

A1: first arbitration terminal

A2: second arbitration terminal

A3: third arbitration terminal

AP: arbitration potential

AP1: first arbitration potential

AP2: second arbitration potential

Clk_idle, ss_idle: idle time

SCLK0, SS0, MOSI0, MISO0, SCLK1, SS1, MOSI1, MISO1, SCLK2, SS2, MOSI2, MISO2, SCLK3, SS3, MOSI3, MISO3: pin

SCLK: serial clock signal

SS: slave selection signal

MS1: first master-slave judgment terminal

MS2: a second master-slave judgment terminal

MS3: third master-slave judgment terminal

RH1, RH2: pull-up resistor

RL1: pull-down resistor

t1, t2, t3, t4: time of

tAL: a first predetermined time

tAT: a second predetermined time

TP: cycle time

Vc1: a first control potential

Vc2: second control potential

Vc3: third control potential

VDD1: first voltage source

VDD2: second voltage source

Claims

1. A storage device sharing system, comprising:

a storage device;

the first chip is connected to the storage device and provided with a first arbitration end; and

a second chip connected to the memory device and having a second arbitration terminal connected to the first arbitration terminal and having an arbitration potential,

wherein the first chip and the second chip are configured to enter an alternating control mode, wherein:

the first chip is used as a master and is configured to periodically control the arbitration potential to be a first control potential and a second control potential through the first arbitration terminal, and communicate with the storage device when the arbitration potential is the first control potential;

the second chip is used as a first controlled party and is configured to communicate with the storage device when the arbitration potential is the second control potential;

the first chip and the second chip are configured to determine whether a priority communication event occurs, and the first chip or the second chip that occurs the priority communication event is configured to enter an arbitration control mode to adjust the arbitration potential from a first arbitration potential to a second arbitration potential and communicate with the memory device, and adjust the arbitration potential to the first arbitration potential when the communication is completed.

2. The storage sharing system of claim 1, wherein the first chip has a first master-slave determination terminal for defining the first chip as the master, the second chip has a second master-slave determination terminal for defining the second chip as the first slave,

the first chip is configured to confirm that the first chip is the master by judging the potential of the first master-slave judging terminal, and the second chip is configured to confirm that the second chip is the first slave by judging the potential of the second master-slave judging terminal.

3. The storage sharing system of claim 1, wherein the first chip and the second chip are configured to enter the alternate control mode in response to the priority communication event exclusion.

4. The memory device sharing system of claim 1, wherein entering the arbitration control mode to adjust the arbitration potential from the first arbitration potential to the second arbitration potential and to communicate with the memory device further comprises:

adjusting the arbitration potential to the second arbitration potential and waiting for a first predetermined time;

judging the arbitration potential as the first arbitration potential or the second arbitration potential; and

and responding to the arbitration potential as the second arbitration potential to communicate with the storage device.

5. The memory device sharing system of claim 1, wherein the step of adjusting the arbitration potential to the first arbitration potential when communication is completed further comprises:

waiting a second predetermined time in response to completing communication with the storage device; and

the arbitration potential is adjusted to the first arbitration potential.

6. The storage sharing system of claim 1, wherein the first chip and the second chip enter the alternate control mode preferentially during an initialization phase.

7. The memory device sharing system of claim 1, further comprising a third chip connected to the memory device and having a third master-slave determination terminal and a third arbitration terminal, wherein the third arbitration terminal is connected to the first arbitration terminal and the second arbitration terminal and has the arbitration potential, and the third master-slave determination terminal is configured to define the third chip as a second controlled party.

8. The storage sharing system of claim 7, wherein the first, second, and third chips are configured to determine whether the priority communication event occurred, and the first, second, or third chip that occurred the priority communication event is configured to enter the arbitration control mode, comprising:

judging the arbitration potential as the first arbitration potential or the second arbitration potential;

responsive to the arbitration potential being the first arbitration potential, adjusting the arbitration potential to the second arbitration potential and communicating with the memory device; and

and adjusting the arbitration potential to the first arbitration potential in response to the communication with the memory device being completed.

9. The storage sharing system of claim 7, wherein the third chip is further configured to enter the alternate control mode, and in the alternate control mode, the first chip is further configured to:

the first arbitration terminal periodically controls the arbitration potential to be the first control potential, the second control potential and the third control potential through a voltage control circuit;

judging whether the arbitration potential is the first control potential, the second control potential or the third control potential; and

responding to the judgment that the arbitration potential is the first control potential and communicating with the storage device; the second chip is further configured to:

judging whether the arbitration potential is the first control potential, the second control potential or the third control potential through a first signal converter; and

responding to the judgment that the arbitration potential is the second control potential and communicating with the storage device; the third chip is further configured to:

confirming that the third chip is the second controlled party by judging the potential of the third master-slave judging terminal;

judging whether the arbitration potential is the first control potential, the second control potential or the third control potential through a second signal converter; and

and responding to the judgment that the arbitration potential is the third control potential and communicating with the storage device.

10. The storage device sharing method is applicable to a storage device sharing system, and comprises a storage device, a first chip and a second chip, and the storage device sharing method comprises the following steps:

connecting the first chip to the storage device, wherein the first chip is provided with a first arbitration terminal;

connecting the second chip to the memory device, wherein the second chip has a second arbitration terminal connected to the first arbitration terminal and having an arbitration potential;

configuring the first chip and the second chip to enter an alternate control mode includes:

the first chip is configured as a master, so that the arbitration potential is periodically controlled to be a first control potential and a second control potential through the first arbitration terminal, and the first chip is communicated with the storage device when the arbitration potential is the first control potential; and

configuring the second chip as a first controlled party to communicate with the memory device when the arbitration potential is the second control potential;

the first chip and the second chip are configured to judge whether a priority communication event occurs, and the first chip or the second chip which occurs the priority communication event is configured to enter an arbitration control mode so as to adjust the arbitration potential from a first arbitration potential to a second arbitration potential and communicate with the storage device, and the arbitration potential is adjusted to the first arbitration potential when the communication is completed.