CN116068815A

CN116068815A - Display substrate, display panel and display device

Info

Publication number: CN116068815A
Application number: CN202111274782.4A
Authority: CN
Inventors: 杨智超; 王建; 张勇; 邓祁; 曲峰; 尹晓峰; 乜玲芳; 安亚帅; 郝龙虎; 王德生
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2023-05-05

Abstract

The present disclosure provides a display substrate, including: a plurality of sub-pixels arranged on the substrate, wherein the plurality of sub-pixels are arranged in an array, and the plurality of sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels; the first sub-pixels and the second sub-pixels positioned in the same row are respectively connected with two adjacent rows of grid lines, and in at least one row of sub-pixels: the plurality of sub-pixels are divided into a plurality of groups, at least one group including a plurality of first sub-pixels and a plurality of second sub-pixels, the plurality of first sub-pixels in the group being disposed adjacent to each other, and each of the first sub-pixels in the group further having a second sub-pixel disposed adjacent thereto, the first sub-pixel and the second sub-pixel adjacent thereto being connected to a column of data lines. The disclosure also provides a display panel and a display device.

Description

Display substrate, display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display substrate, a display panel and a display device.

Background

In a conventional display panel, one data line is required for driving each column of pixels. With the increasing demands of the market for high resolution and narrow frames, dual Gate (Dual Gate) driven designs are emerging. Under this kind of design mode, can drive two rows of pixels with a row of data line to make the quantity of wiring in the display panel reduce, and then, greatly reduced the size of display panel frame, be favorable to satisfying demands such as high resolution and narrow frame.

However, the display panel using the dual gate driving at present is prone to the problem of screen flicker, and the display effect is not ideal.

Disclosure of Invention

In view of the above, the present disclosure provides a display substrate, a display panel, and a display device.

In a first aspect of the present disclosure, there is provided a display substrate, including:

a plurality of sub-pixels arranged on the substrate, wherein the sub-pixels are arranged in an array, and the sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels;

the first sub-pixels and the second sub-pixels positioned in the same row are respectively connected with two adjacent rows of grid lines, and in at least one row of sub-pixels:

the plurality of the sub-pixels are divided into a plurality of groups, at least one group comprises a plurality of the first sub-pixels and a plurality of the second sub-pixels, the plurality of the first sub-pixels in the group are arranged adjacent to each other, each of the first sub-pixels in the group also has a second sub-pixel arranged adjacent to the first sub-pixel, and the first sub-pixel and the second sub-pixel adjacent to the first sub-pixel are connected with a column of data lines.

According to an embodiment of the present disclosure, at the first inversion driving timing, the sub-pixels of at least one color satisfy the following relationship in each frame of the screen:

The number of the first sub-pixels charged with the first voltage signal is the same as the number of the first sub-pixels charged with the second voltage signal, and the number of the second sub-pixels charged with the first voltage signal is the same as the number of the second sub-pixels charged with the second voltage signal;

the first voltage signal and the second voltage signal are voltage signals with opposite polarities.

According to an embodiment of the present disclosure, at the second inversion driving timing, the sub-pixels of at least one color satisfy the following relationship in each frame of the screen:

the number of the first sub-pixels filled with a third voltage signal is the same as the number of the first sub-pixels filled with a fourth voltage signal, the number of the second sub-pixels filled with the third voltage signal is the same as the number of the second sub-pixels filled with the fourth voltage signal, and the third voltage signal and the fourth voltage signal are voltage signals with opposite polarities;

one of the first inversion driving timing and the second inversion driving timing is a dot inversion timing, and the other is a 1+2 dot inversion timing.

According to an embodiment of the present disclosure, in at least one group of sub-pixels, the first sub-pixel is connected to the gate line of the n-th row, and the second sub-pixel is connected to the gate line of the n-1 th row.

According to an embodiment of the present disclosure, the at least one group of sub-pixels includes two of the first sub-pixels and two of the second sub-pixels, wherein the two of the first sub-pixels are different in color and the two of the second sub-pixels are identical in color.

According to an embodiment of the present disclosure, at least one of the sub-pixels includes a first electrode including a first sub-electrode extending along a first direction and a second sub-electrode extending along a second direction, the first direction and the second direction intersecting.

According to an embodiment of the present disclosure, the first electrode further includes a first connection portion through which the first sub-electrode and the second sub-electrode are connected, the first connection portion being bent toward a third direction intersecting the first direction and the second direction.

According to an embodiment of the present disclosure, at least one of the sub-pixels further comprises a second electrode and a liquid crystal layer, the first electrode and the second electrode constituting a driving electrode configured to provide a driving electric field in response to a driving signal, the driving electric field configured to deflect liquid crystals in the liquid crystal layer.

According to an embodiment of the present disclosure, the at least one column of data lines includes a first segment having an extension direction substantially the same as that of the first sub-electrode and a second segment having an extension direction substantially the same as that of the second sub-electrode.

According to an embodiment of the present disclosure, the data line further includes a second connection portion through which the first segment and the second segment are connected, the second connection portion being bent toward a fourth direction intersecting the first direction and the second direction.

According to an embodiment of the present disclosure, at least one of the sub-pixels further includes a thin film transistor in which a first electrode of the thin film transistor is connected to a data line, a gate electrode of the thin film transistor is connected to a gate line, a second electrode of the thin film transistor includes a body portion and a third connection portion, an orthographic projection of the body portion on the substrate at least partially overlaps an orthographic projection of an active layer of the thin film transistor on the substrate, and an orthographic projection of the third connection portion on the substrate at least partially overlaps an orthographic projection of the first electrode on the substrate;

In at least one group of the sub-pixels, the third connection portion of the first sub-pixel extends toward a direction approaching the first sub-pixel adjacent to the first sub-pixel, and the third connection portion of the second sub-pixel extends toward a direction away from the first sub-pixel adjacent to the second sub-pixel.

According to an embodiment of the present disclosure, at least one column of data lines includes a fourth connection portion and a fifth connection portion;

the fourth connecting part is connected with one first sub-pixel in the m-1 row of sub-pixels, the fifth connecting part is connected with one second sub-pixel in the m row of sub-pixels, the orthographic projection of the fourth connecting part on the substrate is positioned on one side of the orthographic projection of the fifth connecting part on the substrate, which is close to the orthographic projection of the m row of sub-pixels on the substrate, and m is a positive integer.

According to an embodiment of the present disclosure, the display substrate further includes a first gate driving circuit for supplying an electric signal to the gate lines of the odd numbered rows and a second gate driving circuit for supplying an electric signal to the gate lines of the even numbered rows.

A second aspect of the present disclosure provides a display panel, including the display substrate described above.

A third aspect of the present disclosure provides a display device, including the display panel described above.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be more apparent from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:

FIG. 1 schematically illustrates a schematic view of a display substrate in one example;

FIG. 2 schematically illustrates polarities of voltage signals charged in sub-pixels of a frame of a display in an example;

FIG. 3 schematically illustrates a schematic diagram of a 102a detection screen in one example;

FIG. 4 schematically illustrates an example of detecting the ON/OFF state of each subpixel in a frame at 102 a;

FIG. 5 schematically illustrates a schematic diagram of thin film transistors in two adjacent columns of subpixels in one example;

FIG. 6 schematically illustrates a schematic diagram of voltage changes during subpixel charging in one example;

FIG. 7 schematically illustrates one of the schematic diagrams of the display substrate in an embodiment of the present disclosure;

fig. 8a and 8b schematically illustrate polarities of voltage signals charged in each subpixel in one frame of a display according to an embodiment of the disclosure;

Fig. 9a and 9b schematically illustrate schematic diagrams of on-off states of each subpixel under the 102a detection screen in the embodiment of the present disclosure;

fig. 10 schematically illustrates a second schematic view of a display substrate in an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are intended to be within the scope of the present disclosure, based on the described embodiments of the present disclosure.

It is noted that in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or description. As such, the dimensions and relative dimensions of the various elements are not necessarily limited to those shown in the figures. In the description and drawings, the same or similar reference numerals refer to the same or similar parts.

When an element is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected to, or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms and/or expressions describing the relationship between elements should be interpreted in a similar manner, e.g. "between … …" pair "directly between … …", "adjacent" pair "directly adjacent" or "on … …" pair "directly on … …" etc. Furthermore, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. Further, the X-axis, Y-axis, and Z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y and Z such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that although the terms "first," "second," etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer and/or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below may be referred to as a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present disclosure.

For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" or "above" the other elements or features.

It will be understood by those skilled in the art that in this context, unless otherwise indicated, the expression "thickness" refers to the dimension along the surface of the display substrate where the respective film layers are disposed, i.e. the dimension along the light exit direction of the display substrate.

In this context, unless otherwise indicated, the expression "patterning process" generally includes the steps of coating of photoresist, exposure, development, etching, stripping of photoresist, and the like. The expression "one patterning process" means a process of forming a patterned layer, feature, component, etc. using a single mask.

The expressions "same layer", "same layer arrangement", or the like refer to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process and then patterning the film layer by one patterning process using the same mask plate. Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

In this document, unless otherwise indicated, the expression "electrically connected" may mean that two components or elements are directly electrically connected, e.g., component or element a is in direct contact with component or element B and electrical signals may be transferred therebetween; it may also be represented that two components or elements are electrically connected by a conductive medium, such as a conductive wire, for example, component or element a is electrically connected by a conductive wire to component or element B to transfer electrical signals between the two components or elements; it may also be indicated that two components or elements are electrically connected by at least one electronic component, for example, component a is electrically connected to component B by at least one thin film transistor to transfer an electrical signal between the two components or elements.

Fig. 1 schematically shows a schematic view of a display substrate in an example, which, as shown in fig. 1, includes a plurality of sub-pixels 11, a plurality of rows of gate lines 12, and a plurality of columns of data lines 13. The plurality of sub-pixels 11 are distributed in an array, and the plurality of sub-pixels 11 includes a plurality of third sub-pixels 111 and a plurality of fourth sub-pixels 112, wherein the third sub-pixels 111 are connected to the gate lines 12 of the odd numbered rows, and the fourth sub-pixels 112 are connected to the gate lines 12 of the even numbered rows. Each column of data lines 13 connects two adjacent columns of subpixels 11, and the subpixels 11 to which different data lines 13 are connected are different. Here, the two adjacent rows of sub-pixels 11 refer to the sub-pixels 11 having no other row between the two rows of sub-pixels 11. For example, for a column data line 13, the column data line 13 is connected to a third subpixel 111 located on the left side of the column data line 13 and a fourth subpixel 112 located on the right side of the column data line 13.

In this example, the display substrate may be a liquid crystal display substrate, and alternatively, in this example, a 1+2 dot inversion driving method is used for driving, thereby improving the problem of polarization of liquid crystal in the liquid crystal layer in the display substrate. Fig. 2 schematically illustrates a schematic diagram of polarities of voltage signals charged in each subpixel in one frame of a display in an example, as shown in fig. 2, in a driving mode of 1+2 dot inversion, for each row of subpixels 11, the voltage signals charged in the remaining subpixels 11 except for the first and last columns of subpixels 11 are inverted in a period of two columns.

Fig. 3 schematically illustrates a schematic diagram of a detection screen of 102a in an example, and fig. 4 schematically illustrates a schematic diagram of on-off states of sub-pixels under the detection screen of 102a in an example, in which only the lighted sub-pixel 11 is illustrated in fig. 4. The 102a detection screen is a screen in which each pixel unit in the display substrate is displayed in one cycle of four colors of "blue B, red R, yellow Y, and cyan C", and alternatively, one pixel unit is composed of red subpixel 11R, green subpixel 11G, and blue subpixel 11B.

As shown in fig. 2 to 4, when the pixel unit displays blue, the blue subpixel 11B in the pixel unit is turned on; when the pixel unit displays red, the red subpixel 11R in the pixel unit is turned on; when the pixel unit displays yellow, the red subpixel 11R and the green subpixel 11G in the pixel unit are turned on; when the pixel unit displays cyan, the green subpixel 11G and the blue subpixel 11B in the pixel unit are turned on. The inventors found in the study that the display substrate in this example had a problem of a flick (Flicker NG) under the 102a detection screen, and the problem of the occurrence of the flick was analyzed below.

Fig. 5 schematically illustrates a schematic diagram of thin film transistors in two adjacent columns of subpixels in an example, and as shown in fig. 5, each subpixel 11 includes a thin film transistor T connected to a gate line 12 and a data line 13, and the thin film transistor T includes a source electrode T1, a drain electrode T2, and a gate electrode T3. In the thickness direction of the display substrate, the source electrode T1 and the gate electrode T3 in the thin film transistor T partially overlap, which results in the generation of parasitic capacitance (Cgs). Fig. 6 schematically illustrates a voltage change during charging of a subpixel, and as shown in fig. 6, the subpixel 11 may be charged according to a data voltage signal on the data line 13, and after the charging is completed, the charging voltage on the subpixel 11 is pulled down by a certain voltage V due to the coupling effect of Cgs, regardless of whether the charging voltage (hereinafter referred to as charging voltage) of the subpixel is positive or negative. As shown in fig. 5, in the display substrate, since the third subpixel 111 is controlled by the gate line 12 of the odd numbered row, the fourth subpixel 112 is controlled by the gate line 12 of the even numbered row, in other words, the plurality of subpixels 11 in each row are respectively controlled by the gate lines 12 of the upper and lower two rows, there are two kinds of thin film transistors T designed in place, for example, as shown in fig. 5, the thin film transistor T of the third subpixel 111 is disposed at the upper end, and the thin film transistor T of the fourth subpixel 112 is disposed at the lower end. When the layer where the source T1 of the thin film transistor T is located and the layer where the gate T3 is located are misaligned, the overlapping area of the source T1 and the gate T3 of the thin film transistor T disposed at the upper end will be different from the overlapping area of the source T1 and the gate T3 of the thin film transistor T disposed at the lower end, and thus Cgs of the thin film transistor T disposed at the upper end is different from Cgs of the thin film transistor T disposed at the lower end. For example, when the layer of the source T1 of the thin film transistor T moves up as a whole, the overlapping area of the source T1 and the gate T3 of the thin film transistor T disposed at the upper end is reduced, while the overlapping area of the source T1 and the gate T3 of the thin film transistor T disposed downward is unchanged, which further results in Cgs of the third subpixel 111 being smaller than Cgs of the fourth subpixel 112. With the third sub-pixel 111, since Cgs thereof is small, the pull-down amplitude of the charging voltage is small after the charging thereof is completed, and when the polarity of the charging voltage of the third sub-pixel 111 is positive after the charging is completed, the luminance thereof is dark with respect to the desired luminance, and the luminance thereof is A1; when the polarity of the charging voltage is negative, the brightness thereof is brighter than the desired brightness, and the brightness is B1; for the fourth subpixel 112, since its Cgs is large, the pull-down amplitude of the charging voltage is large after its charging is completed, and when the polarity of the charging voltage is positive, its luminance is dark with respect to the desired luminance, and the luminance is A2; when the polarity of the charging voltage is negative, the luminance thereof is brighter than the desired luminance, and the luminance is B2. Wherein A1 is more than A2, and B1 is less than B2. When the third subpixel 111 with luminance A1 is not offset by the third subpixel 111 with luminance B1, or the fourth subpixel 112 with luminance A2 is not offset by the fourth subpixel 112 with luminance B2, the display will be entirely darker (or brighter). For example, as shown in fig. 2 to 4, in the 102a detection frame, there are 4 "r+down", 4 "R-up", 4 "g+down", 4 "G-up", 4 "b+down", and 4 "B-up", where "r\g\b" represents red\green\blue sub-pixels 11, respectively, "+/-" represents the polarity of the charging voltage charged by the sub-pixels 11, and "up/down" represents the position of the thin film transistor T in the sub-pixels 11. As can be seen from fig. 4, "R + down" does not have "R-down" corresponding offset, "R-up" does not have "R + up" corresponding offset, and so on. When the polarity of the next frame of picture is reversed, the display picture is overall brighter (or darker), so that the phenomenon of screen flashing is caused.

In view of this, the embodiment of the disclosure provides a display substrate, fig. 7 schematically illustrates one of schematic diagrams of the display substrate in the embodiment of the disclosure, and as shown in fig. 7, the display substrate includes: a plurality of sub-pixels 21, a plurality of rows of gate lines 22, and a plurality of columns of data lines 23 disposed on the substrate. The plurality of sub-pixels 21 are arranged in an array, and the plurality of sub-pixels 21 include a plurality of first sub-pixels 211 and a plurality of second sub-pixels 212. The first subpixel 211 and the second subpixel 212 located in the same row are respectively connected to the adjacent two rows of gate lines 22, and in at least one row of subpixels 21:

the plurality of sub-pixels 21 are divided into a plurality of groups, at least one group including a plurality of first sub-pixels 211 and a plurality of second sub-pixels 212, the plurality of first sub-pixels 211 in the group being disposed adjacent to each other, and each of the first sub-pixels 211 in the group further having a second sub-pixel 212 disposed adjacent thereto, the first sub-pixel 211 and the second sub-pixel 212 adjacent thereto being connected to a column data line 23.

In the embodiment of the present disclosure, the plurality of sub-pixels 21 may display a plurality of colors, for example, the plurality of sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels. The first subpixel 211 may be connected to the gate line 22 of the even numbered row, and the second subpixel 212 may be connected to the gate line 22 of the odd numbered row. Alternatively, each row of subpixels may be divided into a plurality of groups, and each group of subpixels may include a plurality of first subpixels 211 and a plurality of second subpixels 212. For example, each group of the sub-pixels includes four sub-pixels 21 in which two first sub-pixels 211 are disposed adjacent to each other and two second sub-pixels 212 are disposed on both sides of the two first sub-pixels 211, respectively, such that the second sub-pixels 212 on the left side and the second sub-pixels on the right side can each be disposed adjacent to one first sub-pixel 211. In the group of the subpixels, the second subpixel 212 on the left side and the first subpixel 211 adjacent thereto are connected to one data line 23, and the second subpixel 212 on the right side and the first subpixel 211 adjacent thereto are also connected to one data line 23. In this way, for the entire display substrate, each column of data lines 23 can be connected to two adjacent columns of sub-pixels 21, so that two columns of sub-pixels 21 can be driven to display by one data line 23.

By adopting the display substrate disclosed by the embodiment of the invention, the problem of screen flashing of the display substrate under the drive time sequence of polarity inversion can be solved. For example, fig. 8a and 8b schematically illustrate the polarities of the voltage signals charged in the sub-pixels in one frame of the display in the embodiment of the disclosure, wherein fig. 8a is a schematic diagram of the polarities of the voltage signals charged in the sub-pixels in the dot inversion driving timing, and fig. 8b is a schematic diagram of the polarities of the voltage signals charged in the sub-pixels in the 1+2 dot inversion driving timing. As shown in fig. 8a and 8b, with the display substrate according to the embodiment of the present disclosure, in one frame of image, for one row of sub-pixels, it may be ensured that the polarities of voltages charged by the plurality of sub-pixels 21 in the row of sub-pixels are converted with one column as a period, and compared with the conventional display substrate, the display substrate according to the embodiment of the present disclosure is advantageous for canceling the first sub-pixels 211 (the second sub-pixels 212) with different brightness from each other, thereby improving the problem of the flash screen.

The display substrate according to the embodiment of the present disclosure will be described in detail with reference to fig. 7 to 10.

In some embodiments, at the first inversion driving timing, the sub-pixels 21 of at least one color satisfy the following relationship in each frame:

the number of the first sub-pixels 211 charged with the first voltage signal is the same as the number of the first sub-pixels 211 charged with the second voltage signal, and the number of the second sub-pixels 212 charged with the first voltage signal is the same as the number of the second sub-pixels 212 charged with the second voltage signal. The first voltage signal and the second voltage signal are voltage signals with opposite polarities. For example, the polarity of the first voltage signal is positive and the polarity of the second voltage signal is negative. For example, the first voltage signal and the second voltage signal are both voltage signals charged into the sub-pixel 21 through the data line.

In the embodiment of the present disclosure, the first inversion driving timing may be a dot inversion driving timing at which the active level signals are sequentially supplied to the plurality of rows of gate lines 22, wherein the data voltage signals having positive polarities are supplied to the data lines 23 of the odd numbered columns and the data voltage signals having negative polarities are supplied to the data lines 23 of the even numbered columns when the active level signals are supplied to the 1 st row of gate lines 22. When the active level signal is supplied to the 2 nd row gate line 22, the data voltage signal having a negative polarity is supplied to the data lines 23 of the odd columns, and the data voltage signal having a positive polarity is supplied to the data lines 23 of the even columns. When the active level signal is supplied to the 3 rd row gate line 22, the data voltage signal having a positive polarity is supplied to the data lines 23 of the odd columns, and the data voltage signal having a negative polarity is supplied to the data lines 23 of the even columns. In the case of supplying the active level signal to the 4 th row gate line 22, the data voltage signal having the negative polarity is supplied to the data lines 23 of the odd columns, the data voltage signal having the positive polarity is supplied to the data lines 23 of the even columns, and so on. In one frame, the polarity of the voltage charged in each sub-pixel 21 in the display substrate is as shown in fig. 8 a.

The active level signal supplied to the gate line 22 is an electric signal that turns on the thin film transistor connected to the data line 23 in the subpixel 21. Fig. 9a and 9b schematically illustrate diagrams of on-off states of each subpixel in the detection screen at 102a in the embodiment of the present disclosure, wherein fig. 9a is a diagram of on-off states of each subpixel in the dot inversion driving timing, fig. 9b is a diagram of on-off states of each subpixel in the 1+2 dot inversion driving timing, and fig. 9a and 9b only illustrate the lighted subpixel 21.

As shown in fig. 8a and 9a, taking an example that each group of sub-pixels includes four sub-pixels 21, under the 102a detection frame, there are 2 "r+up", 2 "R-up", 2 "r+down", 2 "R-down", 2 "g+up", 2 "G-up", 2 "g+down", 2 "G-down", 2 "b+up", 2 "B-up", 2 "b+down", and 2 "B-down", respectively. Wherein "R\G\B" represents the red\green\blue sub-pixel 21 respectively, and "+/-" represents the polarity of the voltage signal charged in the sub-pixel 21 respectively, for example "+" represents the first voltage signal, and "-" represents the second voltage signal. The "up/down" represents the position of the thin film transistor in the subpixel 21, wherein the subpixel 21 with the thin film transistor located below is the first subpixel 211, and the subpixel 21 with the thin film transistor located above is the second subpixel 212. As can be seen from fig. 8a and 9a, "R + up" is counteracted by "R-up," R + down "is counteracted by" R-down, "G + up" is counteracted by "G-up," G + down "is counteracted by" G-down, "B + up" is counteracted by "B-up," B + down "is counteracted by" B-down. That is, for each color of the sub-pixels 21, the number of the first sub-pixels 211 charged with the first voltage signal and the number of the first sub-pixels 211 charged with the second voltage signal are the same, and the number of the second sub-pixels 212 charged with the first voltage signal and the number of the second sub-pixels 212 charged with the second voltage signal are the same. Therefore, the sub-pixels 21 of the frame can be offset in pairs, and the next frame is also the same, so that the difference of uneven bright display and uneven dark display between two frames is avoided, and the problem of screen flashing can be improved.

In some embodiments, at the second inversion driving timing, the sub-pixels 21 of at least one color satisfy the following relationship in each frame:

the number of the first sub-pixels 211 charged with the third voltage signal is the same as the number of the first sub-pixels 211 charged with the fourth voltage signal, the number of the second sub-pixels 212 charged with the third voltage signal is the same as the number of the second sub-pixels 212 charged with the fourth voltage signal, and the third voltage signal and the fourth voltage signal are voltage signals with opposite polarities. For example, the third voltage signal and the fourth voltage signal are each voltage signals charged into the sub-pixel 21 through the data line.

In the embodiment of the present disclosure, the second inversion driving timing may be a 1+2 dot inversion driving timing, and the active level signals are sequentially supplied to the plurality of rows of gate lines 22 at the 1+2 dot inversion driving timing, wherein the data voltage signals having positive polarities are supplied to the data lines 23 of the odd columns and the data voltage signals having negative polarities are supplied to the data lines 23 of the even columns when the active level signals are supplied to the 1 st row of gate lines 22. When the active level signal is supplied to the 2 nd row gate line 22, the data voltage signal having a negative polarity is supplied to the data lines 23 of the odd columns, and the data voltage signal having a positive polarity is supplied to the data lines 23 of the even columns. When the active level signal is supplied to the 3 rd row gate line 22, the data voltage signal having a negative polarity is supplied to the data lines 23 of the odd columns, and the data voltage signal having a positive polarity is supplied to the data lines 23 of the even columns. In the case of supplying the active level signal to the 4 th row gate line 22, the data voltage signal having the positive polarity is supplied to the data lines 23 of the odd columns, the data voltage signal having the negative polarity is supplied to the data lines 23 of the even columns, and so on. In one frame, the polarity of the voltage charged in each sub-pixel 21 in the display substrate is as shown in fig. 8 b.

As shown in fig. 8B and 9B, taking an example that each group of sub-pixels includes four sub-pixels 21, under the 102a detection frame, there are 2 "r+up", 2 "R-up", 2 "r+down", 2 "R-down", 2 "g+up", 2 "G-up", 2 "g+down", 2 "G-down", 2 "b+up", 2 "B-up", 2 "b+down", and 2 "B-down", respectively. Wherein "R\G\B" represents red\green\blue sub-pixels respectively, "+/-" represents the polarity of the voltage signal charged by sub-pixel 21 respectively, e.g., "+" represents the third voltage signal and "-" represents the fourth voltage signal. The "up/down" represents the position of the thin film transistor in the sub-pixel, wherein the sub-pixel 21 with the thin film transistor located below is the first sub-pixel 211, and the sub-pixel 21 with the thin film transistor located above is the second sub-pixel 212. As can be seen from fig. 8B and 9B, "R + up" is counteracted by "R-up," R + down "is counteracted by" R-down, "G + up" is counteracted by "G-up," G + down "is counteracted by" G-down, "B + up" is counteracted by "B-up," B + down "is counteracted by" B-down. That is, for each color of the sub-pixels 21, the number of the first sub-pixels 211 charged with the third voltage signal and the number of the first sub-pixels 211 charged with the fourth voltage signal are the same, and the number of the second sub-pixels 212 charged with the third voltage signal and the number of the second sub-pixels 212 charged with the fourth voltage signal are the same. Therefore, the sub-pixels 21 of the frame can be offset in pairs, and the next frame is also the same, so that the difference of uneven bright display and uneven dark display between two frames is avoided, and the problem of screen flashing can be improved.

In the embodiments of the present disclosure, the frequency of polarity inversion may be reduced by the 1+2 dot inversion driving timing, so that power consumption may be reduced. Meanwhile, in the 1+2 dot inversion driving timing, the polarity of the voltage signal charged in each sub-pixel 21 is different from the polarity of the voltage signal charged in the four sub-pixels 21 adjacent to the same, so that a better image display effect can be achieved.

In other embodiments, other inversion driving methods may be used, as long as the number of the first sub-pixels 211 charged with the voltage signal having the positive polarity is the same as the number of the first sub-pixels 211 charged with the voltage signal having the negative polarity, and the number of the second sub-pixels 212 charged with the voltage signal having the positive polarity is the same as the number of the second sub-pixels 212 charged with the voltage signal having the negative polarity.

In some embodiments, in at least one group of subpixels, the first subpixel 211 is connected to the gate line 22 of the n-th row, and the second subpixel 212 is connected to the gate line 22 of the n-1 th row. That is, for a group of sub-pixels, the thin film transistors of the plurality of sub-pixels 21 are arranged in a "top-down-top-down" manner.

In some embodiments, at least one group of subpixels comprises two first subpixels 211 and two second subpixels 212, i.e. each group of subpixels comprises four subpixels 21. Wherein, the colors displayed by the two first sub-pixels 211 are different, and the colors displayed by the two second sub-pixels 212 are the same.

For example, in a group of subpixels, two first subpixels 211 are respectively a green subpixel 21G and a blue subpixel 21B, and two second subpixels 212 are respectively a red subpixel 21R. For the other group of subpixels, the two first subpixels 211 are respectively a blue subpixel 21B and a red subpixel 21R, and the two second subpixels 212 are both green subpixels 21G.

Fig. 10 schematically illustrates a second schematic view of a display substrate according to an embodiment of the disclosure, as illustrated in fig. 10, in some embodiments, at least one subpixel 21 includes a first electrode 213, the first electrode 213 including a first sub-electrode 213a and a second sub-electrode 213b, the first sub-electrode 213a extending along a first direction, the second sub-electrode 213b extending along a second direction, the first direction and the second direction intersecting. For example, the first electrode 231 is a stripe-shaped electrode, and one subpixel 21 includes a plurality of first electrodes 213, and the plurality of first electrodes 213 are spaced apart by slits 215.

In some embodiments, at least one subpixel 21 further comprises a second electrode and a liquid crystal layer, the first electrode 213 and the second electrode constituting drive electrodes configured to provide a drive electric field in response to a drive signal, the drive electric field configured to deflect liquid crystals in the liquid crystal layer. For example, one of the first electrode 213 and the second electrode is a pixel electrode, and the other is a common electrode.

In an embodiment of the disclosure, the first direction and the second direction have a preset included angle configured to: the first sub-electrode 213a and the second electrode are enabled to form a first domain electric field, the second sub-electrode 213b and the second electrode are enabled to form a second domain electric field, and directions of the first domain electric field and the second domain electric field are different. In the embodiment of the present disclosure, the preset included angle may be determined according to actual needs, which is not limited herein.

In some embodiments, the first electrode 213 further includes a first connection part 213c, the first sub-electrode 213a and the second sub-electrode 213b are connected by the first connection part 213c, the first connection part 213c is bent toward a third direction, and the third direction crosses the first direction and the second direction.

In the embodiment of the present disclosure, the third direction may be a row direction of the display substrate, and the first connection portion 213c may be bent toward the left side or the right side in fig. 10, and may specifically be determined according to the extending directions of the first sub-electrode 213a and the second sub-electrode 213b, and by using the first connection portion 213c, the first electrode 213 may be better bent, so that the electrical performance at the bending position of the first electrode 213 is prevented from being affected.

In some embodiments, the at least one column of data lines 23 includes a first segment 231 and a second segment 232, the extending direction of the first segment 231 is substantially the same as the extending direction of the first sub-electrode 213a, and the extending direction of the second segment 232 is substantially the same as the extending direction of the second sub-electrode 213 b.

In some embodiments, the data line 23 further includes a second connection portion 233, and the first section 231 and the second section 232 are connected by the second connection portion 233, and the second connection portion 233 is bent toward a fourth direction, which crosses the first direction and the second direction.

In the embodiment of the present disclosure, the fourth direction may be a row direction of the display substrate, and the second connection portion 233 may be bent toward the left or right in fig. 10, and may be specifically determined according to the extension directions of the first and

second segments

231 and 232. Optionally, the third direction and the fourth direction are co-directional. The second connection portion 233 can enable the data line 23 to be bent better, and the electrical performance of the bent portion of the data line 23 is prevented from being affected.

In some embodiments, at least one subpixel 21 further includes a thin film transistor 214, in which subpixel 21 a first electrode 214a of thin film transistor 214 is connected to data line 23, a gate electrode 214c of thin film transistor 214 is connected to gate line 22, a second electrode 214b of thin film transistor 214 includes a body portion 214b1 and a third connection portion 214b2, an orthographic projection of body portion 214b1 on the substrate overlaps at least partially an orthographic projection of an active layer of thin film transistor 214 on the substrate, for example, the active layer of thin film transistor 214 includes a first electrode contact region connected to first electrode 214a through a first via, a second electrode contact region connected to second electrode 214b through a second via, and a channel region between the first electrode contact region and the second electrode contact region. The body portion 214b1 may partially overlap the second-stage contact region. The orthographic projection of the third connection portion 214b2 on the substrate overlaps at least partially with the orthographic projection of the first electrode 213 on the substrate, and is connected to the first electrode 213. In at least one group of the sub-pixels 21, the third connection portion 214b2 of the first sub-pixel 211 extends toward a direction approaching the first sub-pixel 211 adjacent to the first sub-pixel 211, and the third connection portion 214b2 of the second sub-pixel 212 extends toward a direction away from the first sub-pixel 211 adjacent to the second sub-pixel 212.

For example, as shown in fig. 10, each group includes two first sub-pixels 211 and two second sub-pixels 212, the third connection portion 214b2 of the second sub-pixel 212 on the left side extends toward the left side, the third connection portion 214b2 of the second sub-pixel 212 on the right side extends toward the right side, the third connection portion 214b2 of the first sub-pixel 211 on the left side extends toward the right side, and the third connection portion 214b2 of the first sub-pixel 212 on the right side extends toward the left side.

In some embodiments, at least one column of data lines 23 includes a fourth connection portion 234 and a fifth connection portion 235. The fourth connection portion 234 is connected to one first subpixel 211 in the m-1 row of subpixels 21, the fifth connection portion 235 is connected to one second subpixel 212 in the m-1 row of subpixels 21, the orthographic projection of the fourth connection portion 234 on the substrate is located on one side of the orthographic projection of the fifth connection portion 235 on the substrate, which is close to the orthographic projection of the m-1 row of subpixels 21 on the substrate, and m is a positive integer. For example, as shown in fig. 10, the fourth connecting portion 234 is located below the fifth connecting portion 235.

In some embodiments, the display substrate further includes a first gate driving circuit for providing an electrical signal to the gate lines 22 of the odd numbered rows and a second gate driving circuit for providing an electrical signal to the gate lines 22 of the even numbered rows.

The embodiment of the disclosure also provides a display panel, which comprises the display substrate.

The embodiment of the disclosure also provides a display device comprising the display panel. The display device of the embodiment of the disclosure can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Those skilled in the art will appreciate that the features recited in the various embodiments of the disclosure and/or in the claims may be provided in a variety of combinations and/or combinations, even if such combinations or combinations are not explicitly recited in the disclosure. In particular, the features recited in the various embodiments of the present disclosure and/or the claims may be variously combined and/or combined without departing from the spirit and teachings of the present disclosure. All such combinations and/or combinations fall within the scope of the present disclosure.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A display substrate, comprising:

2. The display substrate according to claim 1, wherein at least one of the sub-pixels of one color satisfies the following relationship in each frame of the screen at the first inversion driving timing:

3. The display substrate according to claim 2, wherein at least one of the sub-pixels of one color satisfies the following relationship in each frame of the screen at the second inversion driving timing:

4. The display substrate of claim 1, wherein in at least one group of subpixels, the first subpixel is connected to the gate line of the n-th row, and the second subpixel is connected to the gate line of the n-1 th row.

5. The display substrate of claim 1, wherein at least one group of subpixels comprises two of the first subpixels and two of the second subpixels, wherein the two first subpixels are different in color and the two second subpixels are the same in color.

6. The display substrate according to any one of claims 1 to 5, wherein at least one of the sub-pixels comprises a first electrode comprising a first sub-electrode extending in a first direction and a second sub-electrode extending in a second direction, the first direction and the second direction intersecting.

7. The display substrate according to claim 6, wherein the first electrode further comprises a first connection portion through which the first sub-electrode and the second sub-electrode are connected, the first connection portion being bent toward a third direction intersecting the first direction and the second direction.

8. The display substrate of claim 6, wherein at least one of the sub-pixels further comprises a second electrode and a liquid crystal layer, the first electrode and the second electrode constituting a drive electrode configured to provide a drive electric field in response to a drive signal, the drive electric field configured to deflect liquid crystals in the liquid crystal layer.

9. The display substrate of claim 6, wherein at least one column of data lines comprises a first segment and a second segment, the first segment extending in substantially the same direction as the first sub-electrode, and the second segment extending in substantially the same direction as the second sub-electrode.

10. The display substrate according to claim 9, wherein the data line further comprises a second connection portion through which the first segment and the second segment are connected, the second connection portion being bent toward a fourth direction intersecting the first direction and the second direction.

11. The display substrate according to claim 6, wherein at least one of the sub-pixels further comprises a thin film transistor in which a first electrode of the thin film transistor is connected to a data line and a gate electrode of the thin film transistor is connected to a gate line, a second electrode of the thin film transistor includes a body portion and a third connection portion, an orthographic projection of the body portion on the substrate at least partially overlaps an orthographic projection of an active layer of the thin film transistor on the substrate, and an orthographic projection of the third connection portion on the substrate at least partially overlaps an orthographic projection of the first electrode on the substrate;

12. The display substrate according to any one of claims 1 to 5, wherein at least one column of data lines includes a fourth connection portion and a fifth connection portion;

13. The display substrate according to any one of claims 1 to 5, further comprising a first gate driving circuit for supplying an electric signal to gate lines of an odd-numbered row and a second gate driving circuit for supplying an electric signal to gate lines of an even-numbered row.

14. A display panel, comprising: the display substrate of any one of claims 1 to 13.

15. A display device, comprising: the display panel of claim 14.