CN116056530A

CN116056530A - Display panel manufacturing method and display device

Info

Publication number: CN116056530A
Application number: CN202310169080.2A
Authority: CN
Inventors: 方金钢; 丁录科; 成军; 周斌; 赵策; 程磊磊
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2023-02-22
Filing date: 2023-02-22
Publication date: 2023-05-02

Abstract

The embodiment of the application provides a preparation method of a display panel and a display device, which belong to the technical field of display, and the preparation method comprises the following steps: providing a substrate; forming at least one protruding structure on one side of the substrate base plate; forming a flat layer on one side of the substrate, wherein the orthographic projection of the flat layer on the substrate and the orthographic projection of the convex structure on the substrate are not overlapped; forming an anode layer on one side of the flat layer, which is away from the substrate, and forming an auxiliary electrode layer on one side of the protruding structure, which is away from the substrate; the orthographic projection of the anode layer on the substrate and the orthographic projection of the auxiliary electrode layer on the substrate are not overlapped, and the anode layer and the auxiliary electrode layer are arranged on the same layer. According to the preparation method of the display panel and the display device, the preparation process steps of the auxiliary electrode in the display panel can be reduced, and the production efficiency and the product yield of the display panel are improved.

Description

Display panel manufacturing method and display device

Technical Field

The embodiment of the application relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device.

Background

Recently, large-sized OLED (Organic Light-Emitting Diode) products are becoming new growing hot spots due to their high contrast and self-luminescence. Whereas for large size OLEDs, the top-emitting structure has a higher aperture ratio and higher pixels than the bottom-emitting structure.

In the design of display products with oversized OLED top-emission structures, auxiliary electrode technology must be used to reduce the voltage drop at the cathode of the thin film transistor, so the method of cathode bridging auxiliary electrode is an important technology.

At present, the forming method of the auxiliary electrode needs to go through a plurality of deposition processes, a mask process and an etching process, which results in the reduction of the production efficiency and the product yield of the display panel.

Disclosure of Invention

The embodiment of the application provides a preparation method of a display panel and a display device, and aims to reduce preparation process steps of auxiliary electrodes in the display panel and improve production efficiency and product yield of the display panel.

An embodiment of the present application provides a method for manufacturing a display panel, where the method includes:

providing a substrate;

forming at least one protruding structure on one side of the substrate base plate;

forming a flat layer on one side of the substrate, wherein the orthographic projection of the flat layer on the substrate is not overlapped with the orthographic projection of the raised structure on the substrate;

forming an anode layer on one side of the flat layer, which is away from the substrate, and forming an auxiliary electrode layer on one side of the protruding structure, which is away from the substrate;

the orthographic projection of the anode layer on the substrate is not overlapped with the orthographic projection of the auxiliary electrode layer on the substrate, and the anode layer and the auxiliary electrode layer are arranged on the same layer.

Optionally, the bump structure includes a first metal layer, a second metal layer, and a third metal layer that are stacked, where the first metal layer is disposed near the substrate;

wherein, the orthographic projection of the second metal layer on the substrate is positioned in the orthographic projection range of the first metal layer and the third metal layer on the substrate.

Optionally, a step of forming a planarization layer on one side of the substrate base plate, the preparation method includes:

crystallizing the first metal layer and the third metal layer of the bump structure.

Optionally, the anode layer includes a fourth metal layer, a fifth metal layer, and a sixth metal layer that are stacked, where the fourth metal layer is disposed near the substrate;

wherein the thickness of the fifth metal layer is smaller than the thickness of the second metal layer.

Optionally, an anode layer is formed on a side of the flat layer away from the substrate, and an auxiliary electrode layer is formed on a side of the bump structure away from the substrate, and the preparation method includes:

and etching the fourth metal layer, the fifth metal layer and the sixth metal layer sequentially through a wet etching process to obtain an anode pattern and an auxiliary electrode pattern.

Optionally, in the step of etching the fifth metal layer through a wet etching process, the preparation method further includes:

and carrying out back etching on the second metal layer, so that the orthographic projection of the second metal layer on the substrate is positioned in the orthographic projection range of the first metal layer and the third metal layer on the substrate.

Optionally, the second metal layer has a thickness of greater than or equal to

And less than or equal to

Optionally, the thickness of the fifth metal layer is greater than or equal to 200nm and less than or equal to 1000nm.

Optionally, the thickness of the fourth metal layer is greater than or equal to

And is less than or equal to->

Optionally, the thickness of the planar layer is greater than or equal to 2000nm and less than or equal to 3500nm.

Optionally, the materials of the first metal layer and the third metal layer include: ITO;

the material of the second metal layer comprises Cu/MoNb, al and Mo.

Optionally, an anode layer is formed on a side of the flat layer away from the substrate, and after the step of forming an auxiliary electrode layer on a side of the bump structure away from the substrate, the preparation method further includes:

sequentially forming a light-emitting layer and a cathode layer on one side of the anode layer and the auxiliary electrode layer, which is away from the substrate;

wherein the cathode layer is in metal connection with the auxiliary electrode layer.

Optionally, the bump structure includes a seventh metal layer and an eighth metal layer that are stacked, where the seventh metal layer is disposed near the substrate;

the seventh metal layer comprises a first part and a second part which are independent of each other, wherein the orthographic projection of the first part on the substrate base plate covers the orthographic projection of the flat layer on the substrate base plate.

Optionally, the anode layer includes a ninth metal layer and a tenth metal layer that are stacked, and the ninth metal layer is disposed near the substrate.

A second aspect of the embodiments of the present application provides a display device, including a display panel, where the display panel is prepared by the method for preparing a display panel as provided in the first aspect of the embodiments of the present application.

The beneficial effects are that:

the application provides a preparation method of a display panel and a display device, wherein at least one protruding structure and a flat layer are respectively formed on one side of a substrate, so that orthographic projection of the protruding structure on the substrate and orthographic projection of the flat layer on the substrate are not overlapped, then an anode layer is formed on one side of the flat layer, which is away from the substrate, and an auxiliary electrode layer is formed on one side of the protruding structure, which is away from the substrate, and the anode layer and the auxiliary electrode layer are arranged on the same layer; therefore, when the display panel is prepared, the anode layer can be disconnected at the position of the convex structure by utilizing the convex structure while the anode layer is formed, and the auxiliary electrode layer is prepared together, so that the preparation steps of the auxiliary electrode layer are simplified, and the production efficiency and the product yield of the display panel are improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart illustrating steps of a method for manufacturing a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a display panel manufactured by a manufacturing method of a substrate according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a manufacturing process of a bump structure in a manufacturing method of a display panel according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating a structure of a flat layer manufactured by a method for manufacturing a display panel according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating a structure of an anode layer and an auxiliary electrode layer in a method for fabricating a display panel according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a manufacturing method of a display panel according to an embodiment of the present disclosure, in which fabrication of a bump structure including a seventh metal layer and an eighth metal layer is completed;

fig. 7 is a schematic structural diagram illustrating a manufacturing method of a display panel according to an embodiment of the present application, in which fabrication of an anode layer and an auxiliary electrode layer including a ninth metal layer and a tenth metal layer is completed.

Reference numerals illustrate: 11. a substrate base; 111. a substrate; 112. a light shielding layer; 113. a buffer layer; 114. an active layer; 115. a gate insulating layer; 116. a gate; 117. an interlayer dielectric layer; 118. a source/drain electrode; 119. a passivation layer; 20. a bump structure; 201. a first metal layer; 202. a second metal layer; 203. a third metal layer; 204. a seventh metal layer; 2041. a first portion; 2042. a second portion; 205. an eighth metal layer; 30. a flat layer; 40. an anode layer; 401. a fourth metal layer; 402. a fifth metal layer; 403. a sixth metal layer; 404. a ninth metal layer; 405. a tenth metal layer; 50. and an auxiliary electrode layer.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In the related art, in the process of manufacturing a display panel, generally, the preparation of a flat layer is firstly completed, then the passivation layer is etched to complete the patterning of the passivation layer, and then the preparation of an auxiliary electrode and an anode is respectively completed after a metal layer is deposited.

Because the metal structures of the auxiliary electrode and the anode are complex, the production takt of the display panel is slow due to the fact that the metal structures are required to be subjected to multiple deposition, masking and etching processes, and the yield of the display panel is low due to the complex processes.

In view of this, an embodiment of the present application proposes a method for manufacturing a display panel and a display device, where at least one protrusion structure and a flat layer are formed on one side of a substrate respectively, so that orthographic projection of the protrusion structure on the substrate and orthographic projection of the flat layer on the substrate do not overlap, then an anode layer is formed on a side of the flat layer facing away from the substrate, an auxiliary electrode layer is formed on a side of the protrusion structure facing away from the substrate, and the anode layer and the auxiliary electrode layer are arranged on the same layer; therefore, when the display panel is prepared, the anode layer can be disconnected at the position of the convex structure by utilizing the convex structure while the anode layer is formed, and the auxiliary electrode layer is prepared together, so that the preparation steps of the auxiliary electrode layer are simplified, and the production efficiency and the product yield of the display panel are improved.

Fig. 1 shows a flow chart of steps of a method for manufacturing a display panel. Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a display panel, including:

step 101: a substrate base 11 is provided.

Specifically, the substrate 11 may include a TFT (Thin Film Transistor ) substrate. As shown in fig. 2, the TFT substrate may include a substrate 111, a light shielding layer 112, a buffer layer 113, an active layer 114, a gate insulating layer 115, a gate 116, an interlayer dielectric layer 117, and a source/drain electrode 118 from bottom to top.

The material of the substrate 111 may include glass, and the thickness of the substrate 111 may be greater than or equal to 50 μm and less than or equal to 1000 μm. Illustratively, the thickness of the substrate 111 may be 50 μm, 100 μm, 200 μm, 500 μm, 1000 μm, etc., and may be selected by those skilled in the art according to actual requirements.

The light shielding layer 112 is disposed on the substrate 111, the light shielding layer 112 may be deposited by a sputtering process, patterning of the light shielding layer 112 is completed after a photolithography process and a wet etching process, and then photoresist on the surface of the light shielding layer 112 is stripped to complete the preparation of the light shielding layer 112.

The buffer layer 113 may be deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition ) process; the material of the buffer layer 113 may include SiN _x 、SiO _x Or SiO _x N _y One or more of (a) and (b); the thickness of the buffer layer 113 may be 150nm or more and 500nm or less; illustratively, the thickness of the buffer layer 113 may be 150nm, 200nm, 300nm, 400nm, 500nm, etc., and those skilled in the art may select according to actual requirements. The buffer layer 113 may prevent impurities on the substrate 111 from diffusing into the active layer 114.

The active layer 114 may be formed on a side of the buffer layer 113 facing away from the substrate 111 through a sputtering process, and then patterning of the active layer 114 is completed through a photolithography process and a wet etching process, and photoresist on the surface of the active layer 114 is stripped, and the oxide of the active layer 114 may include an amorphous oxide such as IGZO, znON, ITZO.

The gate insulating layer 115 may be formed on a side of the active layer 114 facing away from the buffer layer 113 through a CVD (Chemical Vapor Deposition ) process; the gate electrode 116 may be formed on a side of the gate insulating layer 115 facing away from the active layer 114 through a sputtering process, patterning of the gate electrode 116 is completed through a photolithography process and a wet etching process, while photoresist is kept from being stripped, patterning of the gate insulating layer 115 is completed through a dry etching process continuously using the photoresist on the gate electrode 116 as a mask; the material of the gate 116 may include Al, mo, cr, cu, ti, etc.; the thickness of the gate 116 may be greater than or equal to 200nm and less than or equal to 1000nm. Illustratively, the thickness of the gate 116 may be 200nm, 300nm, 500nm, 800nm, 1000nm, etc., and may be selected by those skilled in the art according to actual requirements.

NH may be used prior to forming interlayer dielectric layer 117 ₃ 、N ₂ 、H ₂ Any one of the gases performs a conductive treatment on the oxide of the active layer 114 exposed to the outside to reduce an ohmic contact resistance with the source and drain electrodes 118; then, an interlayer dielectric layer 117 can be prepared by deposition through a PECVD process, an ILD hole and a CNT hole pattern are defined through a photoetching process, and a contact via hole between a source drain electrode 118 and an active layer 114 is obtained through a dry etching process; the material of interlayer dielectric layer 117 may include SiN _x Or SiO _x The method comprises the steps of carrying out a first treatment on the surface of the The interlayer dielectric layer 117 may have a single-layer film structure or a multilayer film structure.

The source/drain electrode 118 may be formed on a side of the interlayer dielectric layer 117 facing away from the gate electrode 116 through a sputtering process, and patterning of the source/drain electrode 118 is completed through a photolithography process and a wet etching process, and materials of the source/drain electrode 118 may include Al, mo, cr, cu, ti and the like; the thickness of the source drain 118 may be greater than or equal to 200nm and less than or equal to 1000nm. Illustratively, the thickness of the source and drain electrodes 118 may be 200nm, 300nm, 500nm, 800nm, 1000nm, etc., and those skilled in the art may select according to actual requirements.

Step 102: at least one bump structure 20 is formed on one side of the substrate 11.

Specifically, referring to fig. 3, the bump structure 20 may be deposited by a sputtering process. The bump structure 20 may include a first metal layer 201, a second metal layer 202, and a third metal layer 203 that are stacked, wherein a material of the first metal layer 201 and the third metal layer 203 may include ITO (indium tin oxide), a material of the second metal layer 202 may include Cu/MoNb, al, mo, and the like. Meanwhile, after the deposition is completed, patterning of the bump structure 20 needs to be completed through one more photolithography process and a three-step wet etching process performed in the order of the first metal layer 201, the second metal layer 202, and the third metal layer 203.

Also, since the bump structures 20 correspond to auxiliary electrodes, it is generally necessary to form a plurality of bump structures 20 on the substrate 11, each bump structure 20 corresponding to an auxiliary electrode individually.

In the embodiment of the present application, the bump structure 20 is an ITO/Cu/MoNb/ITO structure; in other embodiments, the bump structure 20 may also be an ITO/MoNb/Cu/ITO structure.

Step 103: a flat layer 30 is formed on one side of the substrate 11, and the orthographic projection of the flat layer 30 on the substrate 11 does not overlap with the orthographic projection of the bump structure 20 on the substrate 11.

Specifically, referring to fig. 4, the planarization layer 30 may be formed on one side of the substrate 11 through a doctor blade process, and then exposed to a pattern of cured pixel areas through pre-baking, exposure, and development, and then post-baking at 230 degrees to remove water and organic solvents, thereby completing the preparation of the planarization layer 30; the material of the planarization layer 30 may include a resin; the thickness of the planarization layer 30 may be 2000nm or more and 3500nm or less. Illustratively, the thickness of the planarization layer 30 may be 2000nm, 2500nm, 3000nm, 3500nm, etc., and those skilled in the art may select according to actual requirements.

In which the first and

third metal layers

201 and 203 of the bump structure 20 may be crystallized in the post-baking process of the flat layer 30, thereby preventing corrosion of the first and

third metal layers

201 and 203 caused in the etching process of the anode layer 40.

Step 104: forming an anode layer 40 on a side of the flat layer 30 facing away from the substrate 11, and forming an auxiliary electrode layer 50 on a side of the bump structure 20 facing away from the substrate 11; wherein, the front projection of the anode layer 40 on the substrate 11 and the front projection of the auxiliary electrode layer 50 on the substrate 11 do not overlap, and the anode layer 40 and the auxiliary electrode layer 50 are arranged in the same layer.

Specifically, referring to fig. 5, the anode layer 40 and the auxiliary electrode layer 50 may be formed by deposition through a sputtering process, the anode layer 40 may include a fourth metal layer 401, a fifth metal layer 402, and a sixth metal layer 403 which are stacked, wherein materials of the fourth metal layer 401 and the sixth metal layer 403 may include ITO (indium tin oxide), materials of the fifth metal layer 402 may include MoCu/MoNb, al, mo, cr, cu, ti, and the like; meanwhile, since the anode layer 40 and the auxiliary electrode layer 50 are provided in the same layer, that is, the anode layer 40 and the auxiliary electrode layer 50 are manufactured in the same step using the same material and the same process, the auxiliary electrode layer 50 also includes the fourth metal layer 401, the fifth metal layer 402, and the sixth metal layer 403.

And, after the deposition of the anode layer 40 and the auxiliary electrode layer 50 is completed, it is necessary to complete the overlap pattern of the anode pattern and the auxiliary electrode through one photolithography process and a three-step wet etching process performed in the order of the fourth metal layer 401, the fifth metal layer 402 and the sixth metal layer 403; wherein the landing pattern of the auxiliary electrode includes a single bump structure 20 and an auxiliary electrode layer 50 attached to the bump structure 20 and covering the bump structure 20.

In the bump structure 20, the thickness of the second metal layer 202 may be greater than or equal to

And less than or equal to

Thus, in the process of forming the anode layer 40, the anode layer 40 may be cut off by the bump structure 20 (i.e., the anode layer 40 may be broken at the bump structure 20, so that the anode layer 40 covered on the bump structure 20 serves as the auxiliary electrode layer 50), so that the anode layer 40 cannot completely cover the bump structure 20, and further, the auxiliary electrode layer 50 may play a role in auxiliary conduction. The thickness of the second metal layer 202 may be, for example +>

Etc., and may be selected by those skilled in the art based on actual needs.

According to the preparation method, the preparation of the anode and the auxiliary electrode is completed in one step, so that the preparation steps of the auxiliary electrode are simplified, and the production efficiency and the product yield of the display panel are improved.

In addition, in the related art, after an annealing process is required to be performed on the metal layer deposited in the previous step before the auxiliary electrode and the anode are manufactured, and in the process, if the metal of the auxiliary electrode is directly deposited on the annealed metal layer, the bulge defect is easy to occur; in the embodiment of the present application, the fifth metal layer 402 is deposited on the fourth metal layer 401 that is not subjected to the annealing process, so that the bulge defect is not generated.

Meanwhile, crystallization of the first metal layer 201 and the third metal layer 203 in the bump structure 20 is completed by means of the post-baking process of the planarization layer 30, and the second metal layer 202 can be prevented from being reversely etched in the process of forming the bump structure 20. In this embodiment, when the fifth metal layer 402 is etched, the second metal layer 202 of the bump structure 20 may be etched back, so that the bump structure 20 is changed into an i-shaped structure, and the orthographic projection of the second metal layer 202 on the substrate 11 is located in the orthographic projection range of the first metal layer 201 and the third metal layer 203 on the substrate 11.

In the present embodiment, the thickness of the fifth metal layer 402 is greater than or equal to 200nm and less than or equal to 1000nm. Illustratively, the thickness of the fifth metal layer 402 may be 200nm, 300nm, 500nm, 800nm, 1000nm, etc., and may be selected by those skilled in the art according to actual requirements. By reducing the thickness of the fifth metal layer 402, dark spots caused during Cu deposition can be reduced when the material of the fifth metal layer 402 is Cu/MoNb.

In the embodiment of the present application, the thickness of the fourth metal layer 401 may be greater than or equal to

And is less than or equal to->

The thickness of the fourth metal layer 401 may be, for example +>

Etc., and may be selected by those skilled in the art based on actual needs. By reducing the thickness of the fourth metal layer 401, the etching time can be reduced.

Meanwhile, in the embodiment of the present application, before the step of forming at least one bump structure 20 on one side of the substrate 11, the preparation method further includes:

a passivation layer 119 is formed on one side of the substrate 11, and the passivation layer 119 is disposed to cover the substrate 11.

And, before the step of forming the anode layer 40 on the side of the planarization layer 30 facing away from the passivation layer 119, the manufacturing method further includes:

the passivation layer 119 is patterned by an etching process.

Specifically, the passivation layer 119 may be deposited by a CVD process, and the material of the passivation layer 119 may include SiN _x 、SiO _x Or SiO _x N _y Etc. Patterning of the passivation layer 119 may be accomplished through a photolithography process and an etching process. By etching the passivation layer 119, the anode layer 40 can be connected to the source and drain electrodes 118, and the etching time of the fourth metal layer 401 can be reduced due to the reduced thickness of the fourth metal layer 401, so that metal corrosion in the passivation layer 119 hole can be improved.

In an alternative embodiment, the anode layer 40 is formed on the side of the flat layer 30 facing away from the substrate 11, and after the step of forming the auxiliary electrode layer 50 on the side of the bump structure 20 facing away from the substrate 11, the preparation method further comprises:

step 105: a light-emitting layer and a cathode layer are sequentially formed on the side of the anode layer 40 and the auxiliary electrode layer 50 facing away from the substrate 11, wherein the cathode layer is in metal connection with the auxiliary electrode layer 50.

Specifically, the light emitting layer may include a hole injection layer, a hole transport layer, a light emitting material layer, and an electron transport layer, which are sequentially stacked from bottom to top, wherein the hole injection layer is disposed close to the substrate 11.

The hole injection layer may be a material that facilitates control of hole injection speed, such as CuPc or the like; the hole transport layer may be a material having high thermal stability, facilitating hole transport, such as NPB (N, N ' - (1-naphthyl) -N, N ' -diphenyl-4, 4' -biphenyldiamine), or the like; the light emitting material layer may be a material having high light emitting efficiency, such as Alq 3; the electron transport layer may be a material having high thermal stability, facilitating electron transport, such as PBD (2- (4-biphenyl) -5- (4-t-butyl) phenyl-1, 3, 4-oxadiazole) and the like.

Under external driving, electrons pass through the electron transport layer from the cathode layer to the light emitting material layer, holes pass through the hole injection layer and the hole transport layer from the anode layer 40 to the light emitting material layer, electrons and holes interact at the light emitting material layer to emit light, and light enters the cathode layer through the electron transport layer and exits from the light emitting region of the cathode layer.

In addition, a pixel defining layer may be further included between the light emitting layer and the anode layer 40, and the pixel defining layer may define a plurality of light emitting regions and non-light emitting regions on the substrate 11, wherein the position of the anode corresponds to the position of the light emitting region, and the position of the auxiliary electrode corresponds to the position of the non-light emitting region, thereby avoiding the auxiliary electrode from affecting the light emitting effect of the product.

In an alternative embodiment, the embodiment of the present application further provides a manufacturing method of a display panel, in which, referring to fig. 6, the bump structure 20 includes a seventh metal layer 204 and an eighth metal layer 205 that are stacked, and the seventh metal layer 204 is disposed near the substrate 11.

Specifically, in this manufacturing method, the manufacturing of the flat layer 30 precedes the manufacturing of the bump structure 20, so that the seventh metal layer 204 may cover the flat layer 30, and the seventh metal layer 204 may be used as the bottom metal layer in the anode layer 40.

Further, referring to fig. 6, the seventh metal layer 204 includes a first portion 2041 and a second portion 2042 that are independent of each other, that is, the positions of the first portion 2041 and the second portion 2042 in the display panel are independent of each other. Wherein the orthographic projection of the first portion 2041 onto the substrate 11 covers the orthographic projection of the flat layer 30 onto the substrate 11. Thus, the first portion 2041 of the seventh metal layer 204 may serve as a bottom metal layer of the anode layer 40 during subsequent formation of the anode layer 40. In particular implementations, the first portion 2041 and the second portion 2042 may be formed by a single photolithographic process through a halftone mask.

The material of the seventh metal layer 204 may include ITO, the material of the eighth metal layer 205 may include Cu/MoNb, al, mo, and the like.

Meanwhile, referring to fig. 7, in this embodiment, the anode layer 40 includes a ninth metal layer 404 and a tenth metal layer 405 which are stacked, wherein a material of the ninth metal layer 404 may include MoCu/MoNb, al, mo, cr, cu, ti and the like, and a material of the tenth metal layer 405 may include ITO. And since the anode layer 40 and the auxiliary electrode layer 50 are provided in the same layer, the auxiliary electrode layer 50 also includes a ninth metal layer 404 and a tenth metal layer 405.

Specifically, the anode layer 40 is formed on a side of the first portion 2041 of the seventh metal layer 204 facing away from the substrate 11, and the auxiliary electrode layer 50 is formed on a side of the eighth metal layer 205 facing away from the substrate 11. Thus, the first portion 2041, the ninth metal layer 404, and the tenth metal layer 405 of the seventh metal layer 204 may form a complete anode, and the second portion 2042, the eighth metal layer 205, the ninth metal layer 404, and the tenth metal layer 405 of the seventh metal layer 204 may form a complete auxiliary electrode.

By the preparation method, the preparation of the anode and the auxiliary electrode is completed in one step, so that the preparation steps of the auxiliary electrode are simplified, and the production efficiency and the product yield of the display panel are improved.

Meanwhile, the film layer at the hole of the passivation layer 119 is reduced by the preparation method, so that metal corrosion of the drain electrode 118 of the passivation layer 119 Kong Nayuan caused by multiple wet etching processes can be prevented.

Based on the same inventive concept, the embodiment of the application also discloses a display device, which comprises a display panel, wherein the display panel is prepared by the preparation method of the display panel.

Specifically, the display device may be a computer display, a television, a billboard, a laser printer with display function, a telephone, a cell phone, a personal digital assistant (Personal Digital Assistant, PDA), a laptop computer, a digital camera, a camcorder, a viewfinder, a vehicle, a large-area wall, a screen of a theater, a stadium sign, or the like.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

It should also be noted that, in this document, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, but do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Moreover, relational terms such as "first" and "second" may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions, or order, and without necessarily being construed as indicating or implying any relative importance. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device comprising the element.

The foregoing has outlined rather broadly the more detailed description of the present application, and the detailed description of the principles and embodiments herein may be better understood as being a limitation on the present application. Also, various modifications in the details and application scope may be made by those skilled in the art in light of this disclosure, and all such modifications and variations are not required to be exhaustive or are intended to be within the scope of the disclosure.

Claims

1. A method for manufacturing a display panel, the method comprising:

providing a substrate;

2. The method for manufacturing a display panel according to claim 1, wherein:

the bump structure comprises a first metal layer, a second metal layer and a third metal layer which are stacked, and the first metal layer is arranged close to the substrate;

3. The method of manufacturing a display panel according to claim 2, wherein the step of forming a flat layer on one side of the substrate base plate, the method comprising:

4. The method of manufacturing a display panel according to claim 2, wherein:

the anode layer comprises a fourth metal layer, a fifth metal layer and a sixth metal layer which are arranged in a stacked manner, and the fourth metal layer is arranged close to the substrate;

5. The method of manufacturing a display panel according to claim 4, wherein an anode layer is formed on a side of the flat layer facing away from the substrate, and an auxiliary electrode layer is formed on a side of the bump structure facing away from the substrate, the method comprising:

6. The method of manufacturing a display panel according to claim 5, wherein in the step of etching the fifth metal layer by a wet etching process, the method further comprises:

7. The method of manufacturing a display panel according to claim 2, wherein:

the thickness of the second metal layer is greater than or equal to

And is less than or equal to->

8. The method for manufacturing a display panel according to claim 4, wherein:

the thickness of the fifth metal layer is greater than or equal to 200nm and less than or equal to 1000nm.

9. The method for manufacturing a display panel according to claim 4, wherein:

the thickness of the fourth metal layer is greater than or equal to

And is less than or equal to->

10. The method for manufacturing a display panel according to any one of claims 1 to 9, wherein:

the thickness of the flat layer is 2000nm or more and 3500nm or less.

11. The method for manufacturing a display panel according to any one of claims 1 to 9, wherein:

the materials of the first metal layer and the third metal layer include: ITO;

the material of the second metal layer comprises Cu/MoNb, al and Mo.

12. The method of any one of claims 1 to 9, wherein after the step of forming an anode layer on a side of the flat layer facing away from the substrate and forming an auxiliary electrode layer on a side of the bump structure facing away from the substrate, the method further comprises:

13. The method for manufacturing a display panel according to claim 1, wherein:

the bump structure comprises a seventh metal layer and an eighth metal layer which are stacked, and the seventh metal layer is arranged close to the substrate;

14. The method of manufacturing a display panel according to claim 13, wherein:

the anode layer comprises a ninth metal layer and a tenth metal layer which are arranged in a stacked mode, and the ninth metal layer is arranged close to the substrate base plate.

15. A display device comprising a display panel prepared by the method of preparing a display panel according to any one of claims 1-14.