CN116056444A

CN116056444A - SRAM device and method of forming the same

Info

Publication number: CN116056444A
Application number: CN202111226881.5A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-10-21
Filing date: 2021-10-21
Publication date: 2023-05-02

Abstract

An SRAM device and method of forming the same, the method of forming comprising: providing a substrate, wherein the substrate comprises a first type device region and a second type device region, the first type SRAM device has the maximum channel width, the first type device region and the second type device region comprise a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region, laminated structures are formed on the substrate and comprise a first sacrificial layer and a channel layer, and the width of each laminated structure in the second type device region is equal to the preset width of the corresponding transistor region in the first type device region; performing channel width adjustment processing, and removing a part of the channel layer with the width in any one or two transistor areas of a transmission gate transistor area, a pull-down transistor area and a pull-up transistor area in the second type of device area; removing the first sacrificial layer after removing the channel layer with partial width; and after the first sacrificial layer is removed, forming a grid structure crossing the channel layer. The invention adopts the same design layout to form a laminated structure, thereby saving the design cost.

Description

SRAM device and method of forming the same

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to an SRAM device and a forming method thereof.

Background

With the continued development of digital integrated circuits, integrated memory on chip has become an important component in digital systems. SRAM (Static Random Access Memory ) is an integral part of on-chip memory because of its low power consumption and high speed. The SRAM can store data only by supplying power to the SRAM, and the SRAM does not need to be refreshed continuously.

The reliability of SRAM is critical to ensure stable and safe operation for electrical applications, and at present, the manufacturing process and the reliability verification process of SRAM are improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing an SRAM device and a forming method thereof, which saves design cost, simplifies verification flow and improves verification efficiency.

To solve the above problems, an embodiment of the present invention provides an SRAM device, including: a base including a substrate and a plurality of bottom fin portions protruding from the substrate and extending in a first direction, the base including a first type device region for forming a first type SRAM device having a maximum channel width and a second type device region for forming a second type SRAM device, each of the first and second type device regions including a plurality of memory cell regions including first and second sub-cell regions adjacent and centrally symmetric, each of the first and second sub-cell regions including a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region, the bottom fin portions of the same transistor region in the first and second type device regions having equal widths; a channel layer structure suspended above the bottom fin, the channel layer structure including one or more channel layers disposed at intervals along a longitudinal direction, the channel layer structure extending along the first direction, in the first device region, a sidewall of the channel layer along a second direction being flush with a sidewall of the bottom fin of the corresponding transistor region in the longitudinal direction, in the second device region, in any one or both of the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region, a sidewall of the channel layer being recessed inward with respect to a bottom fin sidewall of the corresponding transistor region along the second direction, the second direction being perpendicular to the first direction; and a gate structure on the substrate and crossing the channel layer structures along the second direction, wherein the gate structure comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer.

Correspondingly, the embodiment of the invention also provides a forming method of the SRAM device, which comprises the following steps: providing a substrate comprising a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device, the first type SRAM device having a maximum channel width, the first type device region and the second type device region each comprising a plurality of memory cell regions, the memory cell regions comprising first and second sub-cell regions that are contiguous and centrally symmetric, the first and second sub-cell regions each comprising a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region, the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region having a stack structure formed on the substrate that extends in a first direction, the stack structure comprising one or more stacked channel stacks comprising a first sacrificial layer and a channel layer on the first sacrificial layer, the stack structure comprising a channel region in the first direction, wherein the stack structure of each transistor region in the first type device region has a corresponding preset width, and the stack structure of each transistor region in the second type device region has a width that is equal to the corresponding transistor region in the preset width in the second type region; performing channel width adjustment processing, wherein in the second type device region, the channel layer with partial width is removed in a second direction in any one or two transistor regions of the transmission gate transistor region, the pull-down transistor region and the pull-up transistor region, and the second direction is perpendicular to the first direction; removing the first sacrificial layer in the channel region after removing the channel layer with partial width in the channel region; and after the first sacrificial layer in the channel region is removed, forming a gate structure crossing the channel layer in the channel region, wherein the gate structure comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the SRAM device provided by the embodiment of the present invention, in the first device region, a sidewall of the channel layer along a second direction is flush with a sidewall of a bottom fin portion of a corresponding transistor region in a longitudinal direction, and in the second device region, in any one or two transistor regions of the pass gate transistor region, the pull-down transistor region and the pull-up transistor region, the sidewall of the channel layer is recessed inward with respect to the sidewall of the bottom fin portion of the corresponding transistor region along the second direction; in the process of forming the SRAM device, a bottom fin portion and a stacked structure including a channel layer are generally formed in the same etching step, then the channel layer with a partial width is removed along the second direction, and the channel layer structure is formed, so that for different types of SRAM devices, the widths of the bottom fin portions of the same transistor region are consistent, that is, in the embodiment of the invention, for SRAM devices with different performance requirements, the stacked structure can be formed by using the same design layout, only according to the working current requirements of the second type SRAM device on each transistor region, in any one or two transistor regions of the transmission gate transistor region, the pull-down transistor region and the pull-up transistor region, the channel layer with a partial width is removed along the second direction, and the channel layer with a width smaller than the width of the bottom portion is formed.

In the forming method provided by the embodiment of the invention, the width of each laminated structure in the second type device region is equal to the preset width of the corresponding transistor region in the first type device region, after the laminated structure is formed, in the second type device region, in any one or two transistor regions of the pass gate transistor region, the pull-down transistor region and the pull-up transistor region, the channel layer with partial width is removed along the second direction, and for different types of SRAM devices, the laminated structure can be formed by adopting the same design layout, only the working current requirement of the second type SRAM device on each transistor region is needed, in any one or two transistor regions of the pass gate transistor region, the pull-down transistor region and the pull-up transistor region, the channel layer with partial width is removed along the second direction, the layout design is avoided for different types of SRAM devices, the design cost is saved, in the second type device region, the step of reducing the channel layer width along the second direction is reduced, and the verification of the SRAM devices is only needed after the step of forming the channel layer is simplified, and the verification of the first type SRAM device is required, and the reliability is improved.

Drawings

FIGS. 1-7 are schematic diagrams illustrating the structure of an SRAM device corresponding to each step in a method for forming the same;

FIGS. 8-12 are schematic diagrams of the structure of an embodiment of an SRAM device of the present invention;

FIGS. 13-15 are schematic diagrams of structures of another embodiment of an SRAM device of the present invention;

FIGS. 16-28 are schematic views illustrating the structure of the SRAM device according to the present invention corresponding to the steps in one embodiment of the method for forming the SRAM device;

FIGS. 29 through 30 are schematic views of the structure corresponding to the steps in another embodiment of the method for forming an SRAM device of the present invention;

fig. 31 to 33 are schematic structural views corresponding to steps in a method for forming an SRAM device according to another embodiment of the present invention.

Detailed Description

At present, the design cost of the SRAM device needs to be saved, the verification process needs to be simplified, and the verification efficiency needs to be improved. The design cost of the SRAM device is required to be saved, the verification process is required to be simplified, and the verification efficiency is required to be improved by combining the forming method of the SRAM device.

Fig. 1 to 7 are schematic structural diagrams corresponding to steps in a method for forming an SRAM device.

For convenience of illustration, fig. 1 shows only a substrate, fig. 2 is a top view of any one of the memory cells in the first type device region, fig. 3 (a) is a cross-sectional view of fig. 2 along the AA direction, fig. 3 (b) is a cross-sectional view of fig. 2 along the BB direction, fig. 4 is a top view of any one of the memory cells in the second type device region, fig. 5 (a) is a cross-sectional view of fig. 4 along the AA direction, fig. 5 (b) is a cross-sectional view of fig. 4 along the BB direction, fig. 6 is a top view of any one of the memory cells in the third type device region, fig. 7 (a) is a cross-sectional view of fig. 6 along the AA direction, and fig. 7 (b) is a cross-sectional view of fig. 6 along the BB direction.

Referring to fig. 1, a substrate 10 is provided that includes a first type device region 10P for forming a first type SRAM device, a second type device region 10D for forming a second type SRAM device, and a third type device region 10V for forming a third type SRAM device.

Referring to fig. 2, 4 and 6 in combination, the first, second and third

type device regions

10P, 10D and 10V each include a plurality of memory cell regions S including first and second sub-unit regions S1 and S2 adjacent to each other and center-symmetrical, and the first and second sub-unit regions S1 and S2 each include a pass gate transistor region PG, a pull-down transistor region PD and a pull-up transistor region PU, and the channel width ratios of the first, second and third type SRAM devices are different from each other in the pass gate transistor region PG, the pull-down transistor region PD and the pull-up transistor region PU.

Referring to fig. 2 and 3 in combination, a plurality of channel layers 23 are formed in the first device region 10P to be suspended above the substrate 10, the channel layers 23 being spaced apart, wherein the width ratio of the channel layers in the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:2:2; a gate structure 50 is formed on the substrate 10 across and around the plurality of channel layers 23, the channel layers 23 and gate structure 50 being used to construct the first type SRAM device.

In the first device region 10P, the width of the channel layer 23 is defined by a first layout.

Referring to fig. 4 and 5 in combination, in the second-type device region 10D, a plurality of channel layers 23 are formed to be suspended above the substrate 10, the channel layers 23 are spaced apart, wherein the width ratio of the channel layers in the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:1:1; a gate structure 50 is formed on the substrate 10 across and around the plurality of channel layers 23, the channel layers 23 and gate structure 50 being used to construct the second type SRAM device.

Wherein, in the second type device region 10D, the width of the channel layer 23 is defined by using a second layout.

Referring to fig. 6 and 7 in combination, in the third device region 10V, a plurality of channel layers 23 are formed to be suspended above the substrate 10, the channel layers 23 are spaced apart, wherein the width ratio of the channel layers in the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:1:2; a gate structure 50 is formed on the substrate 10 across and around the plurality of channel layers 23, the channel layers 23 and gate structure 50 being used to construct the third type of SRAM device.

Wherein, in the third type device region 10V, the width of the channel layer 23 is defined by a third layout.

According to the working current requirements of different types of SRAM devices on each transistor area, the channel width ratios of the first type of SRAM device, the second type of SRAM device and the third type of SRAM device in the pass gate transistor area PG, the pull-down transistor area PD and the pull-up transistor area PU are different, so that the first type of SRAM device is required to be formed by adopting a first layout, the second type of SRAM device is required to be formed by adopting a second layout, and the third type of SRAM device is required to be formed by adopting a third layout, that is, layout design is required to be performed on different types of SRAM devices, so that the design cost is greatly increased, and after different types of SRAM devices are formed, yield and reliability verification is required to be performed on the first type of SRAM device, the second type of SRAM device and the third type of SRAM device respectively, the verification process is complicated, and the verification efficiency is low.

In order to solve the technical problem, the embodiment of the invention provides a method for forming an SRAM device, wherein the width of each laminated structure in the second type device region is equal to the preset width of the corresponding transistor region in the first type device region, after forming the laminated structure, in the second type device region, in any one or two transistor regions of the pass gate transistor region, the pull-down transistor region and the pull-up transistor region, the channel layer with partial width is removed along the second direction, the laminated structure can be formed by adopting the same design layout for different types of SRAM devices, only the working current requirement of the SRAM device in each transistor region is required according to the second type of SRAM device, and in any one or two transistor regions of the pass gate transistor region, the pull-down transistor region and the pull-up transistor region, the channel layer with partial width is removed along the second direction, so that the layout design cost is avoided for different types of SRAM devices respectively, in the second type of SRAM device region, the second direction is reduced, the step width is reduced, and the channel efficiency is verified only after the second type of SRAM device is required, and the channel efficiency is verified.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 8 to 12 are schematic structural views of an embodiment of the SRAM device of the present invention, in which, for convenience of illustration, fig. 8 shows only a substrate, fig. 9 is a top view of any one of memory cells in a first type device region, fig. 10 (a) is a cross-sectional view along an AA direction of fig. 9, fig. 10 (b) is a cross-sectional view along a BB direction of fig. 9, fig. 11 is a top view of any one of memory cells in a second type device region, fig. 12 (a) is a cross-sectional view along an AA direction of fig. 11, and fig. 12 (b) is a cross-sectional view along a BB direction of fig. 11.

The SRAM device includes: a base 121 including a substrate 101 and a plurality of bottom fin regions 111 protruding from the substrate 101 and extending in a first direction (as shown in an X direction in fig. 9), the base 121 including a first type device region 101P for forming a first type SRAM device having a maximum channel width and a second type device region 101B for forming a second type SRAM device, the first type device region 101P and the second type device region 101B each including a plurality of memory cell regions S including first and second sub-cell regions S1 and S2 adjacent and centrosymmetric, the first and second sub-cell regions S1 and S2 each including a pass gate transistor region PG, a pull-down transistor region PD and a pull-up transistor region PU, the bottom fin regions 111 of the same transistor region in the first and second

type device regions

101P and 101B having an equal width; a channel layer structure 251 suspended above the bottom fin 111, where the channel layer structure 251 includes one or more channel layers 231 disposed at intervals along a longitudinal direction, the channel layer structure 251 extends along the first direction, in the first device region 101P, a sidewall of the channel layer 231 along a second direction (as shown in a Y direction in fig. 9) is flush with a sidewall of the bottom fin 111 of the corresponding transistor region along the longitudinal direction (as shown in a Z direction in fig. 10), and in the second device region 101B, in either or both transistor regions of the pass gate transistor region PG, the pull-down transistor region PD, and the pull-up transistor region PU, a sidewall of the channel layer 231 is recessed inward with respect to a bottom fin 111 sidewall of the corresponding transistor region along the second direction, and the second direction is perpendicular to the first direction; a gate structure 501 is disposed on the substrate 121 and spans the plurality of channel layer structures 251 along the second direction, the gate structure 501 including a gate dielectric layer 511 surrounding the channel layer 231, and a gate electrode layer 521 surrounding the gate dielectric layer 511.

In the SRAM device provided in this embodiment, in the process of forming the SRAM device, the bottom fin 111 and the stacked structure including the channel layer 231 are generally formed in the same etching step, and then the channel layer 231 with a partial width is removed along the second direction to form the channel layer structure 251, so that for the second type SRAM device, the widths of the bottom fin 111 in the same transistor area are consistent, that is, in this embodiment, for the SRAM device with different performance requirements, the stacked structure may be formed by using the same design layout, only according to the working current requirements of the SRAM device with different types on each transistor area, in any one or two transistor areas of the pass gate transistor area PG, the lower transistor area PD and the pull-up transistor area PU, the channel layer 231 with a partial width is removed along the second direction, so that the channel layer 231 with a width smaller than the width of the bottom fin 111 is formed, and the design is avoided for the SRAM device with different types, in the second type SRAM device, and in addition, the SRAM device with a width having the channel layer 231 with a width smaller than the bottom width is required, and the first type SRAM device is verified, and the reliability is greatly improved.

The substrate 121 provides a process operation basis for the formation process of the SRAM device. Wherein the SRAM device comprises a full-all-around (GAA) transistor. The fully-enclosed gate transistors include a nanoflake transistor (nanosheet FET) and a nanowire transistor (nanowire FET).

In this embodiment, the base 121 includes a substrate 101, and the material of the substrate 101 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 101 may be a material suitable for process requirements or easy integration.

In this embodiment, the base 121 further includes a plurality of bottom fins 111 protruding from the substrate 101 and extending in the first direction. In this embodiment, the bottom fin 111 and the substrate 101 are integrally formed. In other embodiments, the bottom fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the bottom fin.

Accordingly, in this embodiment, the material of the bottom fin 111 is the same as the material of the substrate 101, and the material of the bottom fin 111 is silicon. In other embodiments, the material of the bottom fin may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the material of the bottom fin may also be different from the material of the substrate.

In this embodiment, in the first-type device region 101P and the second-type device region 101B, the bottom fin 111 in the same transistor region has the same width.

That is, in the first-type device region 101P and the second-type device region 101B, the bottom fin 111 in the pass-gate transistor region PG has the same width, the bottom fin 111 in the pull-down transistor region PD has the same width, and the bottom fin 111 in the pull-up transistor region PU has the same width.

In this embodiment, the substrate 121 further includes an isolation layer 131, where the isolation layer 131 covers the sidewall of the bottom fin 111, and the isolation layer 131 is used to realize insulation between different devices, for example, in a CMOS manufacturing process, the isolation layer 131 is typically formed between an NMOS transistor and a PMOS transistor.

In this embodiment, the material of the isolation layer 131 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

In this embodiment, the substrate 121 includes a first type device region 101P for forming a first type SRAM device having a maximum channel width, and a second type device region 101B for forming a second type SRAM device.

In this embodiment, the first type of SRAM device having the maximum channel width means that: the channel width of each transistor in the first type of SRAM device is equal to the maximum value in the size specification of the corresponding transistor in the SRAM device.

Therefore, the first type SRAM device has the maximum channel width, which is not limited to the case that the channel width of each transistor in the first type SRAM device is larger than the channel width of the corresponding transistor in the second type SRAM device, and the channel widths of the specific transistors are equal.

The first type SRAM device has the maximum channel width, and for both the first type SRAM device and the second type SRAM device, the stacked structure may be formed by using a design layout of the first type SRAM device, and only the channel layer 231 having a width smaller than the width of the bottom fin 111 may be formed by removing a portion of the channel layer 231 in the second direction in any one or both of the pass gate transistor region PG, the pull-down transistor region PD and the pull-up transistor region PU according to the operating current requirement of the second type SRAM device on each transistor region.

In this embodiment, the second device region 101B includes a first sub-device region 101D, where the first sub-device region 101D is used to form a first sub-SRAM device, and an α ratio of the first sub-SRAM device is greater than an α ratio of the first SRAM device.

Wherein the α ratio (alpha ratio) refers to a ratio of the operating currents of the pull-up transistor region PU and the pull-down transistor region PD.

In this embodiment, the first-type device region 101P and the second-type device region 101B each include a plurality of memory cell regions S.

Specifically, in the first-type device region 101P and the second-type device region 101B, a plurality of memory cell regions S are arranged in a matrix in the first direction and the second direction. Wherein, in the plurality of memory cell regions S arranged in the matrix, the first direction is parallel to the column direction of the plurality of memory cell regions S, and the second direction is parallel to the row direction of the plurality of memory cell regions S.

In this embodiment, the memory cell area S includes a first subunit area S1 and a second subunit area S2 that are symmetrical in center, the first subunit area S1 and the second subunit area S2 each include a pass gate transistor area PG, a pull-down transistor area PD and a pull-up transistor area PU, only the pass gate transistor area PG, the pull-down transistor area PD and the pull-up transistor area PU in the first subunit area S1 are illustrated in fig. 9 and 11, and the second subunit area S2 is symmetrical in center with the first subunit area S1.

Specifically, the pass gate transistor region PG and the pull-down transistor region PD are disposed adjacent to each other in the first direction, and the pass gate transistor region PG and the pull-down transistor region PD are disposed adjacent to the pull-up transistor region PU in the second direction.

The pass gate transistor region PG is used to form a pass gate transistor, the pull-down transistor region PD is used to form a pull-down transistor, and the pull-up transistor region PU is used to form a pull-up transistor. The transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

The channel layer structure 251 includes one or more channel layers 231 spaced apart in a longitudinal direction, and the channel layers 231 serve as channels of corresponding transistors. Wherein the longitudinal direction refers to a normal direction of the top surface of the substrate 121.

In this embodiment, the top, bottom and side walls of the channel layer 231 can be used as channels, so that the area of the channel layer 231 used as channels is increased, and the operating current of the SRAM device is increased.

In this embodiment, the material of the channel layer 231 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. As an example, the material of the channel layer 231 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.

Referring to fig. 10, in the first device region 101P, the sidewall of the channel layer 231 along the second direction is flush with the sidewall of the bottom fin 111 of the corresponding transistor region in the longitudinal direction.

Note that, the corresponding transistor region refers to a transistor region where the channel layer 231 is located, for example, the sidewall of the channel layer 231 of the pass-gate transistor region PG is flush with the sidewall of the bottom fin 111 of the pass-gate transistor region PG in the longitudinal direction.

In this embodiment, for both the first type SRAM device and the second type SRAM device, the stacked structure may be formed by using the design layout of the first type SRAM device, and then in the first type device region 101P, the channel layer 231 with a partial width is not required to be removed along the second direction, so in the first type device region 101P, the sidewall of the channel layer 231 along the second direction is flush with the sidewall of the bottom fin 111 of the corresponding transistor region in the longitudinal direction.

Specifically, in the first device region 101P, the width of the bottom fin 111 in the pull-up transistor region PU is a first width, and the widths of the bottom fin 111 in the pull-down transistor region PD and the pass-gate transistor region PG are equal to each other and are a second width, which is twice the first width, along the second direction.

Therefore, in the first type SRAM device, the channel width ratio among the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:2:2, so that in the semiconductor field, the first type SRAM device is a commonly used SRAM device, and among various types of SRAM devices, the SRAM device with a larger channel width is beneficial to forming a second type SRAM device by removing the channel layer 231 with a partial width of the first type SRAM device, thereby facilitating the design layout of the first type SRAM device to form the first type SRAM device and the second type SRAM device.

In this embodiment, in the second-type device region 101B, in any one or two of the pass-gate transistor region PG, the pull-down transistor region PD, and the pull-up transistor region PU, the sidewall of the channel layer 231 is recessed inward with respect to the bottom fin 111 sidewall of the corresponding transistor region along the second direction, so that other types of SRAM devices can be formed.

Note that, the corresponding transistor region refers to a transistor region where the channel layer 231 is located, for example, along the second direction, the sidewall of the channel layer 231 of the pass gate transistor region PG is recessed inward with respect to the sidewall of the bottom fin 111 of the pass gate transistor region PG.

It should be further noted that, the sidewall of the channel layer 231 is recessed inward with respect to the sidewall of the bottom fin 111 of the corresponding transistor region, which means that the width of the channel layer 231 is smaller than the width of the bottom fin 111.

Specifically, referring to fig. 12, in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 101D, the sidewalls of the channel layer 231 are recessed inward with respect to the bottom fin 111 sidewalls of the corresponding transistor region in the second direction.

That is, in this embodiment, according to the operating current requirement of the first sub-type SRAM device for each transistor region, in the pass gate transistor region PG and the pull-down transistor region PD, the channel layer 231 with a partial width is removed along the second direction, so as to form the channel layer 231 with a width smaller than the width of the bottom fin 111, thereby forming the first sub-type SRAM device.

Therefore, in this embodiment, by recessing the sidewall of the channel layer 231 inward with respect to the sidewall of the bottom fin 111 of the corresponding transistor region in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 101D, the effective width of the channel layer 231 is reduced, and the operating current of the transistor is correspondingly reduced, so that the first sub-SRAM device with smaller operating current can be formed, and at the same time, by reducing the operating current of the pull-down transistor region PD, the α ratio of the first sub-SRAM device is made larger, so that the first sub-SRAM device has good data retention stability.

Specifically, in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 101D, the width of the channel layer 231 is a first width.

Therefore, in the first sub-class SRAM device, the channel width ratio among the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:1:1, so that in the semiconductor field, the first sub-class SRAM device is also a commonly used SRAM device, and the first sub-class SRAM device is an SRAM device with better data retention stability among various commonly used SRAM devices, which is beneficial to adopting the design layout of the first type SRAM device and simultaneously forming the first type SRAM device and the first sub-class SRAM device commonly used in the semiconductor field.

The gate structure 501 is used to control the turning on and off of the channels of the SRAM device.

The gate dielectric layer 511 is used to isolate the gate electrode layer 521 from the channel layer 231.

The gate dielectric layer 511 material includes HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following.

In this embodiment, the gate structure 501 is a metal gate structure, so the gate dielectric layer 511 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ Etc.

Note that the gate dielectric layer 511 may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 231. Specifically, the material of the gate oxide layer may be silicon oxide.

In this embodiment, the material of the gate electrode layer 521 includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.

Specifically, the gate electrode layer 521 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.

In other embodiments, the gate structure may be a polysilicon gate structure, depending on the process requirements.

Fig. 13 to 15 are schematic structural diagrams of another embodiment of the SRAM device of the present invention.

The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: the second type device region includes a second sub-type device region in which sidewalls of the channel layer are recessed inwardly with respect to bottom fin sidewalls of the respective transistor region along the second direction in the transfer gate transistor region.

Referring to fig. 13 to 15 in combination, for convenience of illustration, fig. 13 shows only a substrate, fig. 14 is a top view of any one of memory cells in a second type device region, fig. 15 (a) is a cross-sectional view of fig. 14 in AA direction, and fig. 15 (B) is a cross-sectional view of fig. 14 in BB direction, the second type device region 103B includes a second sub-type device region 103V for forming a second sub-type SRAM device having a β ratio greater than that of the first type SRAM device.

The beta ratio (beta ratio) refers to the ratio of the operating currents of the pull-down transistor region PD and the pass gate transistor region PG.

Specifically, referring to fig. 15, in the pass-gate transistor region PG of the second sub-device region 103V, the sidewall of the channel layer 231 is recessed inward with respect to the bottom fin 113 sidewall of the corresponding transistor region along the second direction.

That is, in the present embodiment, during the process of forming the SRAM device, according to the operating current requirement of the second sub-class SRAM device for each transistor region, in the pass-gate transistor region PG, along the second direction, the channel layer 233 with a partial width is removed, and the channel layer 233 with a width smaller than the width of the bottom fin 113 is formed, so as to form the second sub-class SRAM device.

Therefore, in this embodiment, by recessing the sidewall of the channel layer 233 inward with respect to the sidewall of the bottom fin 113 of the corresponding transistor region in the pass-gate transistor region PG of the second sub-class device region 103V, the operating current of the pass-gate transistor is reduced, that is, the read current of the pass-gate transistor when performing the read operation is reduced, which is advantageous for reducing the disturbance to the second sub-class SRAM device, so that the second sub-class SRAM device is advantageously operated at a lower operating voltage, and at the same time, by reducing the operating current of the pass-gate transistor region PG, the β ratio of the second sub-class SRAM device is made larger, so that the second sub-class SRAM device with a larger static noise margin can be formed.

Specifically, in the pass-gate transistor region PG of the second sub-device region 103V, the width of the channel layer 233 is the first width.

Therefore, in the second sub-class SRAM device, the channel width ratio among the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:1:2, so that in the semiconductor field, the second sub-class SRAM device is also a commonly used SRAM device, and the second sub-class SRAM device is an SRAM device with a larger static noise margin among commonly used SRAM devices, which is beneficial to adopting the design layout of the first-class SRAM device and simultaneously forming the first-class SRAM device and the second sub-class SRAM device commonly used in the semiconductor field.

It should be noted that, in other embodiments, the second device area may further include a first sub-device area and a second sub-device area, which are used to form the first sub-SRAM device and the second sub-SRAM device, respectively, so that the design layout of the first SRAM device is adopted, and the first SRAM device, the first sub-SRAM device and the second sub-SRAM device that are commonly used in the semiconductor field are formed at the same time.

FIGS. 16-28 are schematic diagrams illustrating steps corresponding to one embodiment of a method for forming an SRAM device of the present invention.

Referring to fig. 16 to 18 in combination, for convenience of illustration, fig. 16 shows a substrate only, fig. 17 is a top view of any one of the memory cells, fig. 18 (a) is a cross-sectional view of fig. 17 along the AA direction, fig. 18 (B) is a cross-sectional view of fig. 17 along the BB direction, a substrate 120 is provided, including a first type device region 100P for forming a first type SRAM device having a maximum channel width and a second type device region 100B for forming a second type SRAM device, the first type device region 100P and the second type device region 100B each include a plurality of memory cell regions S, the memory cell regions S include a first sub-cell region S1 and a second sub-cell region S2 adjacent and centrally symmetrical, the first sub-cell region S1 and the second sub-cell region S2 each include a pass gate transistor region PG, a pull-down transistor region PD and a pull-up transistor region PU, the substrate 120 is formed with a sacrificial layer 200 extending in the first direction (e.g. in the X direction in fig. 17) along the first direction, the sacrificial layer structure 200 is formed on the substrate 120, the first type SRAM region 200 includes a layer stack 200 having a width corresponding to the channel region 200 in the stack structure 200, and the channel region 200 is formed in the stack layer stack structure 200, and the sacrificial layer 200 has a channel region 200 is formed in the stack structure corresponding to the first channel region 200.

The substrate 120 provides a process operation basis for the formation process of the SRAM device. Wherein the SRAM device comprises a fully surrounding gate transistor. The fully-enclosed gate transistors include a nanoflake transistor and a nanowire transistor.

In this embodiment, the base 120 includes a substrate 100, and the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 100 may be a material suitable for process requirements or easy integration.

In this embodiment, the base 120 further includes a plurality of bottom fins 110 protruding from the substrate 100 and extending in the first direction. In this embodiment, the bottom fin 110 and the substrate 100 are integrally formed. In other embodiments, the bottom fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the bottom fin.

Accordingly, in this embodiment, the material of the bottom fin 110 is the same as the material of the substrate 100, and the material of the bottom fin 110 is silicon. In other embodiments, the material of the bottom fin may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the material of the bottom fin may also be different from the material of the substrate.

In this embodiment, the substrate 120 further includes an isolation layer 130, where the isolation layer 130 covers the sidewalls of the bottom fin 110, and the isolation layer 130 is used to achieve insulation between different devices, for example, in a CMOS manufacturing process, the isolation layer 130 is typically formed between an NMOS transistor and a PMOS transistor.

In this embodiment, the material of the isolation layer 130 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

In this embodiment, the substrate 120 includes a first type device region 100P for forming a first type SRAM device having a maximum channel width, and a second type device region 100B for forming a second type SRAM device.

The first type SRAM device has the maximum channel width, and for both the first type SRAM device and the second type SRAM device, the stacked structure 200 may be formed by using the design layout of the first type SRAM device, and then, in the second type device region 100B, any one or two of the pass gate transistor region PG, the pull-down transistor region PD and the pull-up transistor region PU may be removed from the channel layer 230 with a partial width according to the operating current requirement of the second type SRAM device on each transistor region, so that the remaining width of the channel layer 230 may meet the requirement of the second type SRAM device.

In this embodiment, the second device region 100B includes a first sub-device region 100D, where the first sub-device region 100D is used to form a first sub-SRAM device, and an α ratio of the first sub-SRAM device is greater than an α ratio of the first SRAM device.

In this embodiment, the first-type device region 100P and the second-type device region 100B each include a plurality of memory cell regions S.

Specifically, in the first-type device region 100P and the second-type device region 100B, a plurality of memory cell regions S are arranged in a matrix in the first direction and the second direction. Wherein, in the plurality of memory cell regions S arranged in the matrix, the first direction is parallel to the column direction of the plurality of memory cell regions S, and the second direction is parallel to the row direction of the plurality of memory cell regions S.

In this embodiment, the memory cell area S includes a first subunit area S1 and a second subunit area S2 that are symmetrical in center, the first subunit area S1 and the second subunit area S2 each include a pass gate transistor area PG, a pull-down transistor area PD and a pull-up transistor area PU, only the pass gate transistor area PG, the pull-down transistor area PD and the pull-up transistor area PU in the first subunit area S1 are illustrated in fig. 17, and the second subunit area S2 is symmetrical in center with the first subunit area S1.

The channel layer 230 in the stacked structure 200 is used as a channel of a corresponding transistor, and the first sacrificial layer 220 is used to provide a process basis for a subsequent suspended arrangement of the channel layer 230 and also is used to occupy a space position for a subsequently formed gate structure. In a subsequent process, the first sacrificial layer 220 is removed, so that the channel layer 230 is suspended, and a gate structure is formed between the channel layer 230 and the substrate 120, and between adjacent channel layers 230, so that the gate structure circumferentially covers the channel layer 230.

In this embodiment, the top, bottom and side walls of the channel layer 230 can all serve as channels, which increases the area of the channel layer 230 used as channels, thereby increasing the operating current of the SRAM device.

Referring to fig. 17, the stacked structure 200 includes a channel region 200c along the first direction. The channel layer 230 of the channel region 200c is used as a channel of the SRAM device.

In this embodiment, the position of the channel region 200c is indicated by a dotted line.

In this embodiment, the material of the channel layer 230 includes silicon, germanium, silicon germanium, or a iii-v semiconductor material. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.

In this embodiment, the material of the first sacrificial layer 220 includes silicon germanium or silicon.

In this embodiment, the material of the channel layer 230 is silicon, and thus, the material of the first sacrificial layer 220 is silicon germanium.

The silicon germanium and silicon can form a larger etching selection ratio, which is favorable for the subsequent removal of the channel layer 230 with partial width, the first sacrificial layer 220 has better protection effect on the upper and lower surfaces of the channel layer 230, and is also favorable for the subsequent removal of the first sacrificial layer 220 and reduction of damage to the channel layer 230.

In other embodiments, a material with an etching selection ratio suitable for the channel layer may be selected according to the material of the channel layer, so as to have a better protection effect on the channel layer later, and be beneficial to reducing damage to the channel layer when the first sacrificial layer is removed later.

In this embodiment, the stacked structures 200 of the transistor areas in the first device area 100P have a corresponding preset width, and the width of each stacked structure 200 in the second device area 100B is equal to the preset width of the corresponding transistor area in the first device area 100P.

That is, in the first-type device region 100P and the second-type device region 100B, the width Ld of each stacked structure 200 in the pull-down transistor region PD is equal, the width Lg of each stacked structure 200 in the pass-gate transistor region PG is equal, and the width Lu of each stacked structure 200 in the pull-up transistor region PU is equal, so that the stacked structures 200 in the first-type device region 100P and the second-type device region 100B can be formed using the same design layout, and the design layout is a design layout for forming the first-type SRAM device with the width of the stacked structure 200 in the first-type device region 100P as a preset width.

Specifically, in the first device region 100P, the width of the stacked structure 200 in the pull-up transistor region PU is a first width, and the widths of the stacked structures 200 in the pull-down transistor region PD and the pass-gate transistor region PG are equal to each other and are a second width, which is twice the first width, in the second direction.

Therefore, in the first type of SRAM device, the channel width ratio among the pull-up transistor region PU, the pass-gate transistor region PG, and the pull-down transistor region PD is 1:2:2, so that in the semiconductor field, the first type of SRAM device is a commonly used SRAM device, and among various types of SRAM devices, the SRAM device with a larger channel width is beneficial to forming a second type of SRAM device by removing the channel layer 230 with a partial width of the first type of SRAM device, thereby facilitating the formation of the first type of SRAM device and the second type of SRAM device by adopting a design layout of the first type of SRAM device.

Referring to fig. 18, in the step of providing the substrate 120, a second sacrificial layer 240 is further formed on the stacked structure 200 to cover the top of the stacked structure 200.

The second sacrificial layer 240 is used for protecting the top surface of the topmost channel layer 230 in the stacked structure 200 when the channel layer 230 with a partial width is subsequently removed, and the second sacrificial layer 240 is also used for occupying a space position for a subsequently formed gate structure.

In this embodiment, the material of the second sacrificial layer 240 is the same as that of the first sacrificial layer 220, which is beneficial to simplifying the forming process, and the subsequent removal of a portion of the second sacrificial layer 240 and the first sacrificial layer 220 is also beneficial to removing the second sacrificial layer 240 and the first sacrificial layer 220 in the same step, thereby simplifying the removing process.

Specifically, the material of the second sacrificial layer 240 includes silicon germanium.

The silicon germanium and silicon can form a larger etching selection ratio, which is favorable for protecting the top surface of the topmost channel layer 230 in the laminated structure 200 when the channel layer 230 with partial width is removed later, and is favorable for removing the second sacrificial layer 240 and reducing the damage to the channel layer 230.

Referring to fig. 19 and 20 in combination, fig. 19 is a plan view based on fig. 17, fig. 20 (a) is a cross-sectional view along AA direction of fig. 19, fig. 20 (b) is a cross-sectional view along BB direction of fig. 19, and the forming method further includes, before performing the channel width adjustment process subsequently: a dummy gate structure 300 is formed across the stack structure 200, the dummy gate structure 300 covering the sidewalls and top of the stack structure 200 of the channel region 200 c.

The dummy gate structure 300 is used to occupy a spatial position for subsequent gate structure formation.

In this embodiment, the dummy gate structure 300 may have a single-layer structure or a stacked-layer structure, and the material of the dummy gate structure 300 includes one or both of amorphous silicon and polysilicon. In other embodiments, the material of the dummy gate structure may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or amorphous carbon.

In this embodiment, the dummy gate structure 300 is a single-layer structure, and the material of the dummy gate structure 300 is amorphous silicon. The amorphous silicon does not have a crystal orientation, so that the uniformity of the etching rate and the uniformity of the etching effect on the amorphous silicon are better, thereby improving the subsequent removal effect on the dummy gate structure 300.

Note that, a gate oxide layer (not shown) may be further formed between the dummy gate structure 300 and the stacked structure 200 according to the process requirement. The gate oxide layer may be made of silicon oxide.

Referring to fig. 21 and 22 in combination, fig. 21 is a plan view based on fig. 19, fig. 22 (a) is a cross-sectional view along AA direction of fig. 21, and fig. 22 (b) is a cross-sectional view along BB direction of fig. 21, an interlayer dielectric layer 400 is formed to cover sidewalls of the dummy gate structure 300, and the interlayer dielectric layer 400 exposes a top of the dummy gate structure 300.

The interlayer dielectric layer 400 is used for isolating adjacent devices, and the interlayer dielectric layer 400 is also used for providing a process basis for forming a gate opening for removing the dummy gate structure 300 later.

The interlayer dielectric layer 400 is made of an insulating material, and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

With continued reference to fig. 21 and 22, the dummy gate structure 300 is removed, and a gate opening 310 surrounded by the interlayer dielectric layer 400 is formed, where the gate opening 310 exposes the channel layer 230.

The gate opening 310 exposes the channel layer 230 in preparation for subsequent removal of a portion of the width of the channel layer 230, the gate opening 310 also providing a spatial location for subsequent formation of a gate structure.

Referring to fig. 23 and 24 in combination, fig. 23 is a top view based on the first sub-device region 100D of fig. 21, fig. 24 (a) is a cross-sectional view of fig. 23 along the AA direction, fig. 24 (B) is a cross-sectional view of fig. 23 along the BB direction, and a channel width adjustment process is performed in the second-type device region 100B, in which the channel layer 230 of a partial width in the channel region 200c is removed in a second direction perpendicular to the first direction in any one or both of the pass-gate transistor region PG, the pull-down transistor region PD, and the pull-up transistor region PU.

Wherein the first sacrificial layer 220 and the second sacrificial layer 240 are not shown in fig. 23 for ease of illustration.

In the forming method provided in the embodiment of the present invention, the width of each stack structure 200 in the second type device region 100B is equal to the preset width of the transistor corresponding to the first type device region 100P, after forming the stack structure 200, in the second type device region 100B, in any one or two transistor regions of the pass-gate transistor region PG, the pull-down transistor region PD and the pull-up transistor region PU, the channel layer 230 with a partial width in the channel region 200c is removed along the second direction, so that for different types of SRAM devices, the stack structure 200 can be formed by using the same design layout, only the working current requirement of the second type SRAM device on each transistor region is required, in any one or two transistor regions of the pass-gate transistor region PG, the pull-down transistor region PD and the pull-up transistor region PU, the channel layer 230 with different widths is removed along the second direction, the layout is prevented from being respectively designed for different types of devices, and the design is saved, and after verifying that the second type SRAM device has a partial width in the second direction is required, the channel layer 230 is greatly reduced, and the channel efficiency is greatly improved, and the process efficiency is greatly improved.

In addition, in this embodiment, by removing a portion of the width of the channel layer 230 in the channel region 200c along the second direction, the width of the removed channel layer 230 may be flexibly selected, so as to more flexibly adapt to the performance requirements of various SRAM devices.

Specifically, a portion of the width of the channel layer 230 in the channel region 200c is removed through the gate opening 310.

In this embodiment, the sidewall of the gate opening 310 is further typically formed with a sidewall, and the channel layer 230 with a partial width in the channel region 200c is removed through the gate opening 310, which has a small influence on the channel layer 230 covered by the sidewall, and is beneficial to the growth of the source-drain doped region. In addition, the gate opening 310 is used to provide a space for forming a gate structure, and the gate opening 310 is used to remove a portion of the thickness of the channel layer 230, so that the modification of the current process is small and the process compatibility is high.

In this embodiment, the channel width adjustment process includes: in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 100D, the channel layer 230 of a partial width in the channel region 200c is removed along the second direction.

Therefore, in this embodiment, by removing the channel layer 230 with a partial width in the channel region 200c in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-type device region 100D, the effective width of the channel layer 230 is reduced, and the operating current of the transistor is correspondingly reduced, so that the first sub-type SRAM device with a smaller operating current can be formed, and at the same time, by reducing the operating current of the pull-down transistor region PD, the α ratio of the first sub-type SRAM device is made larger, so that the first sub-type SRAM device has good data retention stability.

In this embodiment, a selective wet etching process is used to remove a portion of the width of the channel layer 230 in the channel region 200c, where the selective wet etching process is an etching process that has a greater etching rate for the channel layer 230 than for the first sacrificial layer 220.

The etching rate of the selective wet etching process to the channel layer 230 is greater than that to the first sacrificial layer 220, and correspondingly, the etching rate of the selective wet etching process to the channel layer 230 is also greater than that to the second sacrificial layer 240, so that the channel layer 230 and the first sacrificial layer 220 and the second sacrificial layer 240 can form a larger etching selectivity ratio, which is beneficial to better protecting the upper and lower surfaces of the channel layer 230 when the channel layer 230 with partial width is removed.

In this embodiment, the etching solution of the selective wet etching process includes a TMAH solution.

In this embodiment, the material of the channel layer 230 is silicon, and the material of the first sacrificial layer 220 and the second sacrificial layer 240 is silicon germanium, so that the selective wet etching is performed by using the TMAH solution, so that the channel layer 230 with a partial width is easy to be removed, and meanwhile, damage to the first sacrificial layer 220 and the second sacrificial layer 240 is reduced, and protection effects of the first sacrificial layer 220 and the second sacrificial layer 240 on the upper surface and the lower surface of the channel layer 230 are ensured.

Specifically, in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 100D, the step of removing the channel layer 230 having a partial width in the channel region 200c along the second direction includes: forming a first mask layer 410 covering the pull-up transistor region PU in the first sub-device region 100D; after the first mask layer 410 is formed, the channel layer 230 in the channel region 200c is etched in the second direction in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 100D.

The first mask layer 410 is used to protect the channel layer 230 in the pull-up transistor region PU when removing the channel layer 230 of partial widths of the pull-down transistor region PD and the pass-gate transistor region PG.

It should be noted that, the first mask layer 410 also covers the channel layer 230 of the first device region 100P, so as to protect the channel layer 230 of the first device region 100P from being damaged.

In this embodiment, the material of the first mask layer 410 includes photoresist, which is a material easy to remove, so that the subsequent removal of the first mask layer 410 is facilitated, and the damage to other film layers is reduced when the subsequent removal of the first mask layer 410 is facilitated.

In this embodiment, after etching the channel layer 230 in the channel region 200c along the second direction in the pull-down transistor region PD and the pass-gate transistor region PG of the first sub-device region 100D, the method further includes: the first mask layer 410 is removed.

In this embodiment, after the channel width adjustment process, the width of the remaining channel layer 230 in the channel region 200c is the first width in the pull-down transistor region PD and the pass-gate transistor region PG.

Referring to fig. 25 to 28 in combination, fig. 25 is a top view of the first-type device region 100P based on fig. 21, fig. 26 (a) is a cross-sectional view of fig. 25 along the AA direction, fig. 26 (b) is a cross-sectional view of fig. 25 along the BB direction, fig. 27 is a top view of the first sub-type device region 100D based on fig. 23, fig. 28 (a) is a cross-sectional view of fig. 27 along the AA direction, fig. 28 (b) is a cross-sectional view of fig. 27 along the BB direction, and after removing a portion of the channel layer 230 having a width in the channel region 200c, the first sacrificial layer 220 in the channel region 200c is removed.

The first sacrificial layer 220 is removed to provide a spatial location for subsequent formation of a gate structure while exposing the various surfaces of the channel layer 230 in preparation for subsequent formation of a gate structure surrounding and overlying the channel layer 230.

Specifically, the first sacrificial layer 220 in the channel region 200c is removed through the gate opening 310.

In this embodiment, the first sacrificial layer 220 is removed by wet etching. The wet etching process has relatively low cost and simple operation steps, and can also realize a large etching selection ratio, which is beneficial to reducing damage to the channel layer 230 in the process of removing the first sacrificial layer 220.

In this embodiment, the step of removing the first sacrificial layer 220 in the channel region 200c further includes: the second sacrificial layer 240 of the channel region 200c is removed.

The second sacrificial layer 240 of the channel region 200c is removed to expose the top surface of the topmost channel layer 230 in preparation for subsequent formation of a gate structure surrounding and overlying the channel layer 230.

In this embodiment, the second sacrificial layer 240 and the first sacrificial layer 220 are removed in the same step, which simplifies the removal process.

With continued reference to fig. 25-28, after removing the first sacrificial layer 220 in the channel region 200c, a gate structure 500 is formed in the channel region 200c across the channel layer 230, the gate structure 500 including a gate dielectric layer 510 surrounding the channel layer 230, and a gate electrode layer 520 surrounding the gate dielectric layer 510.

Specifically, after the first sacrificial layer 220 is removed, the gate structure 500 is formed in the gate opening 310.

The gate structure 500 is used to control the turning on and off of the channels of the SRAM device.

The gate dielectric layer 510 is used to isolate the gate electrode layer 520 from the channel layer 230 and the gate electrode layer 520 from the substrate 120 of the channel region 200 c.

The gate dielectric layer 510 material includes HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following. In this embodiment, the gate dielectric layer 510 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ Etc.

Note that the gate dielectric layer 510 may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 230. Specifically, the material of the gate oxide layer may be silicon oxide.

In this embodiment, the gate structure 500 is a metal gate structure, and thus, the material of the gate electrode layer 520 includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.

Specifically, the gate electrode layer 520 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.

In other embodiments, the gate electrode layer may also include only the work function layer.

Fig. 29 to 30 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming an SRAM device according to the present invention.

The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: and after the channel width adjustment processing is carried out, forming the pseudo gate structure.

Referring to fig. 29 and 30 in combination, fig. 29 is a top view of any memory cell region of the first sub-device region, fig. 30 (a) is a cross-sectional view along AA direction of fig. 29, fig. 30 (b) is a cross-sectional view along BB direction of fig. 29, and after the channel width adjustment process, before the first sacrificial layer 222 in the channel region 202c is subsequently removed, the method further includes: a dummy gate structure 302 is formed across the stack structure 202, the dummy gate structure 302 covering the sidewalls and top of the stack structure 200 of the channel region 202 c.

Specifically, the channel width adjustment process is performed after the formation of the stacked structure 202, and is not limited to the channel layer 232 for the channel region 202 c.

Accordingly, when the channel width adjustment processing is performed, only the formation position of the first mask layer needs to be adjusted, and the area which does not need the channel width adjustment processing can be protected.

The specific description of the dummy gate structure 302 may be combined with the corresponding description in the foregoing embodiments, and will not be repeated herein.

Note that fig. 29 and 30 show only schematic views of the first sub-device region 102D, and the steps of forming the first and second device regions are the same.

The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: the second type device region includes a second sub-type device region in which the channel layer is removed in a partial width along the second direction in a transfer gate transistor region of the second sub-type device region.

It should be noted that, in the foregoing embodiment, the dummy gate structure may be formed before the channel width adjustment process is performed, or may be formed after the channel width adjustment process is performed.

Referring to fig. 31 to 33 in combination, for convenience of illustration, fig. 31 shows only a substrate, fig. 32 is a top view of any memory cell region of the second sub-class SRAM device region, fig. 33 (a) is a cross-sectional view of fig. 32 in the AA direction, and fig. 33 (B) is a cross-sectional view of fig. 32 in the BB direction, the second sub-class device region 104B including a second sub-class device region 104V for forming a second sub-class SRAM device having a β ratio greater than that of the first class SRAM device.

In this embodiment, the channel width adjustment process includes: in the pass-gate transistor region PG of the second sub-device region 104V, the channel layer 234 of a partial width in the channel region 204c is removed along the second direction.

Therefore, in this embodiment, by removing the channel layer 234 with a partial width in the channel region 204c in the pass gate transistor region PG of the second sub-class device region 104V, the operating current of the pass gate transistor is reduced, that is, the read current of the pass gate transistor when performing the read operation is reduced, which is beneficial to reducing the interference to the second sub-class SRAM device, so that the second sub-class SRAM device operates at a lower operating voltage, and at the same time, by reducing the operating current of the pass gate transistor region PG, the β ratio of the second sub-class SRAM device is larger, so that the second sub-class SRAM device with a larger static noise margin can be formed.

Specifically, in the pass-gate transistor region PG of the second sub-device region 104V, the step of removing the channel layer 234 with a partial width in the channel region 204c along the second direction includes: forming a second mask layer 414 covering the pull-up transistor region PU and the pull-down transistor region PD in the second sub-device region 104V; after the second mask layer 414 is formed, the channel layer 234 in the channel region 204c is etched in the pass-gate transistor region PG of the second sub-device region 104V exposed by the second mask layer 414 along the second direction.

The second mask layer 414 serves to protect the channel layer 234 in the pull-up transistor region PU and the pull-down transistor region PD when the channel layer 234 of a partial width of the pass-gate transistor region PG is removed.

In this embodiment, the material of the second mask layer 414 includes photoresist, which is a material that is easy to remove, so that the subsequent removal of the second mask layer 414 is facilitated, and the damage to other film layers is reduced when the subsequent removal of the second mask layer 414 is facilitated.

It should be noted that the second mask layer 414 also covers the channel layer 234 of the first device region 104P, and protects the channel layer 234 of the first device region 104P from being damaged.

In this embodiment, after the channel layer 234 in the channel region 204c is etched in the second direction in the pass-gate transistor region PG of the second sub-device region 100V, the method further includes: the second mask layer 414 is removed.

Specifically, after the channel width adjustment process, in the pass gate transistor region PG, the width of the remaining channel layer 234 in the channel region 204c is the first width.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. An SRAM device, comprising:

a base including a substrate and a plurality of bottom fin portions protruding from the substrate and extending in a first direction, the base including a first type device region for forming a first type SRAM device having a maximum channel width and a second type device region for forming a second type SRAM device, each of the first and second type device regions including a plurality of memory cell regions including first and second sub-cell regions adjacent and centrally symmetric, each of the first and second sub-cell regions including a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region, the bottom fin portions of the same transistor region in the first and second type device regions having equal widths;

A channel layer structure suspended above the bottom fin, the channel layer structure including one or more channel layers disposed at intervals along a longitudinal direction, the channel layer structure extending along the first direction, in the first device region, a sidewall of the channel layer along a second direction being flush with a sidewall of the bottom fin of the corresponding transistor region in the longitudinal direction, in the second device region, in any one or both of the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region, a sidewall of the channel layer being recessed inward with respect to a bottom fin sidewall of the corresponding transistor region along the second direction, the second direction being perpendicular to the first direction;

and a gate structure on the substrate and crossing the channel layer structures along the second direction, wherein the gate structure comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer.

2. The SRAM device of claim 1, wherein in the first type device region, a width of a bottom fin in the pull-up transistor region is a first width, and widths of bottom fins in the pull-down transistor region and the pass-gate transistor region are equal and a second width, the second width being twice the first width, in the second direction.

3. The SRAM device of claim 1 or 2, wherein the second type device region comprises one or both of a first sub-type device region for forming a first sub-type SRAM device and a second sub-type device region for forming a second sub-type SRAM device, wherein an alpha ratio of the first sub-type SRAM device is greater than an alpha ratio of the first type SRAM device, and a beta ratio of the second sub-type SRAM device is greater than a beta ratio of the first type SRAM device;

in the pull-down transistor region and the pass-gate transistor region of the first sub-device region, sidewalls of the channel layer are recessed inwardly with respect to bottom fin sidewalls of the respective transistor regions along the second direction;

in the pass-gate transistor region of the second sub-device region, sidewalls of the channel layer are recessed inwardly with respect to bottom fin sidewalls of the respective transistor region in the second direction.

4. The SRAM device of claim 3, wherein in the first type of SRAM device, a channel width ratio in the pull-up transistor region, the pass-gate transistor region, and the pull-down transistor region is 1:2:2;

in the first sub-class SRAM device, the channel width ratio in the pull-up transistor region, pass-gate transistor region, and pull-down transistor region is 1:1:1.

5. The SRAM device of claim 4, wherein in the first type device region, a width of the bottom fin in the pull-up transistor region is a first width, and widths of the bottom fins in the pull-down transistor region and the pass-gate transistor region are equal and a second width, the second width being twice the first width, in the second direction;

the channel layer has a first width in the pull-down transistor region and the pass-gate transistor region of the first sub-device region.

6. The SRAM device of claim 3, wherein in the first type of SRAM device, a channel width ratio in the pull-up transistor region, the pass-gate transistor region, and the pull-down transistor region is 1:2:2;

in the second sub-class SRAM device, the channel width ratio in the pull-up transistor region, pass-gate transistor region, and pull-down transistor region is 1:1:2.

7. The SRAM device of claim 6, wherein in the first type device region, a width of the bottom fin in the pull-up transistor region is a first width, and widths of the bottom fins in the pull-down transistor region and the pass-gate transistor region are equal and a second width, the second width being twice the first width, in the second direction;

In the pass gate transistor region of the second sub-device region, the width of the channel layer is a first width.

8. The SRAM device of claim 1, in which a material of the channel layer comprises silicon, germanium, silicon germanium, or a iii-v semiconductor material.

9. The SRAM device of claim 1, wherein the material of the gate dielectric layer comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAlC.

10. A method of forming an SRAM device, comprising:

providing a substrate comprising a first type device region for forming a first type SRAM device and a second type device region for forming a second type SRAM device, the first type SRAM device having a maximum channel width, the first type device region and the second type device region each comprising a plurality of memory cell regions, the memory cell regions comprising first and second sub-cell regions that are contiguous and centrally symmetric, the first and second sub-cell regions each comprising a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region, the pass gate transistor region, the pull-down transistor region, and the pull-up transistor region having a stack structure formed on the substrate that extends in a first direction, the stack structure comprising one or more stacked channel stacks comprising a first sacrificial layer and a channel layer on the first sacrificial layer, the stack structure comprising a channel region in the first direction, wherein the stack structure of each transistor region in the first type device region has a corresponding preset width, and the stack structure of each transistor region in the second type device region has a width that is equal to the corresponding transistor region in the preset width in the second type region;

Performing channel width adjustment processing, wherein in the second type device region, the channel layer with partial width is removed in a second direction in any one or two transistor regions of the transmission gate transistor region, the pull-down transistor region and the pull-up transistor region, and the second direction is perpendicular to the first direction;

removing the first sacrificial layer in the channel region after removing the channel layer with partial width in the channel region;

and after the first sacrificial layer in the channel region is removed, forming a gate structure crossing the channel layer in the channel region, wherein the gate structure comprises a gate dielectric layer surrounding and covering the channel layer and a gate electrode layer surrounding and covering the gate dielectric layer.

11. The method of forming an SRAM device of claim 10, wherein in the step of providing a substrate, in the first type device region, a width of the stacked structure in the pull-up transistor region is a first width, and a width of the stacked structure in the pull-down transistor region and the pass-gate transistor region is equal and is a second width, the second width being twice the first width, in the second direction.

12. The method of forming an SRAM device of claim 10 or 11, wherein in the step of providing a substrate, the second type device region comprises a first sub-type device region for forming a first sub-type SRAM device, the first sub-type SRAM device having an a-ratio that is greater than an a-ratio of the first type SRAM device;

the channel width adjustment process includes: and removing the channel layer with partial width in the channel region along the second direction in the pull-down transistor region and the transmission gate transistor region of the first sub-type device region.

13. The method of forming an SRAM device of claim 12, wherein in the step of providing a substrate, in the first type device region, a width of the stacked structure in the pull-up transistor region is a first width, and a width of the stacked structure in the pull-down transistor region and the pass-gate transistor region is equal and is a second width, the second width being twice the first width, along the second direction;

after the channel width adjustment process, the width of the remaining channel layer in the channel region is a first width in the pull-down transistor region and the pass-gate transistor region.

14. The method of forming an SRAM device of claim 12, wherein in the pull-down transistor region and the pass-gate transistor region of the first sub-device region, the step of removing a portion of the channel layer of the channel region width along the second direction comprises: forming a first mask layer covering the pull-up transistor region in the first sub-type device region;

after the first mask layer is formed, the channel layer in the channel region is etched in the pull-down transistor region and the pass-gate transistor region of the first sub-device region along the second direction.

15. The method of forming an SRAM device of claim 10, wherein in the step of providing a substrate, the second type device region comprises a second sub-type device region for forming a second sub-type SRAM device, the second sub-type SRAM device having a beta ratio greater than a beta ratio of the first type SRAM device;

the channel width adjustment process includes: and removing the channel layer with partial width in the channel region along the second direction in the transmission gate transistor region of the second sub-type device region.

16. The method of forming an SRAM device of claim 15, wherein in the step of providing a substrate, in the first type device region, a width of the stacked structure in the pull-up transistor region is a first width, and a width of the stacked structure in the pull-down transistor region and the pass-gate transistor region is equal and is a second width, the second width being twice the first width, along the second direction;

After the channel width adjustment process, in the pass gate transistor region, a width of a remaining channel layer in the channel region is a first width.

17. The method of forming an SRAM device of claim 15, wherein in a pass gate transistor region of the second sub-device region, removing a portion of the channel layer of the channel region width along the second direction comprises: forming a second mask layer covering the pull-up transistor region and the pull-down transistor region in the second sub-type device region;

and after the second mask layer is formed, etching the channel layer in the channel region along the second direction in a transmission gate transistor region of the second sub-type device region.

18. The method of forming an SRAM device of claim 10, wherein prior to performing the channel width adjustment process, the method of forming further comprises: forming a dummy gate structure crossing the laminated structure, wherein the dummy gate structure covers the side wall and the top of the laminated structure of the channel region;

forming an interlayer dielectric layer covering the side wall of the pseudo gate structure, wherein the interlayer dielectric layer exposes out of the top of the pseudo gate structure;

Removing the pseudo gate structure to form a gate opening surrounded by the interlayer dielectric layer, wherein the gate opening exposes the channel layer;

removing a portion of the width of the channel layer through the gate opening;

removing the first sacrificial layer in the channel region through the gate opening after removing the channel layer with partial width in the channel region;

and after the first sacrificial layer is removed, forming the gate structure in the gate opening.

19. The method of forming an SRAM device of claim 10, wherein after performing the channel width adjustment process, prior to removing the first sacrificial layer in the channel region, further comprises: forming a dummy gate structure crossing the laminated structure, wherein the dummy gate structure covers the side wall and the top of the laminated structure of the channel region;

removing the pseudo gate structure to form a gate opening surrounded by the interlayer dielectric layer, wherein the gate opening exposes the first sacrificial layer;

removing the first sacrificial layer in the channel region through the gate opening;

20. The method of forming an SRAM device of claim 10, wherein in the step of providing the substrate, the stack structure is further formed with a second sacrificial layer thereon covering a top of the stack structure;

the step of removing the first sacrificial layer in the channel region further includes: and removing the second sacrificial layer of the channel region.

21. The method of forming an SRAM device of claim 10, wherein in the step of removing a portion of the width of the channel layer in the second direction, a selective wet etch process is used to remove a portion of the width of the channel layer, the selective wet etch process being an etch process that etches the channel layer at a greater rate than an etch rate of the first sacrificial layer.

22. The method of forming an SRAM device of claim 21, wherein the etching solution of the selective wet etch process comprises a TMAH solution.

23. The method of forming an SRAM device of claim 10, wherein a material of the channel layer comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material; the material of the first sacrificial layer comprises silicon germanium or silicon.