CN116054774A - Monolithic integrated circuit of nitride surface acoustic wave device and field effect transistor and manufacturing method thereof - Google Patents
Monolithic integrated circuit of nitride surface acoustic wave device and field effect transistor and manufacturing method thereof Download PDFInfo
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- 238000002353 field-effect transistor method Methods 0.000 title description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02535—Details of surface acoustic wave devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/125—Driving means, e.g. electrodes, coils
- H03H9/13—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
- H03H9/131—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials consisting of a multilayered structure
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/125—Driving means, e.g. electrodes, coils
- H03H9/145—Driving means, e.g. electrodes, coils for networks using surface acoustic waves
- H03H9/14544—Transducers of particular shape or position
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- Engineering & Computer Science (AREA)
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- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, which mainly solves the problem that the nitride surface acoustic wave device and the field effect transistor are difficult to integrate epitaxially. Which comprises a substrate, a nucleation layer, a channel layer, an insertion layer, a barrier layer and a piezoelectric ferroelectric layer from bottom to top. The barrier layer is scandium indium aluminum gallium nitride material, and the piezoelectric ferroelectric layer is continuous epitaxial monocrystal scandium aluminum nitride material. Forming a separation region from the channel layer to an etched groove in the piezoelectric ferroelectric layer, and filling a passivation layer; the piezoelectric ferroelectric layer at one side of the separation area and the interdigital electrode on the piezoelectric ferroelectric layer form a surface acoustic wave device; an ohmic contact region, a source electrode and a drain electrode are arranged on the other side of the piezoelectric ferroelectric layer, and a field effect transistor is formed by the ohmic contact region, the source electrode, the drain electrode, the channel layer, the piezoelectric ferroelectric layer, the passivation layer and the gate electrode. The invention prepares the monolithic integrated circuit of the nitride surface acoustic wave device and the field effect transistor on the epitaxial monocrystalline material, improves the circuit performance and the matching performance of frequency bands and bandwidths, and can be used for a signal processing system of a communication radio frequency front end.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a monolithic integrated circuit which can be used for a front-end signal processing system in the communication radio frequency field.
Background
In the microwave radio frequency field, the surface acoustic wave device is generally integrated with analog and radio frequency electronic devices due to small size, low insertion loss and rapid filter response, plays an important role in a radio frequency front-end signal processing circuit, and is widely applied to the fields of communication, internet of things, sensors and automatic driving. Because the AlN material has high electromechanical coupling coefficient, low dielectric loss and compatibility with a CMOS process, the piezoelectric material of the surface acoustic wave filter is mainly prepared into the polycrystalline AlN material by adopting physical vapor transmission deposition methods such as magnetron sputtering and the like at present. Gallium nitride-based high electron mobility transistor GaN HEMTs are widely used as one of solid-state electronic devices of microwave power amplifying devices by virtue of excellent power characteristics and frequency characteristics, and play an important role in the fields of 5G communication and information sensing. The performance improvement of the GaN HEMT device can be realized by changing the structure of a barrier layer, and a conventional AlGaN barrier is developed towards a (Sc) AlN barrier.
In order to improve the processing capability of the radio frequency front-end circuit on analog signals, the polycrystalline material nitride filter device and the monocrystalline material nitride radio frequency device are subjected to single-chip epitaxial-level integration, so that the method is a main technical approach for reducing the size of the circuit and improving the performance of the circuit. In recent years, with the increasing maturity of GaN technology, an attempt is made to integrate a polycrystalline AlN surface acoustic wave device with a monocrystalline GaN HEMT radio frequency device to realize a higher-performance monolithically integrated filter-microwave amplifier, meeting the requirements of future communication systems.
The structure of the surface acoustic wave device prepared from the conventional polycrystalline AlN material is shown in fig. 1, and the surface acoustic wave device comprises a substrate and a polycrystalline AlN piezoelectric layer from bottom to top, wherein interdigital electrodes serving as transducers are arranged on the polycrystalline AlN piezoelectric layer. The GaN HEMT device structure of the existing monocrystalline material comprises a substrate, a nucleation layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top, wherein a gate electrode is arranged on the AlGaN barrier layer, and a source electrode and a drain electrode are arranged on ohmic contact of a source region and a drain region.
The GaN HEMT device mainly adopts a metal organic chemical vapor deposition or molecular beam epitaxy mode for growth, an AlN piezoelectric layer of the surface acoustic wave device mainly adopts a magnetron sputtering method for growth, the crystal quality of the GaN HEMT device has a larger gap due to the inconsistency of the growth modes, and continuous growth and epitaxial-level monolithic integration of two device materials of the polycrystalline AlN surface acoustic wave device and the monocrystalline GaN HEMT radio frequency device are difficult to realize. Therefore, the two devices are integrated by the discrete packaging technology shown in fig. 3, that is, after the nitride surface acoustic wave device and the high electron mobility transistor are manufactured, they are respectively soldered in a printed circuit board, and the two devices are interconnected through an external lead to form an integrated circuit. The integrated circuit has the following disadvantages:
1. because the circuit is integrated by adopting an external lead interconnection mode, the process complexity is increased, parasitic parameters are introduced, the working efficiency is seriously reduced, and the performance and the miniaturization of the radio frequency front-end system are seriously limited.
2. Because the filter prepared from the polycrystalline AlN material has low electromechanical coupling coefficient, piezoelectric coefficient, sound velocity, power processing capacity and quality factors thereof, the filter is directly connected with a GaN microwave radio frequency device in an external lead mode, and the problems of unmatched working frequency bands and bandwidths exist, so that the monolithic integrated circuit cannot work effectively;
3. the crystal quality is inconsistent due to different growth modes of the polycrystalline AlN material and the monocrystalline GaN material, so that the reliability of the AlN surface acoustic wave device and the GaN microwave radio frequency device is greatly different, the local area of the integrated circuit is greatly deviated, the stability and consistency of the AlN surface acoustic wave device and the GaN microwave radio frequency device are obviously reduced, and the application frequency range of the integrated circuit is limited.
4. Because the HEMT device in the integrated circuit has weaker gate control capability and larger subthreshold swing, and the device can be turned off only by exhausting the two-dimensional electron gas in the channel below the gate by applying negative pressure on the gate, the complexity of the design of the integrated circuit can be increased undoubtedly, and the application of the HEMT device in a radio frequency circuit is limited.
Disclosure of Invention
The invention aims at solving the defects of the prior art and provides a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor and a manufacturing method thereof, so as to improve the working efficiency and stability of the nitride surface acoustic wave device and the field effect transistor integrated circuit, realize the frequency band and bandwidth matching of the circuit and simplify the complexity of circuit design.
The technical scheme for realizing the purpose of the invention is as follows:
1. a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor comprises a substrate, a nucleation layer, a channel layer, an insertion layer and a barrier layer from bottom to top, and is characterized in that:
a piezoelectric ferroelectric layer is additionally arranged on the barrier layer, and an interdigital electrode and a gate electrode are arranged on the upper part of the piezoelectric ferroelectric layer;
the channel layer, the insertion layer, the barrier layer and the etched grooves in the piezoelectric ferroelectric layer form a separation region and are filled with a passivation layer;
the piezoelectric ferroelectric layer on one side of the separation region and the interdigital electrode on the upper part of the separation region form a nitride surface acoustic wave device, and the ohmic contact region, the source electrode and the drain electrode are arranged on the other side of the separation region, and form a nitride field effect transistor with the channel layer, the insertion layer, the barrier layer, the piezoelectric ferroelectric layer, the passivation layer and the gate electrode.
The nitride surface acoustic wave device and the nitride field effect transistor share the piezoelectric ferroelectric layer, are isolated by the separation area, and do not interfere with each other in operation.
Further, the piezoelectric ferroelectric layer adopts single crystal Sc with continuous epitaxy m Al n N material, wherein component 0<m<0.35, and m+n=1, thickness 500nm-1500nm;
further, the barrier layer adopts Sc x In y Al z Ga w N material, wherein x is more than or equal to 0 and less than or equal to 0.3, y is more than or equal to 0 and less than or equal to 0.3, and z is more than or equal to 0<1，0≤w<1 and x+y+z+w=1, and the thickness is 6nm to 30nm.
Further, the channel layer is made of GaN material, and the thickness of the channel layer is 500-4000 nm;
further, the nucleation layer is made of AlN material and has a thickness of 3nm-1000nm;
furthermore, the insertion layer is made of AlN material and has a thickness of 1nm-2nm.
Further, the substrate is made of any one of a sapphire material, a silicon carbide material, a diamond material, a gallium nitride material, an aluminum nitride material and a boron nitride material. .
Further, the passivation layer adopts SiN material and Al 2 O 3 Material, hfO 2 Any one of the materials.
2. A method of fabricating a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, comprising the steps of:
1) Growing an AlN nucleation layer of 3-1000 nm on the substrate by using a metal organic chemical vapor deposition technology or a molecular beam epitaxy technology;
2) Growing a GaN channel layer of 500-4000 nm on the AlN nucleation layer by using a metal organic chemical vapor deposition method or a molecular beam epitaxy technology;
3) Growing an AlN insertion layer with the thickness of 1nm-2nm on the GaN channel layer by using a metal organic chemical vapor deposition method or a molecular beam epitaxy technology;
4) Growing a barrier layer with the thickness of 6-30 nm on the AlN inserting layer by using a metal organic chemical vapor deposition method or a molecular beam epitaxy technology;
5) Growing a piezoelectric ferroelectric layer with the thickness of 500-1500 nm on the barrier layer by using a metal organic chemical vapor deposition method or a molecular beam epitaxy technology;
6) Selecting a field effect transistor manufacturing area on the piezoelectric ferroelectric layer by taking photoresist as a mask, and carrying out partial thinning on the piezoelectric ferroelectric layer to 30-80 nm by using a dry etching process;
7) Selecting source-drain ohmic contact areas of field effect transistors on the thinned piezoelectric ferroelectric layer by taking photoresist as a mask, and etching the thinned piezoelectric ferroelectric layer by adopting a dry etching method until reaching the upper part of the channel layer to form source-drain ohmic contact area grooves;
8) Growing Si doped n-type GaN layer in the groove of the source-drain ohmic contact region by using a metal organic chemical vapor deposition method or a molecular beam epitaxy method, wherein the dosage of Si is (0.5-5) multiplied by 10 20 cm -3 Forming an ohmic contact region;
9) Depositing ohmic contact metal Ti/Al/Ni/Au in an ohmic contact area by adopting an electron beam evaporation process by taking photoresist as a mask, and annealing at 830 ℃ under nitrogen atmosphere to form a source electrode and a drain electrode;
10 Using photoresist as a mask, selecting a manufacturing area of the surface acoustic wave device, and adopting an electron beam evaporation process to deposit metal Ti/Au on the non-thinned piezoelectric ferroelectric layer to form interdigital electrodes of the surface acoustic wave device;
11 Setting a gate electrode region on the piezoelectric ferroelectric layer thinned in the field effect transistor region by taking the photoresist as a mask, and depositing metal Ni/Au in the region by adopting an electron beam evaporation process to form a gate electrode;
12 Using gate electrode metal as mask, adopting inductively coupled plasma etching method, using BCl 3 /Cl 2 The gas source is used for completely etching the piezoelectric ferroelectric layer outside the gate electrode of the field effect transistor manufacturing area to form a groove;
13 Using the photoresist as a mask, and etching the piezoelectric ferroelectric layer to the bottom of the GaN channel layer by using a dry etching process to form a separation region;
14 A passivation layer with the thickness of 50nm-200nm is deposited in the manufacturing area of the surface acoustic wave device, the manufacturing area of the field effect transistor and the separation area by adopting a plasma enhanced chemical vapor deposition method or an atomic layer deposition process;
15 Using photoresist as mask, adopting reactive ion etching method, using SF 6 A gas source for etching the passivation layer to form a gate electrode through hole, a source electrode through hole, a drain electrode through hole and an interdigital electrode through hole;
16 Forming interdigital electrode Pad patterns in the surface acoustic wave device manufacturing area, forming gate electrode, source electrode and drain electrode Pad patterns in the field effect transistor manufacturing area, evaporating Au metal layers on the electrode Pad patterns by using photoresist as a mask and adopting an electron beam evaporation process to form metal leads between the electrode Pad patterns and the electrodes respectively, thereby completing the preparation of the monolithic integrated circuit.
Compared with the prior art, the invention has the following advantages:
1. the invention designs the separation area on the integrated circuit structure to realize the isolation of the nitride surface acoustic wave device and the nitride field effect transistor, thereby avoiding the influence of the increased process complexity and parasitic parameters of the interconnection of the external leads and further improving the performance and space utilization rate of the front-end system;
2. the piezoelectric ferroelectric layer with higher piezoelectric coefficient, sound velocity, electromechanical coupling coefficient and ferroelectric characteristic is additionally arranged on the integrated circuit, so that the working frequency, quality factor and power processing capacity of the surface acoustic wave device are improved, and the integrated circuit can work in a high-performance system; the ferroelectric control layer of the field effect transistor can be used for increasing the gate control capability of the transistor and reducing the subthreshold swing so as to reduce the energy consumption of the integrated circuit; the channel of the field effect transistor can be exhausted, so that the threshold voltage of the device is positively moved, and the design difficulty of the integrated circuit is reduced;
3. when the integrated circuit is prepared, the problem that the polycrystalline material surface acoustic wave device and the monocrystalline material field effect transistor are difficult to be subjected to single-chip epitaxial integration is solved by a metal organic chemical vapor deposition technology or a molecular beam epitaxy technology, and the consistency of the material processes of the polycrystalline material surface acoustic wave device and the monocrystalline material field effect transistor and the matching of the working frequency band and the bandwidth are realized, so that the integrated circuit has stable frequency band and high reliability;
4. compared with the traditional magnetron sputtering, the method can grow stable and consistent single crystal material, and is beneficial to reducing the working loss and clutter influence of the integrated circuit.
Drawings
Fig. 1 is a structural diagram of a conventional polycrystalline AlN surface acoustic wave device;
fig. 2 is a structural diagram of a conventional GaN field effect transistor;
FIG. 3 is a prior art surface acoustic wave device and field effect transistor monolithic integrated circuit;
FIG. 4 is a block diagram of a nitride surface acoustic wave device and a field effect transistor monolithic integrated circuit of the present invention;
fig. 5 is a flow chart illustrating the fabrication of the integrated circuit of fig. 4 in accordance with the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 4, the nitride surface acoustic wave device and field effect transistor monolithic integrated circuit of the present example includes a substrate 1, a nucleation layer 2, a channel layer 3, an insertion layer 4, a barrier layer 5, a ferroelectric piezoelectric layer 6, and a passivation layer 7, wherein:
the substrate 1 is made of any one of a sapphire material, a silicon carbide material, a diamond material, a gallium nitride material, an aluminum nitride material and a boron nitride material;
the nucleation layer 2 is positioned on the substrate 1, is made of AlN material and has a thickness of 3nm-1000nm;
the channel layer 3 is positioned above the nucleation layer 2, is made of GaN material and has a thickness of 500nm-4000nm;
the insertion layer 4 is positioned above the channel layer 3, is made of AlN material and has a thickness of 1nm-2nm;
the barrier layer 5 is positioned on the insertion layer 4 and adopts the components that x is more than or equal to 0 and less than or equal to 0.3, y is more than or equal to 0 and less than or equal to 0.3, and z is more than or equal to 0 and less than or equal to 0<1，0≤w<1 and x+y+z+w=1, sc having a thickness of 6nm to 30nm x In y Al z Ga w An N material;
the piezoelectric ferroelectric layer 6 is arranged above the barrier layer 5 and adopts the component 0<m<0.35, and m+n=1, and a thickness of 500nm-1500nm m Al n An N material;
the grooves in the channel layer 3, the insertion layer 4, the barrier layer 5 and the piezoelectric ferroelectric layer 6 are filled with passivation layers 7 to form separation areas;
the passivation layer 7 is made of SiN material and Al 2 O 3 Material, hfO 2 Any one of the materials;
the piezoelectric ferroelectric layer 6 at one side of the separation area and the interdigital electrode at the upper part of the separation area form a nitride surface acoustic wave device, the piezoelectric ferroelectric layer 6 at the other side of the separation area is provided with a gate electrode, and the gate electrode, the channel layer 3, the insertion layer 4, the barrier layer 5, the piezoelectric ferroelectric layer 6 and the passivation layer 7 form a nitride field effect transistor.
Referring to fig. 5, the following three embodiments of the present invention are shown for fabricating a nitride surface acoustic wave device and a field effect transistor monolithic integrated circuit.
Embodiment one, in is fabricated on a silicon carbide substrate using molecular beam epitaxy 0.17 Al 0.83 N barrier layer, sc 0.1 Al 0.9 Nitride surface acoustic wave devices and field effect transistor monolithic integrated circuits of N piezoelectric ferroelectric layers.
Step one, epitaxial AlN nucleation layer, as shown in fig. 5 (a).
An AlN nucleation layer with a thickness of 200nm was epitaxially grown on a silicon carbide substrate using a molecular beam epitaxy technique.
The process conditions of molecular beam epitaxy are: the temperature was 750 ℃, the nitrogen flow was 3.0sccm, and the aluminum beam balance vapor pressure was 3.2X10 -7 Torr, nitrogen RF source power is 350W.
Step two, epitaxial GaN channel layer, as shown in fig. 5 (b).
A GaN channel layer with a thickness of 2000nm was epitaxially grown on the AlN nucleation layer using molecular beam epitaxy techniques.
The process conditions of molecular beam epitaxy are: the temperature was 750 ℃, the nitrogen flow was 3.0sccm, and the balance vapor pressure of the gallium beam was 9.5X10 -7 Torr, nitrogen RF source power is 350W.
Step three, epitaxial AlN insert layer, as shown in FIG. 5 (c)
An AlN insert layer with a thickness of 1.5nm was deposited on the GaN channel layer using molecular beam epitaxy techniques.
The process conditions of molecular beam epitaxy are: the temperature was 750 ℃, the nitrogen flow was 3.0sccm, and the aluminum beam balance vapor pressure was 3.2X10 -7 Torr, nitrogen RF source power is 350W.
Step four, depositing In 0.17 Al 0.83 An N barrier layer as in fig. 5 (d).
In with thickness of 15nm is epitaxially grown on AlN insert layer using molecular beam epitaxy technique 0.17 Al 0.83 An N barrier layer.
The process conditions of molecular beam epitaxy are: the temperature was 600 ℃, the nitrogen flow was 3.0sccm, and the indium beam balance vapor pressure was 2.1X10 × 10 -7 Torr, aluminum beam balance vapor pressure of 1.2X10 -7 Torr, nitrogen RF source power is 350W.
Step five, depositing Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer as in fig. 5 (e).
In using molecular beam epitaxy techniques 0.17 Al 0.83 On the N barrier layer, sc with an epitaxial thickness of 1000nm 0.1 Al 0.9 An N-piezoelectric ferroelectric layer.
The process conditions of molecular beam epitaxy are: the temperature was 680℃and the nitrogen flow was 3.0sccm, and the scandium beam balance vapor pressure was 0.5X10 -7 Torr, aluminum beam balance vapor pressure 3.2X10 -7 Torr, nitrogen RF source power is 350W.
Step six, thinning the portion Sc 0.1 Al 0.9 N piezoelectric ferroelectric layer as in fig. 5 (f).
At Sc 0.1 Al 0.9 And taking photoresist as a mask on the N piezoelectric ferroelectric layer, selecting a field effect transistor manufacturing area, and carrying out partial thinning on the piezoelectric ferroelectric layer to 30nm by using a dry etching process.
The etching adopts the process conditions that: cl 2 The flow rate was 15sccm, the chamber pressure was 11mTorr, and the electrode power was 180W.
And step seven, dry etching to form a groove of the source-drain ohmic contact region, as shown in fig. 5 (g).
In thinned Sc 0.1 Al 0.9 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting source-drain ohmic contact regions of the field effect transistor by taking photoresist as the mask, and respectively removing Sc thinned in the source-drain ohmic contact regions by adopting a dry etching method 0.1 Al 0.9 N piezoelectric ferroelectric layer, in 0.17 Al 0.83 And forming a source-drain ohmic contact region groove by the N barrier layer, the AlN inserting layer and a part of the GaN channel layer.
The etching adopts the process conditions that: cl 2 The flow rate was 15sccm, the chamber pressure was 11mTorr, and the electrode power was 180W.
And step eight, depositing a Si doped n-type GaN layer to form an ohmic contact region, as shown in fig. 5 (h).
Depositing a Si doped n-type GaN layer with the thickness of 50nm in a groove of a source-drain ohmic contact region by using a molecular beam epitaxy technology, wherein the Si doping concentration is 1.0x10 20 cm -3 。
The process conditions of molecular beam epitaxy are: the temperature was 750 ℃, the nitrogen flow was 3.0sccm, and the balance vapor pressure of the gallium beam was 9.5X10 -7 Torr, silicon beam balance vapor pressure of 2.8X10 -8 Torr, nitrogen RF source power is 350W.
Step nine, manufacturing a source electrode, a drain electrode and an interdigital electrode, as shown in fig. 5 (i).
9.1 Sc) in partial thinning 0.1 Al 0.9 Manufacturing a mask on the N piezoelectric ferroelectric layer, and respectively depositing Ti/Al/Ni/Au metal combinations on the source-drain ohmic contact areas by using an electron beam evaporation technology, wherein the metal thickness is 0.02 mu m/0.05 mu m/0.04 mu m; then carrying out rapid thermal annealing in nitrogen atmosphere at 830 ℃ to manufacture a source electrode and a drain electrode;
9.2 In un-thinned Sc) 0.1 Al 0.9 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting a manufacturing area of the surface acoustic wave device, and using an electron beam evaporation technology to manufacture a non-thinned Sc 0.18 Al 0.82 And depositing metal Ti/Au on the N piezoelectric ferroelectric layer, wherein the metal thickness is 0.02 mu m/0.04 mu m, and forming the interdigital electrode.
The process conditions adopted for depositing the metal are as follows: vacuum degree is less than 1.5X10 -3 Pa, the power range is 500-800W,the evaporation rate is
The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 830℃and the time was 30s.
Step ten, a gate electrode is fabricated as shown in fig. 5 (j).
Sc thinning in field effect transistor region 0.1 Al 0.9 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting a gate electrode manufacturing area, and using electron beam evaporation technology to thin Sc 0.1 Al 0.9 And depositing metal on the N piezoelectric ferroelectric layer to manufacture a gate electrode, wherein the deposited metal is a Ni/Au metal combination, and the metal thickness is 0.02 mu m/0.3 mu m.
The process conditions adopted for depositing the metal are as follows: vacuum degree is less than 1.4X10 -3 Pa, the power range is 400-800W, the evaporation rate is
Step eleven, etching the gate source and drain conductive regions, as shown in fig. 5 (k).
Using gate electrode metal as a mask, and adopting inductively coupled plasma etching to remove Sc thinned in the gate-source conducting region and the gate-drain conducting region respectively 0.1 Al 0.9 And the N piezoelectric ferroelectric layer is used for forming a gate-source conducting region groove and a gate-drain conducting region groove.
The etching process conditions are as follows: cl 2 The air flow was 10sccm, BCl 3 The gas flow rate was 25sccm and the etching time was 150s.
Step twelve, etching the piezoelectric ferroelectric layer of the two device manufacturing regions to the bottom of the channel layer to form a separation region, as shown in fig. 5 (l).
And etching the piezoelectric ferroelectric layer of the surface acoustic wave device manufacturing area and the piezoelectric ferroelectric layer of the field effect transistor manufacturing area to the bottom of the GaN channel layer by using the photoresist as a mask by using a dry etching process to form a separation area of the two device manufacturing areas.
The etching adopts the process conditions that: cl 2 The flow rate was 15sccm, the chamber pressure was 11mTorr, and the electrode power was 180W.
Step thirteenth, a SiN passivation layer is deposited, as in FIG. 5 (m).
And depositing SiN passivation layers with the thickness of 200nm in the surface acoustic wave device manufacturing area, the field effect transistor manufacturing area and the separation area by adopting a plasma enhanced chemical vapor deposition method.
The plasma enhanced chemical vapor deposition method adopts the process conditions that: the time is 60s, the pressure is 2200mTorr, the temperature is 350 ℃, and SiH is 4 Flow rate is 13.5sccm, NH 3 Flow is 10sccm, N 2 The flow rate was 1000sccm.
Step fourteen, gate electrode through holes, source electrode through holes, drain electrode through holes and interdigital electrode through holes are prepared on the SiN passivation layer, as shown in fig. 5 (n).
And etching the SiN passivation layer to the metal surfaces of the gate electrode, the source electrode, the drain electrode and the interdigital electrode by using the photoresist as a mask and adopting a reactive ion etching method to form a gate electrode through hole, a source electrode through hole, a drain electrode through hole and an interdigital electrode through hole.
The process conditions adopted by the reactive ion etching method are as follows: pressure is 1500mTorr, power is 200W, SF 6 Flow rate of 8sccm, CHF 3 The He flow was 150sccm at 10 sccm.
Fifteen, each electrode Pad is led out from each electrode via hole, as shown in fig. 5 (o).
Photoetching to form metal Pad patterns of a gate electrode, a source electrode, a drain electrode and an interdigital electrode on each electrode through hole by adopting a traditional optical photoetching process; by electron beam evaporation method according to
Au metal with the thickness of 80nm is evaporated on each electrode Pad, and then is soaked by acetone to form a gate electrode Pad, a source electrode Pad, a drain electrode Pad and an interdigital electrode Pad which are respectively interconnected with the gate electrode, the source electrode, the drain electrode and the interdigital electrode, thereby completing the manufacture of the monolithic integrated circuit.
Second embodiment, sc is fabricated on GaN substrate using molecular beam epitaxy 0.18 Al 0.82 N barrier layer, sc 0.18 Al 0.82 Nitride surface acoustic wave device with N piezoelectric ferroelectric layer and field effect transistor monolithic setForming a circuit.
Setting the temperature to 600 ℃, the nitrogen flow rate to 0.6sccm, and the aluminum beam balance vapor pressure to 0.6X10 -7 And (3) an AlN nucleating layer with the thickness of 3nm is epitaxially grown on the gallium nitride substrate by using a molecular beam epitaxy technology under the process condition that the Torr and the nitrogen radio frequency source power is 350W.
Setting the temperature to 600 ℃, the nitrogen flow rate to 0.6sccm, and the balance vapor pressure of the gallium beam is 3.5X10 -7 And (3) under the process condition that the Torr and the nitrogen radio frequency source power are 350W, a GaN channel layer with the thickness of 500nm is epitaxially grown on the AlN nucleation layer by using a molecular beam epitaxy technology.
Setting the temperature to 600 ℃, the nitrogen flow rate to 0.6sccm, and the aluminum beam balance vapor pressure to 0.6X10 -7 And (3) under the process condition that the Torr and the nitrogen radio frequency source power are 350W, an AlN insert layer with the thickness of 1nm is epitaxially grown on the GaN channel layer by using a molecular beam epitaxy technology.
Setting the temperature to 650 ℃, the nitrogen flow rate to 0.6sccm, and the scandium beam balance vapor pressure to 0.5X10 -7 Torr, aluminum beam balance vapor pressure of 0.6X10 -7 Torr, nitrogen radio frequency source power of 350W, and 6nm Sc on AlN insert layer by using molecular beam epitaxy technology 0.18 Al 0.82 An N barrier layer.
Setting the temperature to 650 ℃, the nitrogen flow rate to 0.6sccm, and the scandium beam balance vapor pressure to 0.5X10 -7 Torr, aluminum beam balance vapor pressure of 0.6X10 -7 Under the process condition that Torr and nitrogen radio frequency source power is 350W, molecular beam epitaxy technology is used for Sc 0.18 Al 0.82 Epitaxy on N barrier layer, sc of 500nm 0.18 Al 0.82 An N-piezoelectric ferroelectric layer.
At Sc 0.18 Al 0.82 The N piezoelectric ferroelectric layer uses photoresist as mask, selects field effect transistor manufacturing area, sets Cl 2 The flow is 20sccm, the pressure of the reaction chamber is 15mTorr, the electrode power is 220W, and the Sc is partially calculated 0.18 Al 0.82 The N-piezoelectric ferroelectric layer is thinned to 50nm.
Step 7, etching the selected layers using a dry etching technique, as shown in fig. 5 (g).
In thinned Sc 0.18 Al 0.82 Making mask on N piezoelectric ferroelectric layer, setting Cl 2 The flow is 20sccm, the pressure of the reaction chamber is 15mTorr, the electrode power is 220W, and Sc thinned in the source-drain ohmic contact region is removed 0.18 Al 0.82 N piezoelectric ferroelectric layer, sc 0.18 Al 0.82 And forming a source-drain ohmic contact region groove by the N barrier layer, the AlN inserting layer and a part of the GaN channel layer.
And 8, epitaxially doping the Si-doped n-type GaN layer by using a molecular beam epitaxy technology to form an ohmic contact region, as shown in fig. 5 (h).
Setting the temperature to 600 ℃, the nitrogen flow rate to 0.6sccm, and the balance vapor pressure of the gallium beam is 3.5X10 -7 Torr, silicon beam balance vapor pressure of 1.6X10 -8 Under the process condition that the Torr and the nitrogen radio frequency source power are 350W, si with the thickness of 60nm is deposited in the grooves of the source-drain ohmic contact areas, and the doping concentration of Si is 0.5X10 20 cm -3 N-type GaN layer of (a).
Step 9, using electron beam evaporation technique to make source electrode, drain electrode and interdigital electrode, as shown in fig. 5 (i).
9.1 Sc) in partial thinning 0.18 Al 0.82 Making mask on N piezoelectric ferroelectric, setting vacuum degree smaller than 1.4X10 - 3 Pa, the power range is 400-800W, the evaporation rate is
Respectively depositing Ti/Al/Ni/Au metal combinations on the source-drain ohmic contact regions, wherein the metal thickness is 0.05 mu m/0.12 mu m/0.08 mu m; then carrying out 30s rapid thermal annealing in nitrogen atmosphere with the temperature of 830 ℃ to manufacture a source electrode and a drain electrode;
9.2 In un-thinned Sc) 0.18 Al 0.82 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting a manufacturing area of the surface acoustic wave device, and setting the vacuum degree to be less than 1.4x10 -3 Pa, the power range is 400-800W, the evaporation rate is
Under the conditions of the process of (1) under which Sc is not thinned 0.18 Al 0.82 A Ti/Au metal combination is deposited on the N piezoelectric ferroelectric layer, and the metal thickness is 0.05 mu m/0.08 mu m.
Step 10, using electron beam evaporation technique to fabricate the gate electrode, as shown in fig. 5 (j).
Sc in field effect transistor manufacturing region thinning 0.18 Al 0.82 Making mask on N piezoelectric ferroelectric layer, selecting gate electrode making region, setting vacuum degree smaller than 1.4X10 -3 Pa, the power range is 400-800W, the evaporation rate is
In the thinned Sc 0.18 Al 0.82 And depositing Ni/Au metal combination on the N piezoelectric ferroelectric layer, wherein the metal thickness is 0.04 mu m/0.5 mu m, and completing the manufacture of the gate electrode.
Step 11, using an inductively coupled plasma process, a via recess is formed, as shown in fig. 5 (k).
Setting Cl by using gate electrode metal as mask and adopting inductive coupling plasma process 2 The air flow was 10sccm, BCl 3 The air flow is 25sccm, the etching time is 50s, and the thinned Sc outside the gate electrode of the field effect transistor manufacturing area is removed 0.18 Al 0.82 And the N piezoelectric ferroelectric layer is used for forming a gate-source conducting region groove and a gate-drain conducting region groove.
At step 12, a dry etching process is used to form a separation of the two device fabrication regions, as shown in fig. 5 (l).
Setting Cl by taking photoresist as mask 2 And etching the piezoelectric ferroelectric layer of the surface acoustic wave device manufacturing area and the field effect transistor manufacturing area to the bottom of the GaN channel under the process conditions that the flow is 20sccm, the pressure of the reaction chamber is 15mTorr, and the electrode power is 220W, so as to form a separation area.
Step 13, depositing Al by atomic layer deposition process 2 O 3 Passivation layer as in fig. 5 (m).
Setting the time to 40s, the pressure to 2000mTorr, the temperature to 300 ℃, al (CH) 3 ) 3 Flow is 850sccm, H 2 O flow is 350sccm, N 2 Under the process condition of 1000sccm flow, depositing Al with thickness of 50nm on the surface acoustic wave device manufacturing area, the field effect transistor manufacturing area and the separation area by using an atomic layer deposition process 2 O 3 And a passivation layer.
Step 14, at Al 2 O 3 Gate electrode through holes, source electrode through holes, drain electrode through holes and interdigital electrode through holes are prepared on the passivation layer, as shown in fig. 5 (n).
Taking photoresist as a mask, adopting a reactive ion etching method, setting the pressure to 1500mTorr, and setting the power to 200W and SF 6 Flow rate of 8sccm, CHF 3 Etching Al under the process conditions of 10sccm and He flow of 150sccm 2 O 3 And forming a gate electrode through hole, a source electrode through hole, a drain electrode through hole and an interdigital electrode through hole on the metal surfaces of the electrodes respectively by the passivation layer.
Step 15, using optical lithography and electron beam evaporation method to draw out each electrode Pad on each electrode through hole, completing the monolithic integrated circuit fabrication, as shown in fig. 5 (o).
Firstly, respectively forming electrode Pad patterns on electrode through holes by using a traditional optical lithography process; after which setting is carried out
An Au metal with the thickness of 80nm is evaporated on the patterns of each electrode Pad by using an electron beam and then soaked by acetone to respectively form a gate electrode Pad and a source electrode which are interconnected with the gate electrode, the source electrode, the drain electrode and the interdigital electrodeThe electrode Pad, the drain electrode Pad and the interdigital electrode Pad are used for completing the manufacture of the monolithic integrated circuit.
Embodiment three, al is fabricated on an aluminum nitride substrate using a metal organic chemical vapor deposition technique 0.25 Ga 0.75 N barrier layer, sc 0.3 Al 0.7 Nitride surface acoustic wave devices and field effect transistor monolithic integrated circuits of N piezoelectric ferroelectric layers.
Step a, an AlN nucleation layer is deposited, as shown in fig. 5 (a).
An AlN nucleation layer with an epitaxial thickness of 1000nm is formed on an aluminum nitride substrate by using a metal organic chemical vapor deposition technology under the process conditions that the epitaxial temperature is 1200 ℃, the pressure is 45Torr, the aluminum source flow is 18.0sccm, the ammonia flow is 3500sccm and the hydrogen flow is 2500sccm.
Step B, depositing a GaN channel layer, as shown in FIG. 5 (B).
A GaN channel layer with 4000nm thickness is deposited on the AlN nucleation layer by using a metal organic chemical vapor deposition technology under the process conditions of 1200 ℃, 45Torr pressure, 3500sccm ammonia gas flow, 180sccm gallium source flow and 2500sccm hydrogen gas flow.
Step C, depositing an AlN insert layer as shown in FIG. 5 (C)
An AlN insert layer with the thickness of 2nm is deposited on the GaN channel layer by using a metal organic chemical vapor deposition technology under the process conditions of 1200 ℃, 45Torr pressure, 18sccm aluminum source flow, 3500sccm ammonia gas flow and 2500sccm hydrogen gas flow.
Step D, depositing Al 0.25 Ga 0.75 An N barrier layer as in fig. 5 (d).
Using metal organic chemical vapor deposition technique, adopting process conditions of 1200 deg.C, 45Torr pressure, 10sccm aluminum source flow, 80sccm gallium source flow, 3500sccm ammonia gas flow and 2500sccm hydrogen gas flow, depositing 30nm thick Al on AlN insert layer 0.25 Ga 0.75 An N barrier layer.
Step E, depositing Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer as in fig. 5 (e).
Using metalThe organic chemical vapor deposition technology adopts the process conditions of 1200 ℃ temperature, 80Torr pressure, 10sccm aluminum source flow, 3000sccm scandium source flow, 3500sccm ammonia gas flow and 2500sccm hydrogen gas flow, and the process conditions are that the temperature is 1200 ℃, the pressure is 80Torr, the aluminum source flow is 10sccm, the scandium source flow is 3000sccm, the ammonia gas flow is 3500sccm, the hydrogen gas flow is 2500sccm, the process is that the process is as follows 0.25 Ga 0.75 Deposition of Sc with a thickness of 1500nm on the N barrier layer 0.3 Al 0.7 An N-piezoelectric ferroelectric layer.
Step F, dry etching, thinning part Sc 0.3 Al 0.7 N piezoelectric ferroelectric layer as in fig. 5 (f).
At Sc 0.3 Al 0.7 The N piezoelectric ferroelectric layer uses photoresist as mask, selects field effect transistor manufacturing area, uses dry etching technology, adopts Cl 2 Flow is 18sccm, reaction chamber pressure is 12mTorr, electrode power is 160W, and Sc is thinned 0.3 Al 0.7 N piezoelectric ferroelectric layer to 80nm.
And G, dry etching to form a groove of the source-drain ohmic contact region, as shown in fig. 5 (G).
In thinned Sc 0.3 Al 0.7 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting a source-drain ohmic contact area of a field effect transistor by taking photoresist as the mask, and adopting Cl by using a dry etching technology 2 The flow is 18sccm, the pressure of the reaction chamber is 12mTorr, the electrode power is 160W, and Sc is removed respectively 0.3 Al 0.7 On the N piezoelectric ferroelectric layer, al 0.25 Ga 0.75 And forming a source-drain ohmic contact region groove by the N barrier layer, the AlN inserting layer and a part of the GaN channel layer.
And step H, depositing a Si doped n-type GaN layer to form an ohmic contact region, as shown in fig. 5 (H).
Depositing Si doping concentration of 5 multiplied by 10 with thickness of 120nm in the grooves of the source-drain ohmic contact region under the process conditions that the temperature is 1200 ℃, the pressure is 45Torr, the gallium source flow is 60sccm, the silicon source flow is 800sccm, the ammonia flow is 3500sccm and the hydrogen flow is 2500sccm 20 cm -3 N-type GaN layer of (a).
Step I, manufacturing a source electrode, a drain electrode and an interdigital electrode, as shown in (I) of fig. 5.
I.1 At thinned Sc) 0.3 Al 0.7 N piezoelectric ferroelectricMaking mask on the layer, and vacuum evaporating to a degree of less than 1.6X10 -3 Pa, the power range is 600-900W, the evaporation rate is
And depositing metal on the source-drain ohmic contact regions respectively, wherein the deposited metal adopts a Ti/Al/Ni/Au metal combination, and the metal thickness is 0.02 mu m/0.2 mu m/0.05 mu m.
I.2 In un-thinned Sc) 0.3 Al 0.7 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting a surface acoustic wave device manufacturing area, and performing vacuum degree less than 1.6X10 -3 Pa, the power range is 600-900W, the evaporation rate is
Using electron beam evaporation technique in the un-thinned Sc 0.3 Al 0.7 A Ti/Au metal combination is deposited on the N piezoelectric ferroelectric layer, and the metal thickness is 0.02 mu m/0.05 mu m.
Step J, manufacturing a gate electrode as shown in fig. 5 (J).
In thinned Sc 0.3 Al 0.7 Manufacturing a mask on the N piezoelectric ferroelectric layer, selecting a gate electrode manufacturing area region, and adopting an electron beam evaporation technology to manufacture a mask on the Sc 0.3 Al 0.7 On the N piezoelectric ferroelectric layer, the vacuum degree is less than 1.5X10 -3 Pa, the power range is 300-800W, the evaporation rate is
Wherein the deposited metal is a combination of Ni/Au metal and the metal thickness is 0.03 μm/0.4 μm.
Step K, etching the gate-source conductive region and the gate-drain conductive region, as shown in fig. 5 (K).
Using gate electrode metal as mask, adopting inductively coupled plasma etching process, and forming a mask on Cl 2 The air flow was 10sccm, BCl 3 Under the process condition that the air flow is 25sccm and the etching time is 200s, removing the thinned Sc of the gate-source conducting region and the gate-drain conducting region 0.3 Al 0.7 Forming a gate-source conducting region groove and a gate drain on the N piezoelectric ferroelectric layerAnd the conducting area is provided with a groove.
Step L, the saw device fabrication area is isolated from the field effect transistor fabrication area, as shown in fig. 5 (L).
Using photoresist as mask, dry etching technique, and etching in Cl 2 And etching the piezoelectric ferroelectric layers of the two devices to the bottom of the GaN channel under the process conditions of 18sccm flow, 12mTorr reaction chamber pressure and 160W electrode power to form a separation region.
Step M, depositing HfO 2 Passivation layer as in fig. 5 (m).
Using atomic layer deposition process, at a temperature of 280 ℃ for 70s, a flow rate of 1200sccm of hafnium ethylamino, and H 2 O flow is 110sccm, N 2 Depositing HfO with thickness of 100nm in the surface acoustic wave device manufacturing area, the field effect transistor manufacturing area and the separation area under the process condition of flow of 1000sccm 2 And a passivation layer.
Step N, in HfO 2 The gate electrode via, the source electrode via, the drain electrode via, and the interdigital electrode via are etched on the passivation layer, as shown in fig. 5 (n).
The photoresist is used as a mask, and a reactive ion etching method is adopted, wherein the pressure is 1500mTorr, the power is 200W and SF 6 Flow rate of 8sccm, CHF 3 Under the process conditions of 10sccm and He flow of 150sccm, hfO is etched 2 And forming a gate electrode through hole, a source electrode through hole, a drain electrode through hole and an interdigital electrode through hole on the metal surfaces of the gate electrode, the source electrode, the drain electrode and the interdigital electrode respectively by the passivation layer.
Step O, extracting each electrode Pad on each electrode through hole, as shown in fig. 5 (O).
Photoetching to form metal Pad patterns of a gate electrode, a source electrode and a drain electrode by adopting a traditional optical photoetching process; on each electrode Pad pattern, electron beam evaporation technique is used to
Au metal having a thickness of 80nm is evaporated at a rate of 80nm and then immersed in acetone to form a gate electrode Pad, a source electrode Pad, a drain electrode Pad and an interdigital electrode which are interconnected with the gate electrode, the source electrode, the drain electrode and the interdigital electrode, respectivelyAnd electrode Pad, and completing the manufacture of the monolithic integrated circuit.
The above description is only three specific examples of the invention and does not constitute any limitation of the invention, and it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles and construction of the invention, such as the substrate may use any of sapphire material, silicon material, diamond material, boron nitride material, in addition to the silicon carbide material, gallium nitride material, aluminum nitride material, etc., already used; the barrier layer being In addition to the In already employed 0.17 Al 0.83 N、Sc 0.18 Al 0.82 N、Al 0.25 Ga 0.75 N, x is not less than 0 and not more than 0.3, y is not less than 0 and not more than 0.3, and z is not less than 0 can be used<1，0≤w<1 and x+y+z+w=1, sc having a thickness of 6nm to 30nm x In y Al z Ga w An N material; piezoelectric ferroelectric layer other than Sc already used 0.1 Al 0.9 N、Sc 0.18 Al 0.82 N、Sc 0.3 Al 0.7 N may also employ component 0<m<0.35, and m+n=1, and a thickness of 500nm-1500nm m Al n An N material; such modifications and variations based on the inventive idea are still within the scope of the claims of the present invention.
Claims (10)
1. A monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, comprising, from bottom to top, a substrate (1), a nucleation layer (2), a channel layer (3), an insertion layer (4) and a barrier layer (5), characterized in that:
a piezoelectric ferroelectric layer (6) is additionally arranged on the barrier layer (5), and an interdigital electrode and a gate electrode are arranged on the upper part of the piezoelectric ferroelectric layer (6);
the channel layer (3), the insertion layer (4), the barrier layer (5) and the etched grooves in the piezoelectric ferroelectric layer (6) form separation areas and are filled with passivation layers (7);
the piezoelectric ferroelectric layer (6) at one side of the separation region and the interdigital electrode at the upper part of the separation region form a nitride surface acoustic wave device, and the other side of the separation region is provided with an ohmic contact region, a source electrode and a drain electrode, and forms a nitride field effect transistor together with the channel layer (3), the insertion layer (4), the barrier layer (5), the piezoelectric ferroelectric layer (6), the passivation layer (7) and the gate electrode;
the nitride surface acoustic wave device and the nitride field effect transistor share the piezoelectric ferroelectric layer (6) and are isolated by a separation area, and the nitride surface acoustic wave device and the nitride field effect transistor do not interfere with each other in operation.
2. The integrated circuit of claim 1, wherein:
the piezoelectric ferroelectric layer (6) is formed by continuous epitaxy of single crystal Sc m Al n N material, wherein component 0<m<0.35, and m+n=1, thickness 500nm-1500nm;
the barrier layer (5) is Sc x In y Al z Ga w N material, wherein x is more than or equal to 0 and less than or equal to 0.3, y is more than or equal to 0 and less than or equal to 0.3, and z is more than or equal to 0<1，0≤w<1 and x+y+z+w=1, and the thickness is 6nm to 30nm.
3. The integrated circuit of claim 1, wherein:
the channel layer (3) is made of GaN material and has the thickness of 500-4000 nm;
the nucleation layer (2) is made of AlN material and has a thickness of 3nm-1000nm;
the inserting layer (4) is made of AlN material and has a thickness of 1nm-2nm.
4. The integrated circuit of claim 1, wherein:
the substrate (1) is made of any one of a sapphire material, a silicon carbide material, a diamond material, a gallium nitride material, an aluminum nitride material and a boron nitride material.
The passivation layer (7) adopts SiN material and Al 2 O 3 Material, hfO 2 Any one of the materials.
5. A method of fabricating a monolithic integrated circuit of a nitride surface acoustic wave device and a field effect transistor, comprising the steps of:
1) Growing an AlN nucleation layer (2) of 3-1000 nm on a substrate (1) by using a metal organic chemical vapor deposition technology or a molecular beam epitaxy technology;
2) Growing a GaN channel layer (3) with the thickness of 500-4000 nm on the AlN nucleation layer (2) by using a metal organic chemical vapor deposition method or a molecular beam epitaxy technology;
3) Growing an AlN insert layer (4) with the thickness of 1-2 nm on the GaN channel layer (3) by using a metal organic chemical vapor deposition method or a molecular beam epitaxy technology;
4) Using a metal organic chemical vapor deposition method or a molecular beam epitaxy technique to grow a barrier layer (5) with a thickness of 6nm-30nm on the AlN insert layer (4);
5) Using a metal organic chemical vapor deposition method or a molecular beam epitaxy technique to grow a piezoelectric ferroelectric layer (6) with a thickness of 500-1500 nm on the barrier layer (5);
6) Selecting a field effect transistor manufacturing area on the piezoelectric ferroelectric layer (6) by taking photoresist as a mask, and carrying out partial thinning on the piezoelectric ferroelectric layer (6) to 30-80 nm by using a dry etching process;
7) Selecting source-drain ohmic contact areas of field effect transistors on the thinned piezoelectric ferroelectric layer (6) by taking photoresist as a mask, and etching the thinned piezoelectric ferroelectric layer (6) until reaching the upper part of the channel layer (3) by adopting a dry etching method to form source-drain ohmic contact area grooves;
8) Growing Si doped n-type GaN layer in the groove of the source-drain ohmic contact region by using a metal organic chemical vapor deposition method or a molecular beam epitaxy method, wherein the dosage of Si is (0.5-5) multiplied by 10 20 cm -3 Forming an ohmic contact region;
9) Depositing ohmic contact metal Ti/Al/Ni/Au in an ohmic contact area by adopting an electron beam evaporation process by taking photoresist as a mask, and annealing at 830 ℃ under nitrogen atmosphere to form a source electrode and a drain electrode;
10 Using photoresist as a mask, selecting a manufacturing area of the surface acoustic wave device, and adopting an electron beam evaporation process to deposit metal Ti/Au on the non-thinned piezoelectric ferroelectric layer (6) to form interdigital electrodes of the surface acoustic wave device;
11 Setting a gate electrode region on the piezoelectric ferroelectric layer (6) thinned in the field effect transistor region by taking photoresist as a mask, and depositing metal Ni/Au in the region by adopting an electron beam evaporation process to form a gate electrode;
12 Using gate electrode metal as mask, adopting inductively coupled plasma etching method, using BCl 3 /Cl 2 The gas source is used for completely etching the piezoelectric ferroelectric layer (6) outside the gate electrode of the field effect transistor manufacturing area to form a groove;
13 Using the photoresist as a mask, and etching the piezoelectric ferroelectric layer (6) to the bottom of the GaN channel layer (3) by using a dry etching process to form a separation region;
14 A passivation layer with the thickness of 50nm-200nm is deposited in the manufacturing area of the surface acoustic wave device, the manufacturing area of the field effect transistor and the separation area by adopting a plasma enhanced chemical vapor deposition method or an atomic layer deposition process;
15 Using photoresist as mask, adopting reactive ion etching method, using SF 6 A gas source for etching the passivation layer to form a gate electrode through hole, a source electrode through hole, a drain electrode through hole and an interdigital electrode through hole;
16 Forming interdigital electrode Pad patterns in the surface acoustic wave device manufacturing area, forming gate electrode, source electrode and drain electrode Pad patterns in the field effect transistor manufacturing area, evaporating Au metal layers on the electrode Pad patterns by using photoresist as a mask and adopting an electron beam evaporation process to form metal leads between the electrode Pad patterns and the electrodes respectively, thereby completing the preparation of the monolithic integrated circuit.
6. The method of manufacturing according to claim 5, wherein:
the metal organic chemical vapor deposition process conditions in the steps 1) -3) are as follows:
the temperature is 950-1250 ℃;
the pressure is 40Torr-50Torr;
the flow rate of the aluminum source is 3sccm-20sccm;
the flow rate of the gallium source is 60sccm-200sccm;
the ammonia flow is 3500sccm;
the hydrogen flow rate was 2500sccm.
7. The method of manufacturing according to claim 5, wherein:
the molecular beam epitaxy process conditions in steps 1) -3) are as follows:
the temperature is 600-750 ℃;
the flow rate of the nitrogen is 0.6sccm-3.0sccm;
aluminum beam leveling vapor pressure of 0.6X10 -7 Torr-3.2×10 -7 Torr；
Gallium beam balance vapor pressure 3.5X10 -7 Torr-9.5×10 -7 Torr；
The power of the nitrogen radio frequency source is 350W.
8. The method of manufacturing according to claim 5, wherein:
the metal organic chemical vapor deposition process conditions in the step 4) are as follows:
the temperature is 950-1250 ℃;
the pressure is 40Torr-100Torr;
scandium source flow is 2000sccm-5000sccm;
the flow rate of the aluminum source is 3sccm-20sccm;
the flow rate of the gallium source is 60sccm-200sccm;
the flow rate of the indium source is 50sccm-120sccm;
the ammonia flow is 3500sccm;
the hydrogen flow rate was 2500sccm.
9. The method of manufacturing according to claim 5, wherein:
the metal organic chemical vapor deposition method in the step 5) comprises the following process conditions:
the temperature is 950-1250 ℃;
the pressure is 40Torr-100Torr;
scandium source flow is 2000sccm-5000sccm;
the flow rate of the aluminum source is 3sccm-20sccm;
the ammonia flow is 3500sccm;
the hydrogen flow rate was 2500sccm.
10. The method of manufacturing according to claim 4, wherein:
the molecular beam epitaxy method in the steps 4) -5) has the following process conditions:
the temperature is 600-750 ℃;
the flow rate of the nitrogen is 0.6sccm-3.0sccm;
aluminum beam leveling vapor pressure of 0.6X10 -7 Torr-3.2×10 -7 Torr；
Gallium beam balance vapor pressure 3.5X10 -7 Torr-9.5×10 -7 Torr；
Scandium beam balance vapor pressure of 0.2X10 -7 Torr-0.5×10 -7 Torr；
Indium beam balance vapor pressure 0.8X10 -7 Torr-2.1×10 -7 Torr；
The power of the nitrogen radio frequency source is 350W.
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