CN116054334A - Power supply control circuit, method, electronic device, storage medium, and program product - Google Patents

Power supply control circuit, method, electronic device, storage medium, and program product Download PDF

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Publication number
CN116054334A
CN116054334A CN202310046259.9A CN202310046259A CN116054334A CN 116054334 A CN116054334 A CN 116054334A CN 202310046259 A CN202310046259 A CN 202310046259A CN 116054334 A CN116054334 A CN 116054334A
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China
Prior art keywords
resistor
adc
vusb
triode
battery
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CN202310046259.9A
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CN116054334B (en
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邱辉辉
张黎明
林嵘
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Yunma Intelligent Hainan Technology Co ltd
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Yunma Intelligent Hainan Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The embodiment of the disclosure discloses a power supply control circuit, a method, an electronic device, a storage medium and a program product, wherein the power supply control circuit comprises: the battery charging control circuit, the 3.3V power supply circuit and the ADC sampling circuit are connected with the CPU, and the 3.3V power input circuit is connected with the battery charging control circuit and the battery. The technical scheme is simple to realize and convenient to operate, can effectively ensure the charging stability of the electronic equipment, and can greatly promote the use experience of a user.

Description

Power supply control circuit, method, electronic device, storage medium, and program product
Technical Field
The embodiment of the disclosure relates to the technical field of power supply control, in particular to a power supply control circuit, a power supply control method, electronic equipment, a storage medium and a program product.
Background
At present, a battery of electronic equipment such as a terminal is charged mainly by adopting a fixed current charging mode, wherein a 5V voltage charger is used by many electronic equipment so as to be compatible with various charging modes such as a charger, a computer USB port charging mode and the like. However, the 5V voltage chargers on the market have a lot of specifications and different carrying capacities, if the electronic equipment is designed to be charged only by adopting a fixed current, the situation that many chargers can not normally charge the electronic equipment can occur, and usually, the electronic equipment can not be prompted at this time, so that a user does not know the individual reason, the use experience of the user is greatly affected, and therefore, a power supply control scheme capable of realizing the charging current switching of the electronic equipment and guaranteeing the charging stability of the electronic equipment needs to be designed.
Disclosure of Invention
Embodiments of the present disclosure provide a power supply control circuit, method, electronic device, storage medium, and program product.
In a first aspect, a power supply control circuit is provided in an embodiment of the present disclosure.
Specifically, the power supply control circuit includes:
the battery charging control circuit, the 3.3V power supply circuit and the ADC sampling circuit are connected with the CPU, and the 3.3V power input circuit is connected with the battery charging control circuit and the battery, wherein:
the CPU processor is used for processing the voltage change detected by the ADC sampling circuit and sending a corresponding charging current switching control signal to the battery charging control circuit;
the battery charging control circuit is used for controlling the charging operation of the battery and the switching of different charging current according to the control of the CPU;
the 3.3V power supply circuit is used for providing electric energy for the CPU processor after the external charger power supply VUSB is inserted, so that the normal operation of the CPU processor is ensured;
the ADC sampling circuit is used for detecting the voltage change of the inserted external charger power supply VUSB and feeding back to the CPU processor;
the 3.3V power input circuit is used for charging the battery according to the current output by the battery charging control circuit.
In one embodiment of the present disclosure, the 3.3V power input circuit includes: the first diode D1, the first resistor R11, the second resistor R12 and the MOS transistor Q4, wherein:
the anode of the first diode D1 is connected with an external charger power supply VUSB, and the cathode of the first diode D1 is connected with the source electrode of the MOS tube Q4 and the 4.2-volt voltage end V4.2;
the drain electrode of the MOS tube Q4 is connected with an external battery VBAT, and the grid electrode is connected with one end of a first resistor R11 and one end of a second resistor R12;
the other end of the first resistor R11 is connected with an external charger power supply VUSB;
the other end of the second resistor R12 is grounded.
In one embodiment of the present disclosure, the 3.3V power supply circuit includes: the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C70, the third resistor R13, the fourth resistor R14, the fifth resistor R15 and the second chip U2, wherein:
one end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is connected with the 4.2 volt voltage end V4.2 and the input end Vin of the second chip U2;
one end of the third resistor R13 is connected with an external charger power supply VUSB, and the other end of the third resistor R is connected with an enabling pin CE of the second chip U2;
one end of the fourth resistor R14 is connected with a 3.3V control enabling signal VDD330UT of the CPU processor, and the other end of the fourth resistor R14 is connected with an enabling pin CE of the second chip U2, one end of the fifth resistor R15 and one end of the fourth capacitor C70;
the other ends of the fifth resistor R15 and the fourth capacitor C70 are grounded;
one end of the second capacitor C2 and one end of the third capacitor C3 are connected to the output terminal Vout of the second chip U2 and the 3.3 volt voltage terminal V3.3, and the other end is grounded.
In one embodiment of the present disclosure, the battery charge control circuit includes: sixth resistor R1, seventh resistor R2, eighth resistor R3, ninth resistor R4, tenth resistor R5, eleventh resistor R6, twelfth resistor R18, thirteenth resistor R19, fifth capacitor C63, first chip U1, first triode Q1, second triode Q2, wherein:
one end of the sixth resistor R1 is connected with the current control pin PROG of the first chip U1, and the other end of the sixth resistor R1 is grounded;
one end of the seventh resistor R2 is connected with the current control pin PROG of the first chip U1, and the other end of the seventh resistor R2 is connected with the collector electrode of the second triode Q2;
one end of the eighth resistor R3 is connected with the current control pin PROG of the first chip U1, and the other end of the eighth resistor R3 is connected with the collector electrode of the first triode Q1;
one end of the ninth resistor R4 is connected with a first charging current control signal CHG_900mA output by the CPU processor, and the other end of the ninth resistor R4 is connected with the base electrode of the first triode Q1 and one end of the twelfth resistor R18;
the emitter of the first triode Q1 is grounded;
one end of the tenth resistor R5 is connected with a second charging current control signal CHG_600mA output by the CPU processor, and the other end of the tenth resistor R5 is connected with the base electrode of the second triode Q2 and one end of the thirteenth resistor R19;
the emitter of the second triode Q2 is grounded;
one end of the eleventh resistor R6 is connected with an external charger power supply VUSB, and the other end of the eleventh resistor R6 is connected with an enabling pin CE of the first chip U1;
the other end of the twelfth resistor R18 is grounded;
the other end of the thirteenth resistor R19 is grounded;
one end of the fifth capacitor C63 is connected to the external charger power VUSB and the power input pin VCC of the first chip U1, and the other end is grounded;
the battery pin of the first chip U1 is connected to the external battery terminal VBAT.
In one embodiment of the present disclosure, the ADC sampling circuit includes: a fourteenth resistor R16 and a fifteenth resistor R17, wherein:
one end of the fourteenth resistor R16 is connected with an external charger power supply VUSB, and the other end of the fourteenth resistor R17 is connected with one end of the fifteenth resistor R17 and an ADC detection signal VUSB_ADC output by the CPU processor;
one end of the fifteenth resistor R17 is connected with one end of the fourteenth resistor R16, and the other end of the ADC detection signal VUSB_ADC is grounded, wherein the ADC detection signal VUSB_ADC is output by the CPU processor.
In an embodiment of the present disclosure, the CPU processor outputs an ADC detection signal vusb_adc, a 3.3V control enable signal VDD33OUT, a first charge current control signal chg_900mA, and a second charge current control signal chg_600ma, wherein:
the ADC detection signal VUBS_ADC is connected with a fourteenth resistor R16 and a fifteenth resistor R17 of the ADC sampling circuit;
the 3.3V control enabling signal VDD330UT is connected to a fourth resistor R14 of the 3.3V power supply circuit;
the first charging current control signal CHG_900mA is connected with a ninth resistor R4 of the battery charging control circuit;
the second charging current control signal chg_600ma is connected to a tenth resistor R5 of the battery charging control circuit.
In one embodiment of the present disclosure,
after the CPU processor enters a working state, a first charging current control signal CHG_900mA and a second charging current control signal CHG_600mA are pulled down, at the moment, a first triode Q1 and a second triode Q2 of a battery charging control circuit are not conducted, and a first chip U1 processes and uses a first current to charge a battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, and if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pre-warns that the charging voltage is too low to charge normally; if the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA to enable the second triode Q2 to be conducted, pulls down the first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conducted, and the first chip U1 processes to charge the battery by using the second current;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls down a second charging current control signal CHG_600mA signal to enable the second triode Q2 to be non-conductive, pulls down a first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conductive, and the first chip U1 keeps the first current to charge the battery; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA so as to enable the second triode Q2 to be conducted, pulls up the first charging current control signal CHG_900mA so as to enable the first triode Q1 to be conducted, and the first chip U1 processes and uses the third current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls up a second charging current control signal CHG_600mA signal to enable a second triode Q2 to be conducted, pulls down a first charging current control signal CHG_900mA to enable a first triode Q1 to be non-conducted, and the first chip U1 processes to charge a battery by using a second current; if the ADC detection signal vusb_adc is higher than 4.8v, the cpu processor keeps pulling up the second charging current control signal chg_600ma signal, so that the second transistor Q2 is turned on, keeps pulling up the first charging current control signal chg_900mA, so that the first transistor Q1 is turned on, and the first chip U1 processes to charge the battery with the third current.
In a second aspect, embodiments of the present disclosure provide a power supply control method.
Specifically, the power supply control method includes:
after the CPU processor enters a working state, a first charging current control signal CHG_900mA and a second charging current control signal CHG_600mA are pulled down, at the moment, a first triode Q1 and a second triode Q2 of a battery charging control circuit are not conducted, and a first chip U1 processes and uses a first current to charge a battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, and if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pre-warns that the charging voltage is too low to charge normally; if the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA to enable the second triode Q2 to be conducted, pulls down the first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conducted, and the first chip U1 processes to charge the battery by using the second current;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls down a second charging current control signal CHG_600mA signal to enable the second triode Q2 to be non-conductive, pulls down a first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conductive, and the first chip U1 keeps the first current to charge the battery; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA so as to enable the second triode Q2 to be conducted, pulls up the first charging current control signal CHG_900mA so as to enable the first triode Q1 to be conducted, and the first chip U1 processes and uses the third current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls up a second charging current control signal CHG_600mA signal to enable a second triode Q2 to be conducted, pulls down a first charging current control signal CHG_900mA to enable a first triode Q1 to be non-conducted, and the first chip U1 processes to charge a battery by using a second current; if the ADC detection signal vusb_adc is higher than 4.8v, the cpu processor keeps pulling up the second charging current control signal chg_600ma signal, so that the second transistor Q2 is turned on, keeps pulling up the first charging current control signal chg_900mA, so that the first transistor Q1 is turned on, and the first chip U1 processes to charge the battery with the third current.
In an embodiment of the present disclosure, the first current is less than the second current, and the second current is less than the third current.
In an embodiment of the present disclosure, further comprising:
displaying charging information, wherein the charging information comprises one or more of the following information: charging early warning and charging current magnitude.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including a memory for storing one or more computer instructions for supporting a power supply control apparatus to perform the above power supply control method, and a processor configured to execute the computer instructions stored in the memory. The power control means may further comprise a communication interface for the power control means to communicate with other devices or a communication network.
In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium storing computer instructions for use by a power supply control apparatus, including computer instructions for performing the above power supply control method for use by the power supply control apparatus.
In a fifth aspect, embodiments of the present disclosure provide a computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the above-described power supply control method.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:
according to the technical scheme, the universal circuit is modified, so that the electronic equipment can automatically adjust the charging current according to different charger carrying capacities. The technical scheme is simple to realize and convenient to operate, can effectively ensure the charging stability of the electronic equipment, and can greatly promote the use experience of a user.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of embodiments of the disclosure.
Drawings
Other features, objects and advantages of the embodiments of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:
FIG. 1 shows a circuit configuration diagram of a power supply control circuit according to an embodiment of the present disclosure;
FIG. 2 shows a circuit block diagram of a 3.3V power input circuit according to an embodiment of the present disclosure;
FIG. 3 shows a circuit block diagram of a 3.3V power supply circuit according to an embodiment of the present disclosure;
fig. 4 shows a circuit configuration diagram of a battery charge control circuit according to an embodiment of the present disclosure;
FIG. 5 shows a circuit block diagram of an ADC sampling circuit according to an embodiment of the present disclosure;
FIG. 6 illustrates a flowchart of a power control method according to an embodiment of the present disclosure;
FIG. 7 shows a block diagram of an electronic device according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a computer system suitable for use in implementing a power control method according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, exemplary implementations of the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, portions irrelevant to description of the exemplary embodiments are omitted in the drawings.
In the presently disclosed embodiments, it is to be understood that the terms such as "comprises" or "comprising" and the like are intended to indicate the presence of features, numbers, steps, acts, components, portions, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility of one or more other features, numbers, steps, acts, components, portions, or combinations thereof being present or added.
In addition, it should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. Embodiments of the present disclosure will be described in detail below with reference to the attached drawings in conjunction with the embodiments.
According to the technical scheme provided by the embodiment of the disclosure, the universal circuit is modified, so that the electronic equipment can automatically adjust the charging current according to different charger carrying capacities. The technical scheme is simple to realize and convenient to operate, can effectively ensure the charging stability of the electronic equipment, and can greatly promote the use experience of a user.
Fig. 1 shows a schematic structural diagram of a power supply control circuit according to an embodiment of the present disclosure, wherein the power supply control circuit is installed in an electronic device, and as shown in fig. 1, the power supply control circuit includes a CPU processor, a battery charge control circuit, a 3.3V power supply circuit, and an ADC sampling circuit connected to the CPU processor, and a 3.3V power input circuit connected to the battery charge control circuit and a battery, wherein:
the CPU processor is used for processing the voltage change detected by the ADC sampling circuit and sending a corresponding charging current switching control signal to the battery charging control circuit;
the battery charging control circuit is used for controlling the charging operation of the battery and the switching of different charging current according to the control of the CPU;
the 3.3V power supply circuit is used for providing electric energy for the CPU processor after the external charger power supply VUSB is inserted, so that the normal operation of the CPU processor is ensured;
the ADC sampling circuit is used for detecting the voltage change of the inserted external charger power supply VUSB and feeding back to the CPU processor;
the 3.3V power input circuit is used for charging the battery according to the current output by the battery charging control circuit.
Fig. 2 shows a circuit configuration diagram of a 3.3V power input circuit according to an embodiment of the present disclosure, as shown in fig. 2, in an embodiment of the present invention, the 3.3V power input circuit includes: the first diode D1, the first resistor R11, the second resistor R12 and the MOS transistor Q4, wherein:
the anode of the first diode D1 is connected with an external charger power supply VUSB, and the cathode of the first diode D1 is connected with the source electrode of the MOS tube Q4 and the 4.2-volt voltage end V4.2;
the drain electrode of the MOS tube Q4 is connected with an external battery VBAT, and the grid electrode is connected with one end of a first resistor R11 and one end of a second resistor R12;
the other end of the first resistor R11 is connected with an external charger power supply VUSB;
the other end of the second resistor R12 is grounded.
Fig. 3 shows a circuit configuration diagram of a 3.3V power supply circuit according to an embodiment of the present disclosure, as shown in fig. 3, in an embodiment of the present invention, the 3.3V power supply circuit includes: the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C70, the third resistor R13, the fourth resistor R14, the fifth resistor R15 and the second chip U2, wherein:
one end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is connected with the 4.2 volt voltage end V4.2 and the input end Vin of the second chip U2;
one end of the third resistor R13 is connected with an external charger power supply VUSB, and the other end of the third resistor R is connected with an enabling pin CE of the second chip U2;
one end of the fourth resistor R14 is connected with a 3.3V control enabling signal VDD330UT of the CPU processor, and the other end of the fourth resistor R14 is connected with an enabling pin CE of the second chip U2, one end of the fifth resistor R15 and one end of the fourth capacitor C70;
the other ends of the fifth resistor R15 and the fourth capacitor C70 are grounded;
one end of the second capacitor C2 and one end of the third capacitor C3 are connected to the output terminal Vout of the second chip U2 and the 3.3 volt voltage terminal V3.3, and the other end is grounded.
The 3.3V power supply circuit pulls up the enable pin CE of the second chip U2 through the insertion of the external charger power supply VUSB, so that the second chip U2 can output the 3.3V power supply for the CPU processor to work.
Fig. 4 shows a circuit configuration diagram of a battery charge control circuit according to an embodiment of the present disclosure, as shown in fig. 4, in an embodiment of the present invention, the battery charge control circuit includes: sixth resistor R1, seventh resistor R2, eighth resistor R3, ninth resistor R4, tenth resistor R5, eleventh resistor R6, twelfth resistor R18, thirteenth resistor R19, fifth capacitor C63, first chip U1, first triode Q1, second triode Q2, wherein:
one end of the sixth resistor R1 is connected with the current control pin PROG of the first chip U1, and the other end of the sixth resistor R1 is grounded;
one end of the seventh resistor R2 is connected with the current control pin PROG of the first chip U1, and the other end of the seventh resistor R2 is connected with the collector electrode of the second triode Q2;
one end of the eighth resistor R3 is connected with the current control pin PROG of the first chip U1, and the other end of the eighth resistor R3 is connected with the collector electrode of the first triode Q1;
one end of the ninth resistor R4 is connected with a first charging current control signal CHG_900mA output by the CPU processor, and the other end of the ninth resistor R4 is connected with the base electrode of the first triode Q1 and one end of the twelfth resistor R18;
the emitter of the first triode Q1 is grounded;
one end of the tenth resistor R5 is connected with a second charging current control signal CHG_600mA output by the CPU processor, and the other end of the tenth resistor R5 is connected with the base electrode of the second triode Q2 and one end of the thirteenth resistor R19;
the emitter of the second triode Q2 is grounded;
one end of the eleventh resistor R6 is connected with an external charger power supply VUSB, and the other end of the eleventh resistor R6 is connected with an enabling pin CE of the first chip U1;
the other end of the twelfth resistor R18 is grounded;
the other end of the thirteenth resistor R19 is grounded;
one end of the fifth capacitor C63 is connected to the external charger power VUSB and the power input pin VCC of the first chip U1, and the other end is grounded;
the battery pin of the first chip U1 is connected to the external battery terminal VBAT.
The battery charging control circuit pulls up the enable pin CE of the first chip U1 through the insertion of the external charger power supply VUSB, so that the first chip U1 can start charging.
Fig. 5 shows a circuit configuration diagram of an ADC sampling circuit according to an embodiment of the disclosure, as shown in fig. 5, in an embodiment of the invention, the ADC sampling circuit includes: a fourteenth resistor R16 and a fifteenth resistor R17, wherein:
one end of the fourteenth resistor R16 is connected with an external charger power supply VUSB, and the other end of the fourteenth resistor R17 is connected with one end of the fifteenth resistor R17 and an ADC detection signal VUSB_ADC output by the CPU processor;
one end of the fifteenth resistor R17 is connected with one end of the fourteenth resistor R16, and the other end of the ADC detection signal VUSB_ADC is grounded, wherein the ADC detection signal VUSB_ADC is output by the CPU processor.
In one embodiment of the present invention, the CPU processor outputs an ADC detection signal vusb_adc, a 3.3V control enable signal VDD33OUT, a first charge current control signal chg_900mA, and a second charge current control signal chg_600ma, wherein:
the ADC detection signal VUBS_ADC is connected with a fourteenth resistor R16 and a fifteenth resistor R17 of the ADC sampling circuit;
the 3.3V control enabling signal VDD330UT is connected to a fourth resistor R14 of the 3.3V power supply circuit;
the first charging current control signal CHG_900mA is connected with a ninth resistor R4 of the battery charging control circuit;
the second charging current control signal chg_600ma is connected to a tenth resistor R5 of the battery charging control circuit.
The CPU processor detects an ADC detection signal VUSB_ADC, and controls a second charging current control signal CHG_600mA and a first charging current control signal CHG_900mA according to the signal change of the collected ADC detection signal VUSB_ADC, so that the charging current is controlled.
Based on the power supply control circuit, through real-time detection of the ADC detection signal VUSB_ADC, the second charging current control signal CHG_600mA and the first charging current control signal CHG_900mA can be controlled, so that different charging current magnitudes can be switched, and the battery is in an optimal stable charging state. Specifically:
after the CPU processor enters a working state, a first charging current control signal CHG_900mA and a second charging current control signal CHG_600mA are pulled down, at the moment, a first triode Q1 and a second triode Q2 of a battery charging control circuit are not conducted, and a first chip U1 processes and uses the lowest-grade current such as 300mA, namely, the first current charges a battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, and if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pre-warns that the charging voltage is too low to charge normally; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA to enable the second triode Q2 to be conducted, pulls down the first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conducted, and the first chip U1 processes and uses a middle-grade current such as 600mA, namely the second current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls down a second charging current control signal CHG_600mA signal to enable the second triode Q2 to be non-conductive, pulls down a first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conductive, and the first chip U1 keeps the lowest-grade current of 300mA, namely the first current charges a battery; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA signal to enable the second triode Q2 to be conducted, pulls up the first charging current control signal CHG_900mA to enable the first triode Q1 to be conducted, and the first chip U1 processes and uses high-grade current such as 900mA, namely third current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls up a second charging current control signal CHG_600mA signal to enable a second triode Q2 to be conducted, pulls down a first charging current control signal CHG_900mA to enable a first triode Q1 to be non-conducted, and the first chip U1 processes a middle-grade current of 600mA, namely the second current is used for charging a battery; if the ADC detection signal vusb_adc is higher than 4.8v, the cpu processor keeps pulling the second charging current control signal chg_600ma high, so that the second transistor Q2 is turned on, keeps pulling the first charging current control signal chg_900ma high, so that the first transistor Q1 is turned on, and the first chip U1 processes a high-level current, such as 900mA, to charge the battery.
Fig. 6 shows a flowchart of a power supply control method according to an embodiment of the present disclosure, which is applicable to the power supply control circuit, as shown in fig. 6, and includes the steps of:
after the CPU processor enters a working state, a first charging current control signal CHG_900mA and a second charging current control signal CHG_600mA are pulled down, at the moment, a first triode Q1 and a second triode Q2 of a battery charging control circuit are not conducted, and a first chip U1 processes and uses the lowest-grade current such as 300mA, namely, the first current charges a battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, and if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pre-warns that the charging voltage is too low to charge normally; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA to enable the second triode Q2 to be conducted, pulls down the first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conducted, and the first chip U1 processes and uses a middle-grade current such as 600mA, namely the second current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls down a second charging current control signal CHG_600mA signal to enable the second triode Q2 to be non-conductive, pulls down a first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conductive, and the first chip U1 keeps the lowest-grade current of 300mA, namely the first current charges a battery; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA signal to enable the second triode Q2 to be conducted, pulls up the first charging current control signal CHG_900mA to enable the first triode Q1 to be conducted, and the first chip U1 processes and uses high-grade current such as 900mA, namely third current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls up a second charging current control signal CHG_600mA signal to enable a second triode Q2 to be conducted, pulls down a first charging current control signal CHG_900mA to enable a first triode Q1 to be non-conducted, and the first chip U1 processes a middle-grade current of 600mA, namely the second current is used for charging a battery; if the ADC detection signal vusb_adc is higher than 4.8v, the cpu processor keeps pulling the second charging current control signal chg_600ma high, so that the second transistor Q2 is turned on, keeps pulling the first charging current control signal chg_900ma high, so that the first transistor Q1 is turned on, and the first chip U1 processes a high-level current, such as 900mA, to charge the battery.
In the prior art, the battery of the electronic device such as the terminal is charged by a fixed current, wherein a 5V voltage charger is used for many electronic devices, so as to be compatible with various charging modes such as charger, computer USB port charging, etc. However, the 5V voltage chargers on the market have a lot of specifications and different carrying capacities, if the electronic equipment is designed to be charged only by adopting a fixed current, the situation that many chargers can not normally charge the electronic equipment can occur, and usually, the electronic equipment can not be prompted at this time, so that a user does not know the individual reason, the use experience of the user is greatly affected, and therefore, a power supply control scheme capable of realizing the charging current switching of the electronic equipment and guaranteeing the charging stability of the electronic equipment needs to be designed.
In view of the above, in this embodiment, a power supply control method is proposed that allows an electronic device to automatically adjust a charging current according to different charger carrying capacities by modifying a general-purpose circuit. The technical scheme is simple to realize and convenient to operate, can effectively ensure the charging stability of the electronic equipment, and can greatly promote the use experience of a user.
In the above embodiment, the second charge current control signal chg_600ma and the first charge current control signal chg_900mA are controlled by real-time detection of the ADC detection signal vusb_adc, so that different charge current magnitudes are switched so that the battery is in an optimal stable state of charge.
In one embodiment of the present invention, the method may further comprise the steps of:
displaying charging information, wherein the charging information comprises one or more of the following information: charge early warning, charge current magnitude, etc.
In this embodiment, by displaying the charging information, the user can know the current battery charging state in real time, so that the use experience of the user can be further improved.
The present disclosure also discloses an electronic device, fig. 7 shows a block diagram of the electronic device according to an embodiment of the present disclosure, and as shown in fig. 7, the electronic device 700 includes a memory 701 and a processor 702; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory 701 is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor 702 to implement the above-described method steps.
Fig. 8 is a schematic diagram of a computer system suitable for use in implementing a power control method according to an embodiment of the present disclosure.
As shown in fig. 8, the computer system 800 includes a processing unit 801 that can execute various processes in the above-described embodiments according to a program stored in a Read Only Memory (ROM) 802 or a program loaded from a storage section 808 into a Random Access Memory (RAM) 803. In the RAM803, various programs and data required for the operation of the computer system 800 are also stored. The processing unit 801, the ROM802, and the RAM803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.
The following components are connected to the I/O interface 805: an input portion 806 including a keyboard, mouse, etc.; an output portion 807 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and a speaker; a storage section 808 including a hard disk or the like; and a communication section 809 including a network interface card such as a LAN card, a modem, or the like. The communication section 809 performs communication processing via a network such as the internet. The drive 810 is also connected to the I/O interface 805 as needed. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 810 as needed so that a computer program read out therefrom is mounted into the storage section 808 as needed. The processing unit 801 may be implemented as a processing unit such as CPU, GPU, TPU, FPGA, NPU.
In particular, according to embodiments of the present disclosure, the methods described above may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program tangibly embodied on a medium readable thereby, the computer program comprising program code for performing the method. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section 809, and/or installed from the removable media 811.
The disclosed embodiments also disclose a computer program product comprising a computer program/instructions which, when executed by a processor, implement any of the method steps described above.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units or modules described in the embodiments of the present disclosure may be implemented by software, or may be implemented by hardware. The units or modules described may also be provided in a processor, the names of which in some cases do not constitute a limitation of the unit or module itself.
As another aspect, the embodiments of the present disclosure also provide a computer-readable storage medium, which may be a computer-readable storage medium included in the apparatus described in the above-described embodiment; or may be a computer-readable storage medium, alone, that is not assembled into a device. The computer-readable storage medium stores one or more programs for use by one or more processors in performing the methods described in the embodiments of the present disclosure.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by those skilled in the art that the scope of the invention in the embodiments of the present disclosure is not limited to the specific combination of the above technical features, but encompasses other technical features formed by any combination of the above technical features or their equivalents without departing from the inventive concept. Such as the technical solution formed by mutually replacing the above-mentioned features and the technical features with similar functions (but not limited to) disclosed in the embodiments of the present disclosure.

Claims (10)

1. A power supply control circuit, comprising: the battery charging control circuit, the 3.3V power supply circuit and the ADC sampling circuit are connected with the CPU, and the 3.3V power input circuit is connected with the battery charging control circuit and the battery, wherein:
the CPU processor is used for processing the voltage change detected by the ADC sampling circuit and sending a corresponding charging current switching control signal to the battery charging control circuit;
the battery charging control circuit is used for controlling the charging operation of the battery and the switching of different charging current according to the control of the CPU;
the 3.3V power supply circuit is used for providing electric energy for the CPU processor after the external charger power supply VUSB is inserted, so that the normal operation of the CPU processor is ensured;
the ADC sampling circuit is used for detecting the voltage change of the inserted external charger power supply VUSB and feeding back to the CPU processor;
the 3.3V power input circuit is used for charging the battery according to the current output by the battery charging control circuit.
2. The circuit of claim 1, the 3.3V power input circuit comprising: the first diode D1, the first resistor R11, the second resistor R12 and the MOS transistor Q4, wherein:
the anode of the first diode D1 is connected with an external charger power supply VUSB, and the cathode of the first diode D1 is connected with the source electrode of the MOS tube Q4 and the 4.2-volt voltage end V4.2;
the drain electrode of the MOS tube Q4 is connected with an external battery VBAT, and the grid electrode is connected with one end of a first resistor R11 and one end of a second resistor R12;
the other end of the first resistor R11 is connected with an external charger power supply VUSB;
the other end of the second resistor R12 is grounded.
3. The circuit of claim 1, the 3.3V power supply circuit comprising: the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C70, the third resistor R13, the fourth resistor R14, the fifth resistor R15 and the second chip U2, wherein:
one end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is connected with the 4.2 volt voltage end V4.2 and the input end Vin of the second chip U2;
one end of the third resistor R13 is connected with an external charger power supply VUSB, and the other end of the third resistor R is connected with an enabling pin CE of the second chip U2;
one end of the fourth resistor R14 is connected with a 3.3V control enabling signal VDD330UT of the CPU processor, and the other end of the fourth resistor R14 is connected with an enabling pin CE of the second chip U2, one end of the fifth resistor R15 and one end of the fourth capacitor C70;
the other ends of the fifth resistor R15 and the fourth capacitor C70 are grounded;
one end of the second capacitor C2 and one end of the third capacitor C3 are connected to the output terminal Vout of the second chip U2 and the 3.3 volt voltage terminal V3.3, and the other end is grounded.
4. The circuit of claim 1, the battery charge control circuit comprising: sixth resistor R1, seventh resistor R2, eighth resistor R3, ninth resistor R4, tenth resistor R5, eleventh resistor R6, twelfth resistor R18, thirteenth resistor R19, fifth capacitor C63, first chip U1, first triode Q1, second triode Q2, wherein:
one end of the sixth resistor R1 is connected with the current control pin PROG of the first chip U1, and the other end of the sixth resistor R1 is grounded;
one end of the seventh resistor R2 is connected with the current control pin PROG of the first chip U1, and the other end of the seventh resistor R2 is connected with the collector electrode of the second triode Q2;
one end of the eighth resistor R3 is connected with the current control pin PROG of the first chip U1, and the other end of the eighth resistor R3 is connected with the collector electrode of the first triode Q1;
one end of the ninth resistor R4 is connected with a first charging current control signal CHG_900mA output by the CPU processor, and the other end of the ninth resistor R4 is connected with the base electrode of the first triode Q1 and one end of the twelfth resistor R18;
the emitter of the first triode Q1 is grounded;
one end of the tenth resistor R5 is connected with a second charging current control signal CHG_600mA output by the CPU processor, and the other end of the tenth resistor R5 is connected with the base electrode of the second triode Q2 and one end of the thirteenth resistor R19;
the emitter of the second triode Q2 is grounded;
one end of the eleventh resistor R6 is connected with an external charger power supply VUSB, and the other end of the eleventh resistor R6 is connected with an enabling pin CE of the first chip U1;
the other end of the twelfth resistor R18 is grounded;
the other end of the thirteenth resistor R19 is grounded;
one end of the fifth capacitor C63 is connected to the external charger power VUSB and the power input pin VCC of the first chip U1, and the other end is grounded;
the battery pin of the first chip U1 is connected to the external battery terminal VBAT.
5. The circuit of claim 1, the ADC sampling circuit comprising: a fourteenth resistor R16 and a fifteenth resistor R17, wherein:
one end of the fourteenth resistor R16 is connected with an external charger power supply VUSB, and the other end of the fourteenth resistor R17 is connected with one end of the fifteenth resistor R17 and an ADC detection signal VUSB_ADC output by the CPU processor;
one end of the fifteenth resistor R17 is connected with one end of the fourteenth resistor R16, and the other end of the ADC detection signal VUSB_ADC is grounded, wherein the ADC detection signal VUSB_ADC is output by the CPU processor.
6. The circuit of claim 1, the CPU processor outputting an ADC detection signal vusb_adc, a 3.3V control enable signal VDD33OUT, a first charge current control signal chg_900mA, and a second charge current control signal chg_600mA, wherein:
the ADC detection signal VUBS_ADC is connected with a fourteenth resistor R16 and a fifteenth resistor R17 of the ADC sampling circuit;
the 3.3V control enabling signal VDD330UT is connected to a fourth resistor R14 of the 3.3V power supply circuit;
the first charging current control signal CHG_900mA is connected with a ninth resistor R4 of the battery charging control circuit;
the second charging current control signal chg_600ma is connected to a tenth resistor R5 of the battery charging control circuit.
7. The circuit of any one of claims 1-6, wherein,
after the CPU processor enters a working state, a first charging current control signal CHG_900mA and a second charging current control signal CHG_600mA are pulled down, at the moment, a first triode Q1 and a second triode Q2 of a battery charging control circuit are not conducted, and a first chip U1 processes and uses a first current to charge a battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, and if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pre-warns that the charging voltage is too low to charge normally; if the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA to enable the second triode Q2 to be conducted, pulls down the first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conducted, and the first chip U1 processes to charge the battery by using the second current;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls down a second charging current control signal CHG_600mA signal to enable the second triode Q2 to be non-conductive, pulls down a first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conductive, and the first chip U1 keeps the first current to charge the battery; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA so as to enable the second triode Q2 to be conducted, pulls up the first charging current control signal CHG_900mA so as to enable the first triode Q1 to be conducted, and the first chip U1 processes and uses the third current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls up a second charging current control signal CHG_600mA signal to enable a second triode Q2 to be conducted, pulls down a first charging current control signal CHG_900mA to enable a first triode Q1 to be non-conducted, and the first chip U1 processes to charge a battery by using a second current; if the ADC detection signal vusb_adc is higher than 4.8v, the cpu processor keeps pulling up the second charging current control signal chg_600ma signal, so that the second transistor Q2 is turned on, keeps pulling up the first charging current control signal chg_900mA, so that the first transistor Q1 is turned on, and the first chip U1 processes to charge the battery with the third current.
8. A power supply control method comprising:
after the CPU processor enters a working state, a first charging current control signal CHG_900mA and a second charging current control signal CHG_600mA are pulled down, at the moment, a first triode Q1 and a second triode Q2 of a battery charging control circuit are not conducted, and a first chip U1 processes and uses a first current to charge a battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, and if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pre-warns that the charging voltage is too low to charge normally; if the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA to enable the second triode Q2 to be conducted, pulls down the first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conducted, and the first chip U1 processes to charge the battery by using the second current;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls down a second charging current control signal CHG_600mA signal to enable the second triode Q2 to be non-conductive, pulls down a first charging current control signal CHG_900mA to enable the first triode Q1 to be non-conductive, and the first chip U1 keeps the first current to charge the battery; if the value of the ADC detection signal VUSB_ADC is higher than 4.8V, the CPU processor pulls up the second charging current control signal CHG_600mA so as to enable the second triode Q2 to be conducted, pulls up the first charging current control signal CHG_900mA so as to enable the first triode Q1 to be conducted, and the first chip U1 processes and uses the third current to charge the battery;
the ADC sampling circuit detects an ADC detection signal VUSB_ADC, if the value of the ADC detection signal VUSB_ADC is lower than 4.5V, the CPU processor pulls up a second charging current control signal CHG_600mA signal to enable a second triode Q2 to be conducted, pulls down a first charging current control signal CHG_900mA to enable a first triode Q1 to be non-conducted, and the first chip U1 processes to charge a battery by using a second current; if the ADC detection signal vusb_adc is higher than 4.8v, the cpu processor keeps pulling up the second charging current control signal chg_600ma signal, so that the second transistor Q2 is turned on, keeps pulling up the first charging current control signal chg_900mA, so that the first transistor Q1 is turned on, and the first chip U1 processes to charge the battery with the third current.
9. The method of claim 8, wherein the first current is less than the second current and the second current is less than the third current.
10. The method of claim 8 or 9, further comprising:
displaying charging information, wherein the charging information comprises one or more of the following information: charging early warning and charging current magnitude.
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