CN116053149A

CN116053149A - Electronic packaging method and electronic packaging structure

Info

Publication number: CN116053149A
Application number: CN202211636698.7A
Authority: CN
Inventors: 杜树安; 钱晓峰; 孟凡晓; 逯永广; 杨晓君
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2022-12-19
Filing date: 2022-12-19
Publication date: 2023-05-02

Abstract

The embodiment of the invention discloses an electronic packaging method and an electronic packaging structure, wherein the method comprises the following steps: providing a packaging substrate; forming at least a first alignment mark on the packaging substrate corresponding to the periphery of a first etching area where the cavity is located; taking the first alignment mark as an etching position reference, and performing optical etching on the first etching region; embedding a re-wiring layer substrate into the cavity after etching the cavity, and exposing the top of the re-wiring layer substrate; and connecting one part of the die unit to the rerouting layer substrate and connecting the other part of the die unit to the packaging substrate, wherein the die unit is positioned above the rerouting layer substrate and the packaging substrate. The invention is convenient for realizing optical position alignment, thereby improving the processing precision of the semiconductor package to a certain extent.

Description

Electronic packaging method and electronic packaging structure

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to an electronic packaging method and an electronic packaging structure.

Background

During the semiconductor package processing, some critical process steps, such as photolithography, BGA soldering, etc., are not separated from the optical alignment. Taking a photolithography process as an example, before photolithography starts, alignment correction needs to be performed on the relative positions between a pattern area on a mask plate and a substrate below for re-etching patterns, and the alignment precision of the two positions is related to whether the patterns on the mask plate can be accurately transferred and re-etched to the substrate below, so that the processing precision of semiconductor packaging is affected.

Disclosure of Invention

In view of this, one or more embodiments of the present invention provide an electronic packaging method and an electronic packaging structure, which facilitate optical alignment, so that the processing accuracy of semiconductor packages can be improved to some extent.

In a first aspect, an embodiment of the present invention provides an electronic packaging method, including:

providing a packaging substrate for forming at least one cavity on at least one surface thereof;

forming at least a first alignment mark on the packaging substrate corresponding to the periphery of a first etching area where the cavity is located;

taking the first alignment mark as an etching position reference, and performing optical etching on the first etching region;

embedding a re-wiring layer substrate into the cavity after etching the cavity, and exposing the top of the re-wiring layer substrate; and connecting one part of the die unit to the rerouting layer substrate and connecting the other part of the die unit to the packaging substrate, wherein the die unit is positioned above the rerouting layer substrate and the packaging substrate.

Optionally, the optically etching the first etching region includes: and etching at least one cavity in a first etching area on the packaging substrate through laser etching or exposure and development, wherein the bottom surface of at least one cavity is exposed.

Optionally, the cavity is a rectangular or square cavity, and the first alignment marks at least comprise two first alignment marks, and the two first alignment marks are diagonally arranged.

Optionally, the method further comprises: forming a second alignment mark on the packaging substrate corresponding to the periphery of the first etching area where the cavity is located; the embedding of the rewiring layer substrate in the cavity comprises: and in the process of embedding the rewiring layer substrate into the cavity, taking the second alignment mark as a mounting position reference, and calibrating and positioning the mounting position of the rewiring layer substrate in the cavity.

Optionally, the second alignment marks at least comprise two second alignment marks, and the two second alignment marks are diagonally arranged; the calibrating and positioning the mounting position of the rewiring layer substrate in the cavity comprises the following steps: positioning the midpoint of a connecting line between the two second positioning marks based on at least two second alignment marks; adjusting a center point of the rewiring layer substrate to be aligned with the center point, and aligning an edge of the rewiring layer substrate with an edge of the cavity; after the positioning is completed, the method further comprises: and placing the rewiring layer substrate into the cavity and on the exposed bottom surface of the cavity.

Optionally, the method further comprises: forming a third alignment mark on the packaging substrate and at the edge of the ball implantation area; the ball implantation area is positioned at the periphery of the first etching area and used for forming bonding conductive points thereon, the third alignment marks at least comprise two, and at least two third alignment marks are diagonally arranged at the inner side of the edge of the ball implantation area;

after forming the redistribution layer substrate in the cavity, the method further comprises: calibrating circuit patterns on a mask plate to align with ball-planting areas on the packaging substrate and the rewiring layer substrate according to at least two third positioning marks; forming a first bonding conductive point in a ball-implanting area on the packaging substrate based on the mask plate, and forming a second bonding conductive point in the ball-implanting area on the rewiring layer substrate; the first bonding conductive points and the second bonding conductive points are respectively used for bonding and interconnection with the bonding surfaces of the grain units.

Optionally, the method further comprises: forming a fourth alignment mark on the packaging substrate and positioned outside the ball implantation area; the fourth alignment marks at least comprise two, at least two are diagonally arranged at the outer side of the ball planting area, wherein connecting lines of the at least two fourth alignment marks and connecting lines of the at least two third alignment marks are arranged in a crossing manner;

The connecting a portion of the die unit to the rewiring layer substrate and another portion of the die unit to the package substrate includes: forming first bonding conductive points in ball-planting areas on the packaging substrate, and identifying the fourth alignment marks after forming second bonding conductive points in ball-planting areas on the rewiring layer substrate;

aligning the bonding surfaces of the die units to first bonding conductive points on the lower packaging substrate and second bonding conductive points on the rewiring layer substrate respectively based on the fourth alignment marks;

a portion of the die unit is attached to the package substrate through the first bonding conductive point and another portion of the die unit is attached to the rerouting layer substrate through the second bonding conductive point.

Optionally, the die unit at least includes: a first crystal grain and a second crystal grain, wherein positioning mark points for attachment positioning are respectively arranged on the first crystal grain and the second crystal grain;

the aligning the bonding surface of the die unit to the first bonding conductive point on the underlying package substrate and the second bonding conductive point on the rewiring layer substrate based on the fourth alignment mark, respectively, includes:

Determining an initial position of the first die relative to the package substrate and the rewiring layer substrate below based on the positions of the positioning mark points and the at least two fourth alignment marks on the first die;

according to the initial position, adjusting the joint surface of the first crystal grain to be aligned with a first joint conductive point of a first side area of the lower packaging substrate and to be aligned with a second joint conductive point of the first side area of the lower rewiring layer substrate;

and adjusting the bonding surface of the second die to be aligned with the first bonding conductive point of the second side region of the underlying package substrate and to be aligned with the second bonding conductive point of the second side region of the underlying rewiring layer substrate; the first crystal grains and the second crystal grains are arranged side by side at intervals, and the first side area and the second side area are symmetrical relative to the symmetry axis of the rewiring layer substrate. .

Optionally, the first alignment mark is a geometric feature pattern, and the first alignment mark is a groove formed on at least one surface of the package substrate.

Optionally, the redistribution layer substrate is mainly composed of dielectric layers and metal layers stacked alternately, wherein the metal layers are mutually coupled, and the dielectric layers are made of insulating materials.

In a second aspect, an embodiment of the present invention further provides an electronic package structure, including: a package substrate, wherein at least one surface of the package substrate is provided with at least one cavity, and the bottom surface of at least one cavity is exposed;

a first alignment mark formed on at least one of the surfaces of the package substrate and located at the periphery of the cavity;

a rewiring layer substrate; the rewiring layer substrate is embedded in the cavity and is positioned on the bottom surface of the cavity;

a die unit; one part of the die unit is connected to the rewiring layer substrate, and the other part of the die unit is connected to the packaging substrate.

Optionally, the first alignment mark includes: a closed geometry, and intersecting lines within the closed geometry.

Optionally, the first alignment mark is a groove formed on at least one surface of the package substrate.

Optionally, the electronic package structure is a chip.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of an electronic packaging method according to an embodiment of the present application;

FIG. 2 is a top view of an embodiment of a package substrate with alignment marks formed in one process of the present application;

FIG. 3 is a schematic structural diagram of an embodiment of a package substrate with a cavity formed in one process of the present application;

FIG. 4 is a schematic structural diagram of an embodiment of a package substrate formed in a further process of the present application;

FIG. 5 is a schematic structural diagram of an embodiment of a package substrate formed in a further process of the present application;

fig. 6 is a schematic diagram of an interconnection structure between a die unit and a package substrate formed in another process of the present application.

Fig. 7 is a schematic structural diagram of a plurality of examples of each alignment mark in the present application.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In order to help understand the technical scheme and the technical effect of the embodiment of the invention, before the technical scheme of the embodiment of the invention is developed in detail, some proper nouns involved in the invention are briefly explained, more terms are introduced in the description, and the detailed description of the terms is as follows:

Die: individual die, which are cut from a semiconductor wafer (e.g., a silicon wafer) by a dicing process prior to packaging, contain the complete design, generally referred to in chinese as "die" or "die", collectively referred to herein as "die".

μBump: refers to micro-interconnect bumps for high density interconnects.

control l ed-co l l apse chip connect ion Bump: the controllable collapse chip is connected with the Bump, which is called as C4 Bump for short in the invention;

aj i nomoto Bu i l d-up Fi lm substrate: the taste element laminated film resin carrier is simply called as ABF substrate in the present invention.

MCM: a module in which Mu lt i-chi p Modu l e is encapsulated by a plurality of dies is called a "multichip module" in the invention.

Semiconductor package devices, typically high performance high power chips, for interconnection between high density dies (also referred to as wafers or dies) in a Fan out (Fan out) packaging process, to improve the performance of the semiconductor package devices, for example, heat dissipation, signal immunity, power consumption, etc., RDL (ReDi str ibut I on Layer ) is introduced, and Die line contact locations (I/O pads) are changed by wafer level metal wiring and bumps (bumps), so that the dies can be adapted to different package forms.

After introduction of RDL, layout compactness and thinning design of semiconductor package device structures are also one of the issues to be considered. Thus, in some embodiments, it is contemplated that the RDL layer is embedded in a cavity formed on the package substrate, however, the etch accuracy of the cavity, the positional accuracy of the RDL embedded within the cavity, etc., are critical to overall semiconductor package structure performance.

FIG. 1 is a flow chart of an electronic packaging method according to an embodiment of the present application; as shown in fig. 1, the electronic packaging method provided in the embodiment of the present application is intended to facilitate optical position alignment in some key process steps (procedures), for example, a cavity etching process step, a redistribution layer substrate mounting process step, etc., so that the processing precision of semiconductor packaging can be improved to a certain extent, and thus, a semiconductor packaging structure meeting the design requirements is packaged and processed.

FIG. 2 is a top view of one embodiment of the package substrate of FIG. 1; referring to fig. 1 and 2, in some embodiments, an electronic packaging method S100 provided in the embodiments of the present application may include:

s110, providing a package substrate 100 for forming at least one cavity 110 on at least one surface thereof.

The package Substrate 100Substrate, referred to as SUB) can provide the functions of electrical connection, protection, support, heat dissipation, assembly, etc. for the chip as required, so as to achieve the purposes of multi-pin, reduced package product volume, improved electrical performance and heat dissipation, ultra-high density, or multi-chip modularization. The package substrate 100 may be made of an organic material or an inorganic material, depending on the materials used. In some embodiments, the package substrate 100 is a hard package substrate 100, and may be a substrate made of BT material, ABF material, or ms material. The package substrate 100 is preferably a resin substrate, i.e., ABF substrate (Aj i nomoto Bu i l d-up Fi lm substrate), and can be made thinner at I C (I ntegrate c i rcu it), with more pins and higher transmission rate.

The package substrate 100 may be, for example, a paper-based copper foil layer composite, a composite copper foil layer composite, or a glass fiber-based copper foil layer composite such as polymer impregnation. Referring to fig. 3, the package substrate 100 may include an interconnect structure, such as a plurality of conductive traces or Through Silicon Vias (TSVs), which enable inter-layer interconnection); the package substrate 100 may be a base semiconductor substrate including a structure such as silicon or germanium, or may be a compound semiconductor substrate including a structure such as silicon or germanium.

The types of the above-mentioned substrates may be classified into flexible thin film substrates, hard substrates, and the like according to the materials of the package substrate 100, and the specific type of the substrate selected as the package substrate 100 may be considered according to environmental factors such as temperature, operating frequency, and the like of the semiconductor package device application, in combination with the dimensional stability, high frequency characteristics, heat resistance, thermal conductivity, and the like of the substrates of different materials.

Referring to fig. 3, in some embodiments, the cavity 110 is formed on the upper surface of the package substrate 100, exposing a portion of the internal structure of the package substrate 100.

S120, forming at least a first alignment mark 111 on the package substrate 100 corresponding to the periphery of the first etching region 110S where the cavity 110 is located.

Referring to fig. 2, a plurality of different alignment marks (also referred to as optical positioning points, commonly referred to as Mark points) are formed on the package substrate 100, and are used as alignment reference in the process steps requiring alignment; the alignment marks may be formed by transferring and copying the patterns of the alignment marks designed on the mask plate to the package substrate 100 through one mask etching process in the process of forming the pattern structures such as the interconnection lines on the package substrate 100. In some embodiments, the alignment marks may be bare copper or tin plated on the surface to form patterns easily distinguishable from other peripheral structures, so that the alignment marks can be accurately identified by the photoetching machine before photoetching for position calibration.

In some embodiments, the top of the alignment marks are substantially in a coplanar plane with the metal structures on the upper surface of the package substrate 100, and the alignment marks may be formed by exposing, developing, and etching the patterns on a mask in the same forming process.

Referring to fig. 2 and 3, a first etched region 110s is used to form the cavity 110; the first alignment mark 111 is a geometric feature pattern with a symmetrical structure, the outline size is about 60-120 μm, the line width is about 15 μm, the z-direction height is about 0.6 μm, the edge gradient is about 60 degrees, and the same or similar repeated marks are not arranged on the package substrate 100 and in 1mm near the first alignment mark 111, so that the photolithography machine can accurately identify the alignment mark, and the precision of the photolithography process is ensured.

Of course, in order to ensure positioning accuracy of other steps in the packaging process, in some embodiments, other alignment marks are further provided on the packaging substrate 100, and the alignment marks used in different steps are preferably different patterns, so that the machine used in different steps can be accurately distinguished and identified, and the other alignment marks are described in the following embodiments one by one.

And S130, taking the first alignment mark 111 as an etching position reference, and performing optical etching on the first etching region 110S.

Before etching for forming the cavity 110 is performed, the first alignment mark 111 on the surface of the package substrate 100 is detected using an image detection device, such as a camera or a laser detector, mounted on a photolithography tool.

It will be appreciated that where two layers, elements or structures, etc. are generally required to be joined relative to one another, side-to-side, etc., or where dummy structures (e.g., holes, trenches, cavities, etc.) are formed in designated areas, the degree of alignment (also referred to as overlap) of the relative joint may be ensured based on alignment marks such as first alignment mark 111, etc.

S140, after etching the cavity 110, embedding the re-wiring layer substrate 120 into the cavity 110, and exposing the top of the re-wiring layer substrate 120.

Referring to fig. 4, after the cavity 110 is etched in step S140, the redistribution layer substrate 120 is formed in the cavity 110. The process of forming the redistribution layer substrate 120 may be to manufacture the redistribution layer substrate 120 in advance, and then, after the cavity 110 is formed, use an automated machine to absorb and place the redistribution layer substrate 120 into the cavity 110. Since the redistribution layer substrate 120 is preformed, the manufacturing quality thereof can be ensured.

Of course, the redistribution layer substrate 120 may be formed by growing a dielectric layer in the cavity 110 after the cavity 110 is formed, and depositing a metal layer, thereby forming a structure in which the metal layer and the dielectric layer are alternately stacked.

And S150, connecting one part of the die unit to the rewiring layer substrate 120, and connecting the other part of the die unit to the packaging substrate 100, wherein the die unit is positioned above the rewiring layer substrate 120 and the packaging substrate 100.

After S150, the method further includes: and coating and packaging the die unit by using a molded shell to form a protective layer of the die unit. Wherein the molded housing may be a molded plastic housing, or may be a glass housing, epoxy, or other molded compound article.

After the redistribution layer substrate 120 is embedded in the cavity 110, die unit metal bonding surfaces are interconnected with a Bump attachment on the package substrate 100 and the redistribution layer substrate 120.

To facilitate alignment of the die unit with the underlying package substrate 100 and the rewiring layer substrate 120 in this process, an alignment mark for this process may be formed in advance on a predetermined area of the package substrate 100 in order to improve the mounting positioning accuracy of the die unit.

According to the electronic packaging method provided by the embodiment of the application, the first alignment mark 111 for calibrating the etching position is formed on the packaging substrate 100 in advance, and in the etching process, the optical position alignment is conveniently realized by means of the first alignment mark 111, so that the processing position precision of the cavity 110 is favorably ensured, and the processing precision of the semiconductor package can be improved to a certain extent.

In some embodiments, in step S130, the optically etching the first etched region 110S includes: at least one cavity 110 is etched in the first etching region 110s on the package substrate 100 by laser etching or exposure and development, and a bottom surface of at least one cavity 110 is exposed.

Wherein, exposure, development and etching are three processes, in order to realize the etching process, a mask is generally manufactured according to a layout, and when a predetermined area on the package substrate 100 needs to be etched after the mask is manufactured, a layer of silicon nitride dielectric film is deposited on the surface of the package substrate 100; uniformly coating polyimide on the silicon nitride dielectric film and curing to form a polyimide sacrificial layer; depositing a layer of silicon nitride medium on the polyimide sacrificial layer to form a hard mask; uniformly coating photoresist on the hard mask, exposing, developing and baking the photoresist by means of the mask plate to form a preset pattern on the mask plate; the predetermined pattern includes a first etched region 110s forming the cavity 110. After forming the predetermined pattern, the etching head of the etching machine is moved to the first etching area 110s by using the first alignment mark 111 as a reference position point, and the cavity 110 is etched in the first etching area 110s according to a predetermined trend.

With continued reference to fig. 2 and 3, in some embodiments, the cavity 110 is a rectangular or square cavity 110, and the first alignment marks 111 include at least two first alignment marks 111 disposed diagonally. In this way, by the two first alignment marks 111 being diagonally arranged, accurate positioning is facilitated.

Fig. 7 illustrates a pattern of alignment marks, and referring to fig. 6, the first alignment mark 111 includes: closed geometry, such as circle, torus, quadrilateral, pentagon, etc. In some embodiments, intersecting lines, such as crisscross lines, L-shaped intersecting lines, T-shaped intersecting lines, etc., may also be provided in the closed geometry to form a composite pattern mark.

The person skilled in the art can select the corresponding pattern marks by himself as required, and in some embodiments, the alignment marks for different processes are preferably different pattern marks in order to accurately identify the alignment marks.

In some embodiments, in order to improve the accuracy of the mounting position of the redistribution layer substrate 120, when embedding the RDL substrate, a corresponding alignment mark may be formed on the package substrate 100 in advance, or the first alignment mark 111 may be used for mounting positioning. Of course, for ease of recognition and avoiding confusion, referring to fig. 2 again, the corresponding second alignment marks 112 may be specially configured, or the second alignment marks 112 may be diagonally configured and distributed around the periphery of the first etching region 110s at an angle with respect to the first alignment marks 111.

Thus, in some embodiments, the method further comprises: forming a second alignment mark 112 on the package substrate 100 corresponding to the periphery of the first etching region 110s where the cavity 110 is located; the second alignment mark 112 and the first alignment mark 111 are formed by the same process, and can be formed at one time by the same layout during the formation of the metal structure on the package substrate 100, which will not be described in detail herein, and reference may be made to the description of the first alignment mark 111.

The embedding of the redistribution layer substrate 120 in the cavity 110 includes: in the process of embedding the rerouting layer substrate 120 into the cavity 110, the second alignment mark 112 is used as a reference for the mounting position, and the mounting position of the rerouting layer substrate 120 in the cavity 110 is aligned and positioned. Thus, by providing the second alignment mark 112, it is convenient to secure the positional alignment accuracy during the mounting of the rewiring layer substrate 120 by means of the second alignment mark 112, thereby improving the processing accuracy of the semiconductor package structure.

The second alignment marks 112 include at least two second alignment marks 112 disposed diagonally. In some embodiments, the second alignment mark 112 is patterned differently from the first alignment mark 111 to facilitate machine identification.

The calibrating and positioning the mounting position of the redistribution layer substrate 120 in the cavity 110 includes:

locating the midpoint of the connection line between the two second positioning marks based on at least two second alignment marks 112;

the center point of the rewiring layer substrate 120 is adjusted to align with the midpoint and the edge of the rewiring layer substrate 120 is aligned with the edge of the cavity 110. Thus, through the above steps, the positional accuracy of the rewiring layer substrate 120 in the cavity 110 can be ensured.

After the positioning is completed, the method further comprises: the redistribution layer substrate 120 is placed in the cavity 110 and is located on the exposed bottom surface of the cavity 110. Thus, the rerouting layer substrate 120 can be conveniently and accurately mounted into the cavity 110 with the aid of the second alignment mark 112, and the mounting accuracy thereof can be ensured.

In some embodiments, the redistribution layer substrate 120 is mainly composed of dielectric layers and metal layers that are alternately stacked, where the metal layers are coupled to each other, and the dielectric layers are insulating materials. The metal layer may be, for example, gold, silver, copper, nickel, titanium, aluminum, or an alloy thereof, and the dielectric layer may be a Polybenzoxazole (PBO) film, a polyimide (P I) film, a benzocyclobutene (BCB) film, or a combination thereof, or the like.

A portion of the metal layer of the redistribution layer substrate 120 is coupled to a through-layer via (TSV) of the package substrate 100.

In step S150, after the completion of the mounting of the rewiring layer substrate 120, an interconnection step of the die units is performed next.

Referring to fig. 5, before interconnection, bonding

conductive points

4 and 5 are required to be formed on the package substrate 100 and the redistribution layer substrate 120 at the area where the bonding surfaces of the die units are interconnected for key interconnection; the bonding conductive points may include: conductive bumps (Bump), conductive metal pillars, conductive balls (Ba l), etc. The bonding

conductive points

4 and 5 may be formed on pads (pads) on the surfaces of the package substrate 100 and the redistribution layer substrate 120, and passivation layers, which may be dielectric layers of silicon oxide, silicon nitride, or the like, are laid around the pads and expose the vertices of the pads.

With continued reference to fig. 2, in order to ensure accuracy of the mounting location of the die unit interface, in some embodiments, the method further comprises: forming a third alignment mark 113 on the package substrate 100 at the edge of the ball mounting region 140; the ball-implanting area 140 is located at the periphery of the first etching area 110s, and is used for forming bonding

conductive points

4 and 5 thereon, the third alignment marks 113 at least comprise two, and at least two of the third alignment marks 113 are diagonally arranged inside the edge of the ball-implanting area 140;

After forming the redistribution layer substrate 120 in the cavity 110, the method further comprises: calibrating circuit patterns on a mask plate to align with the ball-planting region M of the package substrate 100 and the ball-planting region N of the rewiring layer substrate 120 according to at least two third positioning marks;

forming first bonding conductive points 4 in the ball-implanting region M on the package substrate 100 and forming second bonding conductive points 5 in the ball-implanting region N on the rewiring layer substrate 120 based on the mask; the first bonding conductive points 4 and the second bonding conductive points 5 are respectively used for bonding and interconnection with the bonding surface of the die unit 150, as shown in fig. 6.

In this embodiment, the interconnection of the die units 150 is performed by a flip Chip (fci Chip) process. Wire Bond i ng (WB) interconnection, which is more widely used, may also be used.

The third alignment mark 113 is substantially the same as the first alignment mark 111, and will not be described again; the third alignment mark 113 is preferably different from the patterns of the first alignment mark 111 and the second alignment mark 112.

Specifically, the formation process of the bonding

conductive points

4 and 5 is: and (3) performing optical positioning based on the diagonal arrangement of at least two third alignment marks 113, and performing copper column electroplating and solder ball electroplating on the positions of the pad vertexes exposed by the passivation layers on the upper surfaces of the redistribution layer RDL FANOUT substrate and the ABF packaging substrate 100 after positioning. The pitch of copper pillars in the region of the ABF package substrate 100 is about 130 μm, and the diameter is about 70 μm; the copper pillars of the redistribution layer RLD Fanout substrate have a pitch of about 50 μm, a diameter of about 25 μm, and a uniform height.

After forming the bonding conductive points, solder mounting of the die unit is performed next. In this embodiment, the die units are connected by flip chip bonding. Likewise, to ensure the accuracy of the mounting position of the die unit after the process is completed, please refer again to fig. 2, in some embodiments, the method further includes: forming a fourth alignment mark 114 on the package substrate 100 outside the ball mounting region 140; the fourth alignment marks 114 at least comprise two, at least two of the fourth alignment marks 114 are diagonally arranged at the outer side of the ball planting area, wherein the connecting lines of the at least two fourth alignment marks 114 and the connecting lines of the at least two third alignment marks 113 are crossed;

the attaching a portion of the die unit to the redistribution layer substrate 120 and another portion of the die unit 150 to the package substrate 100 includes: forming first bonding conductive points 4 in ball-mounting regions on the package substrate 100, and identifying the fourth alignment mark 114 after forming second bonding conductive points 5 in ball-mounting regions on the rerouting layer substrate 120;

aligning the bonding surfaces of the die units to the first bonding conductive points 4 on the lower package substrate 100 and the second bonding conductive points 5 on the rewiring layer substrate 120, respectively, based on the fourth alignment marks 114; a portion of the die unit 150 is attached to the package substrate 100 through the first bonding conductive points 4, and another portion of the die unit 150 is attached to the rerouting layer substrate 120 through the second bonding conductive points 5. Thus, by providing the fourth alignment mark 114 for die unit mounting alignment, die unit mounting position accuracy is facilitated to be ensured.

With continued reference to fig. 6, in some embodiments, the die unit 150 includes at least: a first die 151 and a second die 152, wherein positioning mark points (not shown) for attachment positioning are respectively arranged on the first die 151 and the second die 152.

The aligning the bonding surfaces of the die units with the first bonding conductive points 4 on the lower package substrate 100 and the second bonding conductive points 5 on the rewiring layer substrate 120 based on the fourth alignment mark 114 includes:

determining an initial position of the first die 151 relative to the package substrate 100 and the rewiring layer substrate 120 thereunder based on the positions of the positioning mark points on the first die 151 and the at least two fourth alignment marks 114;

adjusting the bonding surface of the first die 151 to be aligned with the first bonding conductive point 4 of the first side region (left side in fig. 6) of the lower package substrate 100 and the second bonding conductive point 5 of the first side region of the lower rewiring layer substrate 120 according to the initial position;

and, adjusting the bonding surface of the second die 152 to align with the first bonding conductive point 4 of the second side region (right side in fig. 6) of the lower package substrate 100 and to align with the second bonding conductive point 5 of the second side region of the lower rewiring layer substrate 120; the first die 151 and the second die 152 are arranged side by side at intervals, and the first side region and the second side region are symmetrical about the symmetry axis of the redistribution layer substrate 120.

In this embodiment, when two different dies are adopted, a portion of the two dies are welded to the local high-density interconnection RDL substrate, and the two chips communicate with each other through the local high-density interconnection RDL substrate; part of the power supply is welded on the packaging substrate 100, and signals and power supplies needing to be led out are led out of the packaging substrate 100 so as to be interconnected with the outside, so that fan-out type packaging is realized.

Of course, in the embodiment of the present invention, a case of two dies is illustrated, and interconnection of two or more dies may be further provided based on the technical idea of the embodiment of the present invention.

In order to increase the effective area of the two crystal grains and improve the performance of the two crystal grains, active chip stacking can be carried out in a low-heat area of the two crystal grains through TSVs, so that the effective area and the performance of the chips are improved; whereas for its high thermal area d mu mmydie (virtual die) is stacked to facilitate thermal conduction.

Preferably, the patterns of the first alignment mark 111, the second alignment mark 112, the third alignment mark 113 and the fourth alignment mark are different from each other to facilitate machine discrimination. In the above embodiments, the alignment marks provided in pairs are described as an example, however, more alignment marks may be provided as needed or one alignment mark may be provided as needed, or a structure with obvious features on the package substrate 100 may be used instead of the special alignment marks, but the alignment marks may be required to be recognized by a machine and the alignment marks may be easily aligned.

In order to help understand the technical solutions provided in some embodiments of the present invention, taking a part of the process implemented by the semiconductor package structure as an example, the following details are described below:

s11, providing a package substrate 100, wherein in the process of forming the interconnection structure and the surface metal device on the package substrate 100, the surface of the package substrate 100 is formed into the optical alignment marks provided in different package processes through a mask, and please refer to FIG. 2, which includes: the first alignment mark 111, the second alignment mark 112, the third alignment mark 113 and the fourth alignment mark 114 are respectively provided with at least two alignment marks which are diagonally arranged.

More alignment marks can be arranged, but considering that the area of the package substrate 100 is precious, the arrangement of too many alignment marks occupies the effective area of too many substrates, so that the alignment marks are arranged as little as possible on the premise of meeting the alignment positioning requirement.

And S12, in the process of forming the cavity 110, the photoetching machine station detects and identifies the first alignment marks 111 through the imaging component, after the first alignment marks 111 are identified, optical etching positioning is performed based on the two first alignment marks 111 which are arranged diagonally and in a grid pattern shape as optical position references, and after positioning is completed, a high-precision cavity 202 is formed on at least one surface of the packaging substrate 100 through laser grooving, exposure and development etching.

It will be appreciated that the patterning template of each alignment mark on the package substrate 100 is pre-configured in the photolithography tool program for identifying the corresponding alignment mark provided on the package substrate 100.

S13, after the cavity 110 is formed in the first etching region 110S, a step of mounting the redistribution layer substrate 120 in the cavity 110 is started. The imaging module on the machine station recognizes the second alignment marks 112, uses the two diagonally arranged second alignment marks 112 as mounting position references, and after alignment is completed, adsorbs the redistribution layer substrate 120 by using a vacuum adsorption mechanism, calibrates the posture of the vacuum adsorption mechanism, places the redistribution layer substrate 120 in the cavity 110, and places the redistribution layer substrate on the bottom surface of the exposed cavity 110.

In order to secure the position of the rewiring layer substrate 120 within the cavity 110, after the cavity 110 is embedded, the bottom surface of the exposed cavity 110 and the bottom surface of the rewiring layer substrate 120 may be fixed together by double-sided adhesive bonding, and the side portion of the rewiring layer substrate 120 and the side inner wall of the cavity 110 may also be fixed together by double-sided adhesive bonding.

S14, after the redistribution layer substrate 120 is disposed in the cavity 110, bonding conductive bumps are formed in the ball-mounting areas on the package substrate 100 and the redistribution layer substrate 120, so as to implement attachment interconnection between the die unit and the package substrate 100 and the redistribution layer substrate 120. Specifically, before the copper pillar and the solder ball are electroplated in the process of forming the bonding conductive bump, first identifying a third alignment mark 113, optically positioning a ball-implanting area for forming the conductive bump based on the third alignment mark 113, determining the placement reference positions of a mask plate on the package substrate 100 and the rewiring layer substrate 120 according to the at least two third positioning marks, calibrating and aligning the positions of the mask plate, and then electroplating the copper pillar and the solder ball on the upper surfaces of the RDL FANOUT substrate and the ABF substrate based on the mask plate to form the conductive bump; specifically, the pitch of the copper pillars in the ball-mounting region of the ABF package substrate 100 may be set to about 130 μm, and the diameter may be set to about 70 μm; the RLD fanout substrate copper pillars have a pitch of about 50 μm, a diameter of about 25 μm, and a uniform height.

S15, after the formation of the bonding conductive bumps, activating a vacuum suction device to prepare for bonding at least one first die 151 and one second die 152 to the package substrate 100 and the redistribution layer substrate 120. Specifically, the fourth alignment mark 114 is used for performing optical positioning diagonally, and the first die 151 and the second die 152 are flip-chip soldered in the bonding conductive point region of the ABF substrate and the RDL substrate, so as to complete attachment interconnection. After the welding is finished, the communication between the two chips can be carried out through the RDL fanout substrate, so that the high-density grain interconnection is realized.

During the flip-chip interconnection of the at least two dies, the soldering position of the first die 151 on the first side region of the package substrate 100 and the redistribution layer substrate 120 may be further determined according to the at least two fourth alignment marks 114. For example, a center point of the at least two fourth alignment marks 114 may be determined according to the at least two fourth alignment marks 114; the positioning mark points on the first die 151 are aligned up and down with the center points of the at least two fourth alignment marks 114, and the soldering starts to be performed. Likewise, the bonding location of the second die 152 on the second side regions of the package substrate 100 and the rewiring layer substrate 120 may be determined.

It will be appreciated that since the first die and the second die 152 are mounted on one side region of the package substrate 100 and the re-wiring layer substrate 120, respectively, the center point of each die does not coincide with the center point of the main substrate, and further movement of the first die 151 may be required when the fourth alignment mark 114 is used as a positional reference. In order to facilitate positioning during movement, auxiliary alignment mark points may be found on the first die 151, for example, a first metal connection Bump (referred to as Bump 1) and a second metal connection Bump (referred to as Bump 2) on the bonding surface of the first die 151 (for example, two metal connection bumps located on diagonal vertices). At the same time, the corresponding bonding conductive bumps, bump3 and Bump4, may be determined at corresponding locations on the package substrate and the redistribution layer substrate (e.g., also at two locations on the diagonal vertices), and after alignment, bump3 and Bump1 need to be soldered together, and Bump4 and Bump2 need to be soldered together.

Then, the metal connection bumps on the first die 151 are in opposite directions to the bonding conductive bumps on the package substrate 100 and the redistribution layer substrate 120, that is, the metal bonding surface (the surface having the metal connection bumps) of the first die 151 is turned down by flip-flop adjustment, while the bonding conductive bumps on the package substrate 100 and the redistribution layer substrate 120 are turned up. And, the Bump1 is aligned with the Bump3 in the vertical direction, and the Bump2 is aligned with the Bump4 in the vertical direction, so that all the metal connection bumps on the first die 151 can be aligned with all the corresponding bonding conductive bumps of the package substrate 100 and the rewiring layer substrate 120, and the positional accuracy of the flip-chip bonding of the first die 151 and the second die 152 is ensured.

The shapes of the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark 114 are geometric feature figures, and are all different geometric feature figures. The first alignment marks have the same shape, the second alignment marks have the same shape, the third alignment marks have the same shape, and the fourth alignment marks 114 have the same shape.

In the embodiment of the present invention, the shapes of the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark 114 are different, the shapes of the first alignment marks are the same, the shapes of the second alignment marks are the same, the shapes of the third alignment marks are the same, and the shapes of the fourth alignment marks 114 are the same. Thus, the shapes of all the alignment marks used each time are the same, but the shapes of the alignment marks which are not used at the same time are different, so that when the image of the main substrate is identified, the alignment marks which are used at the same time can be distinguished according to the shapes of the alignment marks, and the probability of error occurrence is reduced.

According to the disclosure of the embodiment of the present application, in the semiconductor packaging method provided by the embodiment of the present invention, at least the cavity forming process is provided with the first alignment mark 111 on the packaging substrate 100, so that the alignment of the position before the cavity etching is formed is facilitated, and therefore, the optical position alignment precision in the cavity etching process can be improved, and the processing quality of the semiconductor packaging can be improved.

Further, different optical alignment marks are preset on the package substrate 100 in the processes of embedding the Fanout re-wiring layer substrate 120, preparing various bonding conductive points, reversely buckling and welding the multi-chip, so that the accuracy of optical alignment can be ensured, and the processing quality and performance of the semiconductor package can be improved.

Referring to fig. 2 and 6, a further embodiment of the present application provides an electronic package structure, including:

a package substrate 100 having at least one cavity 110 on at least one surface of the package substrate 100 and exposing a bottom surface of at least one cavity 110;

a first alignment mark 111 formed on at least one of the surfaces of the package substrate 100 and located at a periphery of the cavity 110 (a region indicated by 110s in fig. 2);

a rewiring layer substrate 120; the re-wiring layer substrate 120 is embedded in the cavity 110 and is located on the bottom surface of the cavity 110;

a die unit 150; one part of the die unit is connected to the redistribution layer substrate 120, and the other part of the die unit is connected to the package substrate 100.

In the electronic packaging structure provided in this embodiment, the first alignment mark 111 is disposed on the packaging substrate 100, so that the alignment of the position before the cavity etching is formed is facilitated, and therefore, the optical position alignment precision in the cavity etching process can be improved, and the processing quality of the semiconductor package can be improved.

In some embodiments, the cavity 110 is a rectangular or square cavity 110, and the first alignment marks 111 include at least two first alignment marks 111 disposed diagonally.

The first alignment mark 111 and other alignment marks respectively include: a closed geometry, and intersecting lines within the closed geometry.

The first alignment mark 111 may be a geometric feature pattern formed by copper plating on at least one surface of the package substrate 100.

The electronic packaging structure is a chip.

In summary, in the embodiment of the present application, at least for the cavity forming process, the first alignment mark 111 is disposed on the package substrate 100, so as to facilitate the alignment of the position before the cavity etching is formed, thereby improving the optical position alignment precision in the cavity etching process and improving the processing quality of the semiconductor package.

Further, by providing alignment marks required for different processes on the package substrate 100, it is convenient to ensure that optical positioning in a plurality of processing steps is not interfered with each other, and positioning errors are prevented, so that the processing precision of semiconductor package can be improved, and the yield can be improved.

Further, by embedding a low cost RDL fanout substrate within the ABF substrate cavity, high density inter-die interconnects can be accomplished at a minimum cost.

Various embodiments in this specification are described in terms of their associated methods, and reference is made to each other or to cross-reference thereto.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-On-y Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. An electronic packaging method, comprising:

embedding a re-wiring layer substrate into the cavity after etching the cavity, and exposing the top of the re-wiring layer substrate;

and connecting one part of the die unit to the rerouting layer substrate and connecting the other part of the die unit to the packaging substrate, wherein the die unit is positioned above the rerouting layer substrate and the packaging substrate.

2. The electronic packaging method of claim 1, wherein the optically etching the first etched region comprises: and etching at least one cavity in a first etching area on the packaging substrate through laser etching or exposure and development, wherein the bottom surface of at least one cavity is exposed.

3. The electronic packaging method according to claim 1, wherein the cavity is a rectangular or square cavity, and the first alignment marks include at least two, and the two first alignment marks are diagonally arranged.

4. The electronic packaging method according to claim 1 or 2, characterized in that the method further comprises: forming a second alignment mark on the packaging substrate corresponding to the periphery of the first etching area where the cavity is located;

the embedding of the rewiring layer substrate in the cavity comprises: and in the process of embedding the rewiring layer substrate into the cavity, taking the second alignment mark as a mounting position reference, and calibrating and positioning the mounting position of the rewiring layer substrate in the cavity.

5. The electronic packaging method according to claim 4, wherein the second alignment marks include at least two second alignment marks disposed diagonally;

The calibrating and positioning the mounting position of the rewiring layer substrate in the cavity comprises the following steps:

positioning the midpoint of a connecting line between the two second positioning marks based on at least two second alignment marks;

adjusting a center point of the rewiring layer substrate to be aligned with the center point, and aligning an edge of the rewiring layer substrate with an edge of the cavity;

after the positioning is completed, the method further comprises: and placing the rewiring layer substrate into the cavity and on the exposed bottom surface of the cavity.

6. The electronic packaging method of claim 5, further comprising: forming a third alignment mark on the packaging substrate and at the edge of the ball implantation area; the ball implantation area is positioned at the periphery of the first etching area and used for forming bonding conductive points thereon, the third alignment marks at least comprise two, and at least two third alignment marks are diagonally arranged at the inner side of the edge of the ball implantation area;

after forming the redistribution layer substrate in the cavity, the method further comprises:

calibrating circuit patterns on a mask plate to align with ball-planting areas on the packaging substrate and the rewiring layer substrate according to at least two third positioning marks;

Forming a first bonding conductive point in a ball-implanting area on the packaging substrate based on the mask plate, and forming a second bonding conductive point in the ball-implanting area on the rewiring layer substrate; the first bonding conductive points and the second bonding conductive points are respectively used for bonding and interconnection with the bonding surfaces of the grain units.

7. The electronic packaging method of claim 6, further comprising: forming a fourth alignment mark on the packaging substrate and positioned outside the ball implantation area; the fourth alignment marks at least comprise two, at least two are diagonally arranged at the outer side of the ball planting area, wherein connecting lines of the at least two fourth alignment marks and connecting lines of the at least two third alignment marks are arranged in a crossing manner;

8. The electronic packaging method of claim 7, wherein the die unit comprises at least: a first crystal grain and a second crystal grain, wherein positioning mark points for attachment positioning are respectively arranged on the first crystal grain and the second crystal grain;

And adjusting the bonding surface of the second die to be aligned with the first bonding conductive point of the second side region of the underlying package substrate and to be aligned with the second bonding conductive point of the second side region of the underlying rewiring layer substrate; the first crystal grains and the second crystal grains are arranged side by side at intervals, and the first side area and the second side area are symmetrical relative to the symmetry axis of the rewiring layer substrate.

9. The electronic packaging method of claim 1, wherein the first alignment mark is a geometric feature pattern.

10. The electronic packaging method according to claim 1, wherein the rerouting layer substrate is mainly composed of dielectric layers and metal layers stacked alternately, wherein the metal layers are coupled to each other, and the dielectric layers are insulating materials.

11. An electronic package structure, comprising:

a package substrate, wherein at least one surface of the package substrate is provided with at least one cavity, and the bottom surface of at least one cavity is exposed;

12. The electronic package of claim 11, wherein the cavity is a rectangular or square cavity, and the first alignment marks comprise at least two first alignment marks disposed diagonally.

13. The electronic package of claim 11 or 12, wherein the first alignment mark comprises: a closed geometry, and intersecting lines within the closed geometry.

14. The electronic package of claim 11, wherein the electronic package is a chip.