CN116053130A - Method for preparing deep trenches step by step - Google Patents

Method for preparing deep trenches step by step Download PDF

Info

Publication number
CN116053130A
CN116053130A CN202211735019.1A CN202211735019A CN116053130A CN 116053130 A CN116053130 A CN 116053130A CN 202211735019 A CN202211735019 A CN 202211735019A CN 116053130 A CN116053130 A CN 116053130A
Authority
CN
China
Prior art keywords
etching
epitaxial layer
preset
patterned mask
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211735019.1A
Other languages
Chinese (zh)
Inventor
沈志钦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Fuxin Semiconductor Co Ltd
Original Assignee
Hangzhou Fuxin Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Fuxin Semiconductor Co Ltd filed Critical Hangzhou Fuxin Semiconductor Co Ltd
Priority to CN202211735019.1A priority Critical patent/CN116053130A/en
Publication of CN116053130A publication Critical patent/CN116053130A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The present disclosure provides a method for preparing deep trenches step by step, the method comprising: acquiring an initial semiconductor structure; depositing epitaxial material with preset thickness on the surface of the initial semiconductor structure to form an epitaxial layer; forming a patterned mask layer on the epitaxial layer; etching the epitaxial layer according to the patterned mask layer to obtain a preset groove; removing the patterned mask layer; depositing an anti-reflection substance into the preset groove and overflowing the anti-reflection substance to the surface of the epitaxial layer; etching back the anti-reflection material; and repeatedly depositing epitaxial materials to form an epitaxial layer, and repeatedly etching the epitaxial layer until the times of etching the epitaxial layer reach the target etching times, so as to obtain the deep trench with the target etching depth. The deep groove is prepared by the method through the step-by-step epitaxial layer growth-etching mode, the difficulty in processing the deep groove can be reduced, the risk of generating defects is reduced, the processing precision, the yield and the reliability of products are improved, and the requirement on an etching machine is reduced.

Description

Method for preparing deep trenches step by step
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a method for preparing deep trenches step by step.
Background
In the production and preparation process of the semiconductor chip, the situation that a high-depth-ratio structure needs to be etched and a deep groove needs to be etched immediately is met, and the traditional process usually adopts a single-step etching method when the high-depth-ratio structure is etched, namely the etching of the high-depth-ratio structure is completed at one time. However, as the depth value to be etched is larger, the polymer generated in the etching process is not easy to be pumped away and gathered at the bottom or the side wall of the groove, which not only can prevent the etching from being carried out, but also can cause various defects, the shape after etching is difficult to control, the shape and the size of the position near the bottom of the deep groove deviate from the pattern defined by the mask, and the shape and the size deviate, so that the electrical property and the manufacturing process of different products can be influenced; and the processing capability of the deep groove etched by the single-step etching method on the machine is a great challenge, and the processing precision is difficult to control well.
Disclosure of Invention
The present disclosure provides a method for preparing deep trenches step by step to at least solve the above technical problems existing in the prior art.
According to a first aspect of the present disclosure, there is provided a method of preparing deep trenches step by step, the method comprising: step 101, obtaining an initial semiconductor structure; step 102, depositing an epitaxial material with a preset thickness on the surface of the initial semiconductor structure to form an epitaxial layer; step 103, forming a patterned mask layer on the epitaxial layer; step 104, etching the epitaxial layer according to the patterned mask layer to obtain a preset groove; step 105, removing the patterned mask layer; step 106, depositing an anti-reflection substance into the preset groove and overflowing the anti-reflection substance to the surface of the epitaxial layer; step 107, etching back the anti-reflection substance; and 108, continuing depositing epitaxial materials on the surface of the epitaxial layer to form the epitaxial layer, and repeating the steps 103-107 until the times of etching the epitaxial layer reach the target etching times so as to obtain the deep groove with the target etching depth.
In an embodiment, the method further comprises: and determining the target etching times for preparing the deep groove according to the target etching depth and the single etching depth.
In an embodiment, the forming a patterned mask layer on the epitaxial layer includes: coating photoresist on the surface of the epitaxial layer; and photoetching the photoresist to form a patterned mask layer.
In an embodiment, the width of the preset trench obtained by etching the epitaxial layer at the last time is larger than the width of the preset trench obtained by etching the epitaxial layer at the previous time.
In an embodiment, the etching the epitaxial layer according to the patterned mask layer includes: etching the epitaxial layer according to the patterned mask layer and a preset angle to enable the preset groove formed after etching and the side wall of the semiconductor structure to form an inclined angle.
In one embodiment, the angle of inclination is in the range of 88 ° -90 °.
In an embodiment, the bottom width of the preset trench obtained by etching the epitaxial layer at the last time is greater than the top width of the preset trench obtained by etching the epitaxial layer at the previous time.
In an embodiment, after obtaining the deep trench having the target etch depth, the method further comprises: and removing the anti-reflection substance deposited in the deep trench.
In one embodiment, the antireflective substance is a bottom antireflective coating.
In one embodiment, the epitaxial material is silicon.
According to the method for preparing the deep trenches step by step, an epitaxial layer is formed by depositing epitaxial materials with preset thickness on the surface of an initial semiconductor structure, a patterned mask layer is formed on the epitaxial layer, etching is conducted on the epitaxial layer according to the patterned mask layer, the preset trenches are obtained, the patterned mask layer is removed, anti-reflection substances are deposited in the preset trenches, etching is conducted on the anti-reflection substances, the epitaxial materials are repeatedly grown to form the epitaxial layer, and etching is conducted on the epitaxial layer repeatedly until the etching times reach the target etching times, so that the deep trenches with the target etching depths are obtained. The deep groove is prepared by the method of step-by-step epitaxial layer growth and etching, so that the difficulty in processing the deep groove can be reduced, the risk of generating defects is reduced, the processing precision and the yield and reliability of products are improved, the requirement on an etching machine is reduced, and the cost is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a schematic diagram of an implementation flow of a method for preparing deep trenches step by step in an embodiment of the disclosure;
fig. 2A-2S are schematic cross-sectional views illustrating an implementation scenario of step-by-step deep trench fabrication according to an embodiment of the present disclosure.
The reference numerals in the figures illustrate: 201. an initial semiconductor structure; 202. a first epitaxial layer; 203. a patterned mask layer; 204. a first preset groove; 205. an antireflective substance; 206. a second epitaxial layer; 207. a second preset groove; 208. deep trenches having a target can be depth; 209. a third epitaxial layer; 210. and a third preset groove.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
Fig. 1 shows a schematic implementation flow diagram of a method for preparing deep trenches in a distributed manner according to an embodiment of the disclosure.
Referring to fig. 1, according to an embodiment of the present disclosure, there is provided a method for preparing deep trenches step by step, the method comprising: step 101, obtaining an initial semiconductor structure; step 102, depositing an epitaxial material with a preset thickness on the surface of an initial semiconductor structure to form an epitaxial layer; step 103, forming a patterned mask layer on the epitaxial layer; step 104, etching the epitaxial layer according to the patterned mask layer to obtain a preset groove; step 105, removing the patterned mask layer; step 106, depositing an anti-reflection substance into the preset groove and overflowing the anti-reflection substance to the surface of the epitaxial layer; step 107, etching back the anti-reflection material; and 108, continuing depositing epitaxial materials on the surface of the epitaxial layer to form the epitaxial layer, and repeating the steps 103-107 until the etching times of the epitaxial layer reach the target etching times so as to obtain the deep groove with the target etching depth.
According to the method for preparing the deep trenches step by step, the epitaxial layer is formed by depositing epitaxial materials with the preset thickness on the surface of the initial semiconductor structure, the patterned mask layer is formed on the epitaxial layer, the epitaxial layer is etched according to the patterned mask layer to obtain the preset trenches, then the patterned mask layer is removed, anti-reflection substances are deposited in the preset trenches, the anti-reflection substances are etched back, the epitaxial material is repeatedly grown to form the epitaxial layer, and etching is repeatedly performed on the epitaxial layer until the etching times reach the target etching times, so that the deep trenches with the target etching depths are obtained. The deep trench is prepared by the method of step growth epitaxial layer-etching, thus the deep trench is obtained by multiple times of etching, compared with the preparation of the deep trench by single-step etching, the preparation of the deep trench is decomposed into multiple times of etching, the difficulty in processing the deep trench is reduced, an anti-reflection substance is added into the preset trench after each time of etching is finished, finally the anti-reflection substance is removed to obtain the deep trench with the target etching depth, and the removal of the anti-reflection substance to obtain the deep trench with the target etching depth is easier than the direct removal of the epitaxial layer to obtain the deep trench with the target etching depth, so that the preparation of the deep trench is simpler, the risk of generating defects can be reduced, the processing precision and the yield and reliability of products are improved, the requirement on an etching machine table is reduced, and the cost is reduced.
Specifically, the initial semiconductor structure is a semiconductor structure that has not been etched to create a trench. Epitaxial material is a material that can continue to grow on the basis of the original semiconductor structure by depositing epitaxial material on the surface of the original semiconductor structure, i.e., forming an epitaxial layer. The preset thickness can be determined according to the single etching depth when etching is performed, the preset thickness is larger than or equal to the single etching depth, specifically, the preset thickness of the first deposited preset material can be larger than or equal to the single etching depth when etching is performed for the first time, and after the first etching is completed to obtain the preset groove, the preset thickness of the preset material deposited each time is equal to the single etching depth after etching is performed. The deposition method for depositing the epitaxial material with the preset thickness can be a physical vapor deposition method or a chemical vapor deposition method.
And forming a patterned mask layer on the epitaxial layer, and etching the epitaxial layer according to the patterned mask layer to obtain a preset groove, wherein the obtained preset groove also has a shape consistent with the pattern in the patterned mask layer. Further, the method for forming the patterned mask layer comprises the following steps: gray scale lithography, nanoimprint, gray scale mask lithography and ion book gas assisted deposition. After the preset trench is obtained, the patterned mask layer is removed, and specifically, the removal can be performed in an etching manner.
After the patterned mask layer is removed, anti-reflection substances are deposited into the preset grooves obtained by etching and overflow to the surface of the epitaxial layer, wherein the anti-reflection substances are deposited for protecting the preset grooves which are formed, so that damage to the preset grooves which are etched when the next etching is performed is prevented, and the sizes of the preset grooves are influenced. Since the anti-reflection substance overflows to the surface of the epitaxial layer when the anti-reflection substance is deposited in the preset groove, a part of the anti-reflection substance needs to be etched back to remove the anti-reflection substance on the surface of the epitaxial layer until the upper surface of the anti-reflection substance is flush with the surface of the epitaxial layer or the upper surface of the anti-reflection substance is slightly lower than the surface of the epitaxial layer, and specifically, a plasma etching method can be adopted to etch back a part of the anti-reflection substance.
And repeating the process from depositing the epitaxial material to etching back the deposited anti-reflection substance until the number of times of etching the epitaxial layer is the target etching number, stopping etching to obtain the deep trench with the target etching depth, so that the conventional one-step preparation of the deep trench with the target etching depth is changed into step preparation, and the appearance of the position near the bottom of the deep trench is slightly different from the defined pattern, thereby obtaining the deep trench meeting the requirements.
In an embodiment, the method further comprises: and determining the target etching times for preparing the deep trench according to the target etching depth and the single etching depth.
Specifically, the number of target etches is determined according to a target etch depth and a single etch depth, which may be the same or different, the single etch depth being related to the degree of deposition of the epitaxial material to form the epitaxial layer. For example, a deep trench of 10 micrometers is to be etched, the single etching depth can be 1 micrometer and 2 micrometers, when etching is performed, if the single etching depth is selected to be 1 micrometer, 10 times of etching are needed to obtain a target etching depth of 10 micrometers, namely, the target etching times are 10, if the single etching depth is selected to be 2 micrometers, 5 times of etching are needed to obtain a target etching depth of 10 micrometers, namely, the target etching times are 5, in addition, the single etching times selected when etching is performed can be 1 micrometer or 2 micrometers, the target etching times can be determined according to the single etching depth and the target etching depth, and the single etching times selected when etching is performed can be determined according to an actual process.
In one embodiment, forming a patterned mask layer on the epitaxial layer includes: coating photoresist on the surface of the epitaxial layer; and photoetching the photoresist to form a patterned mask layer.
Specifically, the photoresist is coated on the surface of the epitaxial layer, and in order to make the photoresist coated on the surface of the epitaxial layer smoother, the photoresist can be coated in a rotating manner. The photoresist is prepared from a photosensitive resin, a sensitizer and a solvent which are 3 main components and are mixed with light-sensitive liquid, and the photoresist is irradiated or radiated by ultraviolet light, electron beams, ion beams, X rays and the like, so that the solubility of the photoresist can be changed, and the photoresist is subjected to alignment exposure, baking and development to obtain a patterned mask layer.
In an embodiment, the width of the preset trench obtained by etching the epitaxial layer at the next time is larger than the width of the preset trench obtained by etching the epitaxial layer at the previous time.
When the deep trenches are prepared in a distributed manner, etching is performed on the epitaxial layer according to the patterned mask layer at the first time, after the preset trenches are obtained, the patterned mask layer is removed, anti-reflection substances are deposited in the preset trenches, the deposited anti-reflection substances are etched back to remove the anti-reflection substances on the surface of the epitaxial layer, then epitaxial materials are continuously deposited on the surface of the epitaxial layer to form the epitaxial layer, the patterned mask layer is formed on the epitaxial layer to perform the next etching, and in order to ensure that the preset trenches obtained by the next etching can be aligned with the preset trenches obtained by the previous etching, the problems of difficulty in depositing the film layer, electrical failure and the like caused by the phenomenon of displacement are avoided, and the width of the preset trenches obtained by the next etching of the epitaxial layer is slightly larger than that of the preset trenches obtained by the previous etching of the epitaxial layer.
In an embodiment, the width of the preset trench obtained by the last etching is too large compared with the width of the preset trench obtained by the previous etching, which causes the problems of electrical property change, low area utilization rate of the manufactured chip device, and the like. Therefore, preferably, the width of the preset groove obtained by etching the epitaxial layer at the next time is 10 nanometers larger than the width of the preset groove obtained by etching the epitaxial layer at the previous time, and the influence of 10 nanometers is acceptable and the width is favorable for improving the yield of the chip.
In one embodiment, etching the epitaxial layer according to the patterned mask layer includes: etching the epitaxial layer according to a preset angle according to the patterned mask layer, so that an inclination angle is formed between the preset groove formed after etching and the side wall of the semiconductor structure.
Specifically, when the epitaxial layer is etched to form a preset groove, the epitaxial layer is etched from top to bottom according to a preset angle, so that the width of the preset groove is gradually narrowed from top to bottom, and the angle between the preset groove formed after etching and the side wall of the semiconductor structure is the inclination angle.
In one embodiment, the angle of inclination ranges from 88 ° to 90 °, i.e., the epitaxial layer is etched at an angle between 88 ° and 90 ° each time, including 88 ° and 90 °, according to the patterned mask layer, such that the predetermined trench formed after etching forms an angle of inclination ranging from 88 ° to 90 ° with the sidewalls of the semiconductor structure. When the inclination angle is in the range of 88-90 degrees, the bottom of the preset groove obtained by each etching can reach the uniformity of the electric property of the groove under the condition that the deep groove can be manufactured, and the process requirements can be met when the film structures such as an oxide layer and the like are deposited later.
In one embodiment, the inclination angle is preferably 89 °, that is, the epitaxial layer is etched at an angle of 89 ° according to the patterned mask layer, so that the inclination angle formed by the preset trench formed after etching and the side wall of the semiconductor structure is 89 °.
Specifically, the preset angle used for etching the epitaxial layer according to the patterned mask layer can be the same or different each time, but the preset angle used for etching each time is in the range of 88-90 degrees. Preferably, each time etching is performed at the same preset angle. In addition, the preset angle adopted in etching can be determined according to the target etching depth, the preset angle can be more approximate to 90 degrees when the target etching depth is larger, and the preset angle can be more approximate to 88 degrees when the target etching depth is smaller.
In an implementation scenario, if the thickness of the formed epitaxial layer is 1000 nm, that is, the single etching depth is 1000 nm, the bottom width of the prepared deep trench is 200 nm, and the epitaxial layer is etched according to the patterned mask layer at a preset angle of 89 degrees, so that the preset trench formed after etching and the side wall of the semiconductor structure form an inclination angle of 89 degrees, then the top width of the preset trench obtained by the etching can be obtained by calculation.
In an embodiment, the bottom width of the preset trench obtained by etching the epitaxial layer at the next time is larger than the top width of the preset trench obtained by etching the epitaxial layer at the previous time.
The epitaxial layer is etched according to the preset angle, so that the top width of the preset groove obtained after each etching is larger than the bottom width, and the bottom width of the preset groove obtained after the last etching is slightly larger than the top width of the preset groove obtained by the previous etching in order to ensure that the preset groove obtained by the next etching is aligned with the preset groove obtained by the previous etching, so that the problems of difficult film deposition, electrical failure and the like caused by displacement are avoided.
In one embodiment, the bottom width of the preset trench obtained by the previous etching is preferably 10 nm larger than the top width of the preset trench obtained by the previous etching.
In an embodiment, after obtaining the deep trench having the target etch depth, the method further comprises: and removing the anti-reflection substance deposited in the deep trench.
Specifically, before the etching times do not reach the target etching times, an anti-reflection coating is deposited in the preset groove after each time of etching to generate the preset groove, so that when the etching times reach the target etching times, the total etching depth obtained after the etching for the target etching times is indicated to meet the target etching depth, and at the moment, anti-reflection substances deposited for the previous times are removed, so that the deep groove with the target etching depth is obtained. In one embodiment, the anti-reflective material deposited in the deep trench may be removed by etching.
In one embodiment, the antireflective substance is a bottom antireflective coating.
Specifically, the bottom anti-reflection coating is used as a filling material when deep trenches are prepared step by step, and has the characteristics of easy filling and easy removal. And removing the bottom anti-reflection coating inside the preset groove by using an ashing method to obtain the deep groove with the target etching depth.
In one embodiment, the epitaxial material is silicon.
Fig. 2A-2S are schematic cross-sectional views illustrating an implementation scenario of step-by-step deep trench fabrication according to an embodiment of the present disclosure.
First, as in fig. 2A, an initial semiconductor structure 201 is obtained; as shown in fig. 2B, a first epitaxial layer 202 is formed by depositing a predetermined thickness of epitaxial material on the surface of the initial semiconductor structure 201; as shown in fig. 2C, a patterned mask layer 203 is formed on the first epitaxial layer 202; referring to fig. 2D, according to the patterned mask layer 203, the first epitaxial layer 202 is etched to obtain a first preset trench 204; as shown in fig. 2E, the patterned mask layer 203 is removed; as shown in fig. 2F, an anti-reflective material 205 is deposited into the first pre-defined trench 204 and overflows the surface of the first epitaxial layer 202; referring to fig. 2G, the anti-reflective material 205 is etched back to remove the anti-reflective material 205 on the surface of the first epitaxial layer 202; as shown in fig. 2H, deposition of epitaxial material continues on the surface of the first epitaxial layer 202 as shown in fig. 2G, forming a second epitaxial layer 206; as shown in fig. 2I, a patterned mask layer 203 is formed on the second epitaxial layer 206; as shown in fig. 2J, the second epitaxial layer 206 is etched to obtain a second preset trench 207; as shown in fig. 2K, the patterned mask layer 203 is removed; as shown in fig. 2L, if the target etching times are two times, the anti-reflection substance 205 deposited after the first etching is removed, so as to obtain the deep trench 208 with the target etching depth.
If the target etching times are more than two times, as shown in fig. 2M, depositing an anti-reflection substance 205 in the second preset trench 207 obtained as shown in fig. 2K and overflowing the surface of the second epitaxial layer 206; as shown in fig. 2N, the anti-reflective material is etched back only to remove the anti-reflective material 205 on the surface of the second epitaxial layer 206; as shown in fig. 2O, deposition of epitaxial material continues on the surface of the second epitaxial layer 206 shown in fig. 2N, forming a third epitaxial layer 209; as shown in fig. 2P, a patterned mask layer 203 is formed on the third epitaxial layer 209; as shown in fig. 2Q, the third epitaxial layer 209 is etched to obtain a third preset trench 210; as in fig. 2R, the patterned mask layer 203 is removed; referring to fig. 2S, if the target etching depth is 3 times, the anti-reflection substance 205 deposited after the first etching and the second etching is clear, and the deep trench 208 with the target etching depth is obtained. If the target etching depth is greater than three times, continuing to deposit the epitaxial material to form an epitaxial layer, and etching the epitaxial layer until the times of etching the epitaxial layer is the target etching times, and finally obtaining the deep groove with the target etching depth.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A method of preparing deep trenches in steps, the method comprising:
step 101, obtaining an initial semiconductor structure;
step 102, depositing an epitaxial material with a preset thickness on the surface of the initial semiconductor structure to form an epitaxial layer;
step 103, forming a patterned mask layer on the epitaxial layer;
step 104, etching the epitaxial layer according to the patterned mask layer to obtain a preset groove;
step 105, removing the patterned mask layer;
step 106, depositing an anti-reflection substance into the preset groove and overflowing the anti-reflection substance to the surface of the epitaxial layer;
step 107, etching back the anti-reflection substance;
and 108, continuing depositing epitaxial materials on the surface of the epitaxial layer to form the epitaxial layer, and repeating the steps 103-107 until the times of etching the epitaxial layer reach the target etching times so as to obtain the deep groove with the target etching depth.
2. The method according to claim 1, wherein the method further comprises:
and determining the target etching times for preparing the deep groove according to the target etching depth and the single etching depth.
3. The method of claim 1, wherein forming a patterned mask layer over the epitaxial layer comprises:
coating photoresist on the surface of the epitaxial layer;
and photoetching the photoresist to form a patterned mask layer.
4. The method of claim 1, wherein the width of the pre-determined trench that is etched from the epitaxial layer at a later time is greater than the width of the pre-determined trench that is etched from the epitaxial layer at a previous time.
5. The method of claim 1, wherein etching the epitaxial layer according to the patterned mask layer comprises:
etching the epitaxial layer according to the patterned mask layer and a preset angle to enable the preset groove formed after etching and the side wall of the semiconductor structure to form an inclined angle.
6. The method of claim 5, wherein the angle of inclination is in the range of 88 ° -90 °.
7. The method of claim 5 or 6, wherein a bottom width of the preset trench obtained by etching the epitaxial layer at a later time is greater than a top width of the preset trench obtained by etching the epitaxial layer at a previous time.
8. The method of claim 1, wherein after obtaining the deep trench having the target etch depth, the method further comprises:
and removing the anti-reflection substance deposited in the deep trench.
9. The method of claim 1, wherein the antireflective substance is a bottom antireflective coating.
10. The method of claim 1, wherein the epitaxial material is silicon.
CN202211735019.1A 2022-12-31 2022-12-31 Method for preparing deep trenches step by step Pending CN116053130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211735019.1A CN116053130A (en) 2022-12-31 2022-12-31 Method for preparing deep trenches step by step

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211735019.1A CN116053130A (en) 2022-12-31 2022-12-31 Method for preparing deep trenches step by step

Publications (1)

Publication Number Publication Date
CN116053130A true CN116053130A (en) 2023-05-02

Family

ID=86117660

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211735019.1A Pending CN116053130A (en) 2022-12-31 2022-12-31 Method for preparing deep trenches step by step

Country Status (1)

Country Link
CN (1) CN116053130A (en)

Similar Documents

Publication Publication Date Title
CN107112212B (en) Patterning substrates using grafted polymeric materials
TWI505324B (en) Method for forming high density patterns
KR100562189B1 (en) Design of lithography alignment and overlay measurement marks on cmp finished damascene surface
US8138093B2 (en) Method for forming trenches having different widths and the same depth
KR20180045892A (en) Method for forming an etching mask for substrate patterning with less resolution
CN105589131B (en) A kind of silicon chip groove etching method for optical waveguide
TWI625602B (en) Method for patterning a substrate using extreme ultraviolet lithography
CN103871846B (en) The application of autoregistration multiple patterning methods and silicon substrate hard mask compositions
JP2004134574A (en) Manufacturing method of semiconductor device
US9097975B2 (en) Double patterning by PTD and NTD process
KR20170120516A (en) Method for forming organic film and method for manufacturing substrate for semiconductor apparatus
US20230223349A1 (en) Method for forming overlay marks and semiconductor structure
CN116053130A (en) Method for preparing deep trenches step by step
CN117406319A (en) Processing method of relief helical grating
CN108962726A (en) The forming method of semiconductor devices
US6569578B2 (en) Method for forming photo-mask
US20120225560A1 (en) Manufacturing method of integrated circuits based on formation of lines and trenches
CN108107497A (en) Preparing grating method
CN111103767B (en) Semiconductor device, manufacturing method thereof and electronic equipment
KR100953053B1 (en) Method of forming fine patterns in semiconductor device
JP3959212B2 (en) Mask pattern correction method and exposure mask using the same
CN111834201A (en) Semiconductor process
TW419722B (en) Method for producing photoresist with uniform coating
US11211258B2 (en) Method of addressing dissimilar etch rates
CN104752314B (en) A kind of semiconductor devices and preparation method with sti structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination