CN116050333A - Method for identifying nonfunctional device in analog circuit - Google Patents

Method for identifying nonfunctional device in analog circuit Download PDF

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CN116050333A
CN116050333A CN202310078259.7A CN202310078259A CN116050333A CN 116050333 A CN116050333 A CN 116050333A CN 202310078259 A CN202310078259 A CN 202310078259A CN 116050333 A CN116050333 A CN 116050333A
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赖昕栎
杨成林
田书林
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University of Electronic Science and Technology of China
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Abstract

The invention discloses a non-functional device identification method in an analog circuit design drawing, which comprises the steps of extracting element information and node information of an analog circuit according to a netlist file of the analog circuit, traversing an element dictionary set, judging a short circuit device according to the node information, selecting root nodes, generating a node tree based on each root node, identifying a cutting point in the analog circuit by adopting a Tarjan algorithm, searching paths according to the cutting point and sub-nodes which enable the cutting point to be the cutting point, taking elements passing through the paths as non-functional elements, and obtaining a collection of the short circuit elements and the non-functional elements as a final non-functional element collection. The invention can automatically identify nonfunctional components in the analog circuit according to the analog circuit diagram, and reduce the number of faults to be simulated of the analog circuit, thereby shortening the time of fault simulation of the analog circuit.

Description

Method for identifying nonfunctional device in analog circuit
Technical Field
The invention belongs to the technical field of analog circuits, and particularly relates to a method for identifying nonfunctional devices in an analog circuit.
Background
The automotive industry is currently the fastest growing integrated circuit market, and the integrated circuits of automobiles contain a large number of analog circuits, and the defective components of automobile ICS (Integrated Circuit Systems) must be zero as specified, which means that 100% fault coverage is required. The essential link for realizing high fault coverage rate is the fault simulation of an analog circuit, the coverage rate of 100% is required, and the fault simulation is required to be carried out on each device in the circuit. Because the circuit scale of the vehicle-scale is huge, the circuit design diagram contains thousands of components, and by taking hard faults as examples, each two-port device has two hard faults of open circuit and short circuit, three-port devices are more, the simulation time is intolerable, and the simulation time can be up to months or even years, so that the fault simulation time of the analog circuit is very necessary to be shortened as much as possible.
The method for shortening the fault simulation time of the analog circuit mainly comprises the following two directions: (1) accelerating the circuit simulation speed; (2) The scheme for reducing the number of circuit simulations can be subdivided into the following three schemes: (1) fault equivalence; (2) identification of isolated components; (3) identification of nonfunctional (invalid) components. At present, identification of nonfunctional components is mostly carried out manually, and efficiency is low.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a method for identifying nonfunctional devices in an analog circuit, which automatically identifies nonfunctional devices in the analog circuit according to an analog circuit diagram, reduces the number of faults required to be simulated by the analog circuit, and shortens the time for simulating faults of the analog circuit.
In order to achieve the above object, the method for identifying a nonfunctional device in an analog circuit of the present invention comprises the steps of:
s1: extracting element information and node information of the analog circuit according to a netlist file of the analog circuit to obtain element dictionary set Components and node dictionary set Nodes, wherein keys in the element dictionary set Components are element names, values are arrays and are used for storing node names connected with the element, keys in the node dictionary set Nodes are node names, values are arrays and are used for storing element names connected with the node;
s2: traversing Components of the dictionary set of Components, comparing node names of each component, and adding the component into the short-circuit device set A when the same node names exist in a plurality of node names connected with a certain component;
s3: k nodes are selected from the nodes of the analog circuit as root nodes according to actual needs.
S4: let k=1;
s5: the cutting point in the analog circuit is identified by adopting a Tarjan algorithm based on the kth root node, and the specific method is as follows:
s5.1: based on the kth root node, the keys in the node dictionary set Nodes are used as Nodes, the keys in the component dictionary set Components are used as the connection lines between the Nodes, and the connection relation between different Nodes is determined by the mutual search of the Components and the node dictionary sets, so that a node tree is obtained k
S5.2: each node in the node tree is searched in a depth-first mode, and each node x in the node tree is obtained i The order accessed during the depth-first search is taken as node x i Time stamp dfn [ x ] of (2) i ]I=1, 2, …, N represents the number of nodes;
s5.3: according to each node x i Time stamp dfn [ x ] of (2) i ]Traversing each node, and determining each node x based on Tarjan algorithm i Is a trace-back value low x i ]The specific method comprises the following steps:
the current node is recorded as now, and a traceability value low [ now ] is initialized]=dfn[now]The subtree number child=0, and the parent node fa and all child nodes to of the node now are obtained d D=1, 2, …, D representing the number of sub-nodes of the node now, to for each sub-node d If the sub-node to d Timestamp dfn [ to ] d ]Timestamp low [ now ] less than node now]Then node to d Is an ancestor node, further judges whether to d =fa, if not, update the trace back value low [ now ] of node now]=min(low[now],dfn[to d ]) Otherwise, do nothing; if the sub-node to d Timestamp dfn [ to ] d ]Timestamp Low [ now ] greater than node now]Let child tree number child=child+1 of node now, then sub-node to d Determining its traceback value low to by using improved Tarjan algorithm d ]Then updating the traceability value low of node now]=min(low[now],low[to d ]);
After all nodes determine the traceability value, judging whether each node is a cut point or not in sequence, wherein the specific method comprises the following steps:
when the node isx i Judging whether the number of subtrees is more than or equal to 2 if the number is the root node, if so, node x i If the cutting point is the cutting point, otherwise, the cutting point is not the cutting point;
when node x i Not the root node, if node x i The trace back value of some sub-nodes in the sub-nodes of (a) is larger than the node x i Node x i As cut point, otherwise node x i Is not a cutting point;
node tree k The number of the obtained cutting points is M, and for the mth cutting point
Figure BDA0004066687580000031
i m The node sequence number of the mth cut point is represented, and the child nodes with the trace back value larger than the time stamp of the cut point in the child nodes are constructed to obtain +.>
Figure BDA0004066687580000032
Sub-node set toSet as cut point k,m M=1, 2, …, M;
s6: m cutting points obtained according to the step S5
Figure BDA0004066687580000033
Sub-node set toSet k,m Searching to obtain a nonfunctional component set B k The specific method comprises the following steps: for each cut point->
Figure BDA0004066687580000034
Optionally selecting a sub-node set toSet thereof k,m Taking one node as a sub-node to perform path searching, and ending the path searching when the searched sub-node is a cutting point or the sub-node does not exist; will be according to M cut points->
Figure BDA0004066687580000035
Sub-node set toSet k,m All the components passing through the paths obtained by searching form a tree according to the current node k The obtained nonfunctional component set B k
S7: judging whether K is less than K, if yes, entering a step S8, otherwise, entering a step S9;
s8: let k=k+1, return to step S5;
s9: obtaining a short circuit device set A and K nonfunctional element sets B k To obtain the nonfunctional component set F of the analog circuit, i.e. F=A U.B 1 ∪B 2 ∪…∪B K
The invention relates to a non-functional device identification method in a design drawing of an analog circuit, which comprises the steps of extracting element information and node information of the analog circuit according to a netlist file of the analog circuit, traversing an element dictionary set, judging a short circuit device according to the node information, selecting root nodes, generating a node tree based on each root node, identifying a cutting point in the analog circuit by adopting a Tarjan algorithm, carrying out path search according to the cutting point and a sub-node which enables the cutting point to be the cutting point, taking elements passing through the path as non-functional elements, and solving a combined set of the short circuit element and the non-functional elements to obtain a final non-functional element set.
The invention abstracts the analog circuit into the undirected graph, solves the problems of short circuit and circuit breaking by utilizing the cutting points in the graph theory, realizes the automatic identification of nonfunctional components in the analog circuit according to the analog circuit graph, reduces the number of faults required to be simulated by the analog circuit, and shortens the time for simulating the faults of the analog circuit.
Drawings
FIG. 1 is a diagram of an example of a single device short circuit in an analog circuit;
FIG. 2 is a diagram of an example of a multi-device short circuit in an analog circuit;
FIG. 3 is a diagram of an exemplary schematic diagram of the analog circuit of FIG. 2;
FIG. 4 is a diagram of an example schematic diagram of an analog circuit with open circuit;
FIG. 5 is a flow chart of an embodiment of a method for identifying non-functional devices in an analog circuit according to the present invention;
FIG. 6 is a flow chart of the present invention for identifying cut points based on the Tarjan algorithm;
fig. 7 is a circuit diagram of a class b push-pull power amplifier circuit in the present embodiment;
FIG. 8 is an abstract view of the circuit configuration of the present embodiment;
FIG. 9 is a circuit diagram of a class B push-pull power amplifier circuit after a human set failure;
FIG. 10 is a diagram showing an example of a node tree of the circuit diagram shown in FIG. 9 in the present embodiment;
fig. 11 is a schematic diagram of a recursive reduction search path in the present embodiment.
Detailed Description
The following description of the embodiments of the invention is presented in conjunction with the accompanying drawings to provide a better understanding of the invention to those skilled in the art. It is to be expressly noted that in the description below, detailed descriptions of known functions and designs are omitted here as perhaps obscuring the present invention.
In order to better explain the present invention, a brief description of the principles of the present invention will be provided.
The non-functional components (also called as invalid components) in the invention refer to components which do not contribute to the circuit function in the analog circuit design diagram but are connected in a main circuit, and mainly refer to all components which are short-circuited and open-circuited. In the invention, the analog circuit is abstracted into an undirected graph, and then the cutting points in the graph theory are utilized to solve the short circuit and the open circuit, because only the circuit connection structure is concerned when the short open circuit condition in the analog circuit is considered, and the current flow direction, the component parameters and the like of the circuit connection structure are not concerned. The undirected graph reflects the connection relation between different nodes, and for the analog circuit graph, the connection relation is also a certain connection relation, namely, the connection relation between different components or between different ports, so that the ports are replaced by nodes, the components are replaced by wires, and the components are basically the same, so that the connection relation can be handled by abstracting the graph structure.
For analog circuits, the shorts are divided into individual device shorts and multi-device shorts. Fig. 1 is a diagram of an example of a single device short circuit in an analog circuit. As shown in fig. 1, in the case of a short circuit in an analog circuit, if a single device is short-circuited, for example, R3 is short-circuited, both nodes of R3 are 0, so that it is only necessary to compare whether the two nodes are equal to each other, so that the short circuit of the single device can be determined. Fig. 2 is a diagram of an example of a multi-device short circuit in an analog circuit. As shown in fig. 2, the components R1 and R2 are shorted together, and at this time, the port nodes of the two components are different, and the identification method of a single-component short circuit cannot be used. Fig. 3 is a diagram illustrating a schematic model of the analog circuit shown in fig. 2. As shown in fig. 3, the node 1 is obviously found to be a cut point when the whole circuit structure is exposed. In fact, if a node is a short-circuit node, no matter how many short-circuit devices are in the node, since both ends of the short-circuit are the same node, they can only be finally connected back to the main circuit through the same node, so the short-circuit node must be a cut-off point.
In the case of a circuit break in the analog circuit, because the circuit break occurs in the analog circuit, it is certain that there are components that are not connected back to the root node in the main circuit, and its ports are floating. Fig. 4 is a diagram of an example of a schematic model of an analog circuit in which a circuit break exists. As shown in fig. 4, no matter how many components are in the main circuit, the components return to the root node through a plurality of nodes, and the device with open circuit is suspended because the port is suspended, so the suspended node does not point to any next node, just like the component b shown in fig. 4, so that the components cannot return to any node in the search tree through detour, and therefore the node 2 becomes a cut point.
Based on the principle analysis, the invention provides a non-functional device identification method in an analog circuit.
FIG. 5 is a flow chart of an embodiment of a method for identifying nonfunctional devices in an analog circuit of the present invention.
As shown in fig. 5, the method for identifying the nonfunctional device in the analog circuit of the present invention comprises the following specific steps:
s501: obtaining analog circuit information:
and extracting the component information and the node information of the analog circuit according to a netlist (netlist) file of the analog circuit to obtain component dictionary set Components and node dictionary set Nodes, wherein keys in the component dictionary set Components are component names, values are arrays and are used for storing the node names connected with the Components, keys in the node dictionary set Nodes are node names, and values are arrays and are used for storing the component names connected with the Nodes.
S502: identifying a single component short:
traversing Components of the dictionary set of Components, comparing the node names of each component, and adding the component into the short-circuit device set A when the same node names exist in a plurality of node names connected with a certain component.
S503: a root node is selected.
K nodes are selected from the nodes of the analog circuit as root nodes according to actual needs.
The root node is used to generate a tree of nodes for searching to determine nonfunctional components. In practical application, if the selected root node itself has short-circuited components or is not connected in the main circuit, the node tree generated based on the root node will misjudge the components during searching, so that more root nodes are required to be set for searching respectively, and the obtained nonfunctional component set is more accurate and comprehensive. In the analog circuit, the ground node and the power source node can confirm that they are certainly connected in the main circuit, and therefore, the ground node and the power source node are preferably included in the K root nodes.
S504: let k=1.
S505: identifying a cutpoint based on the kth root node:
in step S502, only the case where a single component is shorted can be identified, and other methods are required for determining whether a plurality of connected components are shorted or disconnected. In the invention, before judging the short circuit or the open circuit of the component, the cutting point in the analog circuit needs to be firstly identified based on the Tarjan algorithm based on the kth root node. FIG. 6 is a flow chart of the present invention for identifying cut points based on the Tarjan algorithm. As shown in FIG. 6, the specific steps for identifying the cut point based on the Tarjan algorithm in the invention comprise the following steps:
s601: generating a node tree:
based on the kth root node, the keys in the node dictionary set Nodes are used as Nodes, the keys in the Component dictionary set Components are used as the connection lines between the Nodes, and the connection relations between different Nodes pass through the Componentss and Nodes are determined by searching each other to obtain a node tree k
S602: determining a node timestamp:
each node in the node tree is searched in a depth-first mode, and each node x in the node tree is obtained i The order accessed during the depth-first search is taken as node x i Time stamp dfn [ x ] of (2) i ]I=1, 2, …, N represents the number of nodes. Timestamp dfn [ x i ]I.e., the dfs_clock value at the time of access to the node in the Tarjan algorithm. dfs_clock is a global variable of the record traversal order, the initial value is 1, and the value of dfs_clock is increased by 1 every time a new node is reached.
S603: judging a cutting point:
then, judging the cut points in the node tree based on the Tarjan algorithm, and improving the existing Tarjan algorithm to adapt to the needs of the invention, wherein the specific method is as follows:
first of all, according to each node x i Time stamp dfn [ x ] of (2) i ]Traversing each node, and determining each node x based on Tarjan algorithm i Is a trace-back value low x i ]. The trace back value represents the minimum time stamp value in all nodes in the accessible search tree by an edge on a non-search tree starting with the current node as the root node of the search tree. The specific method for determining the traceability value is as follows:
the current node is recorded as now, and a traceability value low [ now ] is initialized]=dfn[now]The subtree number child=0, and the parent node fa and all child nodes to of the node now are obtained d D=1, 2, …, D representing the number of sub-nodes of the node now, to for each sub-node d If the sub-node to d Timestamp dfn [ to ] d ]Timestamp low [ now ] less than node now]Then node to d Is an ancestor node, further judges whether to d =fa, if not, update the trace back value low [ now ] of node now]=min(low[now],dfn[to d ]) Otherwise, do nothing; if the sub-node to d Timestamp dfn [ to ] d ]Timestamp Low [ now ] greater than node now]Let the number of subtrees of node nowchild=child+1, then child node to d Determining its traceback value low to by using improved Tarjan algorithm d ]Then updating the traceability value low of node now]=min(low[now],low[to d ])。
After all nodes determine the traceability value, whether each node is a cut point or not is sequentially judged. The definition of the cut point is as follows: if a node and all edges associated with the node are deleted from the graph, the graph is divided into two or more unconnected sub-graphs, then the node is referred to as a cut point of the graph. The specific method for judging the cutting point in the invention is as follows:
when node x i Judging whether the number of subtrees is more than or equal to 2 if the number is the root node, if so, node x i For a cut point, otherwise not. This is because when the number of subtrees is equal to or greater than 2, if the root node is removed, the subtrees will no longer interwork, so the root node is now the cut point.
When node x i Without root node, if node x i The trace back value of some sub-nodes in the sub-nodes of (a) is larger than the node x i Node x i As cut point, otherwise node x i Not the cut point. Because if the trace back value of the child node is larger, this means that node x is removed once i Node x i The ancestor node of (a) will no longer be in communication with its child node, so node x i Is a cut point.
Node tree k The number of the obtained cutting points is M, and for the mth cutting point
Figure BDA0004066687580000071
i m The node sequence number of the mth cut point is represented, and the child nodes with the trace back value larger than the time stamp of the cut point in the child nodes are constructed to obtain +.>
Figure BDA0004066687580000072
Sub-node set toSet as cut point k,m M=1, 2, …, M.
S506: determining a nonfunctional component based on the current cut point:
m cut points obtained according to step S505
Figure BDA0004066687580000073
Sub-node set toSet k,m Searching to obtain a nonfunctional component set B k The specific method comprises the following steps: for each cut point->
Figure BDA0004066687580000074
Optionally selecting a sub-node set toSet thereof k,m One node of the tree is used as a sub-node to perform path search, and when the searched sub-node is a cut point or the sub-node does not exist (namely, the tree arrives at the node tree) k End of (f) then the path search ends; will be according to M cut points->
Figure BDA0004066687580000075
Sub-node set toSet k,m All the components passing through the paths obtained by searching form a tree according to the current node k The obtained nonfunctional component set B k
S507: whether K < K is judged, if yes, the process proceeds to step S508, otherwise, the process proceeds to step 109.
S508: let k=k+1, return to step SS505.
S509: determining a set of nonfunctional components:
obtaining a short circuit device set A and K nonfunctional element sets B k To obtain the nonfunctional component set F of the analog circuit, i.e. F=A U.B 1 ∪B 2 ∪…∪B K
In order to better illustrate the technical scheme of the invention, the invention is experimentally verified by taking a class-B push-pull power amplifier circuit as an example. Fig. 7 is a circuit diagram of a class b push-pull power amplifier circuit in this embodiment. The component names and node names are labeled in fig. 7. The required circuit connection information is extracted from the circuit netlist file to construct a component dictionary set Components and a node dictionary set Nodes, as follows:
components: { 'qQ': [ '5', '4', '0', 'qQ' ], 1 '[' 1','2','5',' d2': ['3','4',' d1': ['2','3',' v2': ['1','0',' v1': [' Input ','0',' rR3 '[' Output ','0',' cC3'] ['5',' Output ',' rR2': 4', '0', 'rR 1'. It can be seen that the node connection relation corresponding to the component is stored in the Components dictionary set Components, for example, the last 'cC1' is [ 'Input', '2' ] represents that the component C1 is connected with the Input port and the 2 port, and is consistent with the circuit diagram information of fig. 3.
And (3) Nodes: { '5' [ 'qQ', 'qQ1', 'cC3', '4' [ 'qQ', 'dD2', 'rR2', 'cC2', '0' [ 'qQ2', 'v 1', 'rR3', 'rR2', '1' [ 'qQ1', 'v 2', 'rR1', '2' ], respectively, 'qQ1', 'dD1', 'rR1', 'cC1', '3' ], respectively, 'dD2','d 1', 'Input', 'cC2', 'cC1', 'Output 3', 'cC3' ]. The Nodes and their connected component information are stored in the Nodes, such as '5' [ ' qQ ', ' qQ '1', ' cC3' ], which means that the node 5 is connected with three components, Q2, Q1 and C3, respectively, which also coincides with the circuit diagram.
Firstly, the short circuit condition of a single component is identified, components of the component dictionary set are traversed, and the node name of one component is not found to be a subset of the node name of another component, so that no component is short-circuited in the embodiment.
Then constructing a graph abstracted by a circuit diagram structure through Components and node dictionary sets Nodes, traversing the node dictionary sets Nodes, taking a first element '5': [ 'qQ', 'qQ', 'c3' ] as an example, finding Nodes 4 and 0 in the Components to be connected with a node 5 through qQ2, finding Nodes 1 and 2 to be connected with the node 5 through qQ1, and finding Output to be connected with the node 5 through c3, namely, finding Nodes 4,0,1,2 and Output to be connected with the node 5. Then, the connection relation between the 4,0,1,2, output and 5 sub-nodes and other nodes can be obtained by the same method. The timestamp and traceback value for each node is then determined based on the Tarjan algorithm. Fig. 8 is an outline of the circuit configuration in this embodiment. As shown in fig. 8, the rectangular base color value is a time stamp, and the diamond base color value is a trace back value. It can be seen that, starting from the root node, there are three search paths obtained in this embodiment:
①:5→4→0→1→2→3
②:5→4→0→1→2→Input
③:5→4→0→Output
after the traversal is finished, no low child node is equal to or greater than dfn parent node, and the subtree number value of the root node 5 is 1, so that the graph has no cut point, and the graph also shows that the original circuit diagram has no short-circuit and open-circuit nodes.
In order to demonstrate the workflow of the present invention, the case of short circuit and open circuit is artificially set in this embodiment. Fig. 9 is a circuit diagram of a class b push-pull power amplifier circuit after a human set failure. As shown in fig. 9. Connecting the original nodes 2 and 4 shorts D1 and D2 and then disconnects the ground terminal of R3. At this time, the Components dictionary sets Components and node dictionary sets Nodes are as follows:
Components:{'qQ2':['5','4','0'],'qQ1':['1','4','5'],'dD2':['3','4'],'dD1':['4','3'],'vV2':['1','0'],'vV1':['Input','0'],'rR3':['output','R3_OPEN_2'],'cC3':['5',cC3'output'],'rR2':['4','0'],'rR1':['1','4'],'cC2':['Input','4'],'cC1':['Input','4']}。
Nodes:{'5':['qQ2','qQ1','cC3'],'4':['qQ2','qQ1','dD2','dD1','rR2','rR1','cC2','cC1'],'0':['qQ2','vV2','vV1','rR2'],'1':['qQ1','vV2','rR1'],'3':['dD2','dD1'],'Input':['vV1','cC2','cC1'],'output':['rR3','cC3'],'R3_OPEN_2':['rR3']}。
fig. 10 is a node tree example diagram of the circuit diagram shown in fig. 9 in the present embodiment. At this time, starting from the root node, four search paths are obtained in this embodiment:
①:5→4→0→1
②:5→4→0→Input
③:5→4→3
④:5→Output
at this time, the number child of the root node 5 is 2, and the child nodes are node 4 and node Output respectively. low input=2 is low input= dfn [4] =2 because traversing to node Input can return to nodes 4 and 0, dfn [4] < dfn [0 ]. low [3] =6 is because initially low [3] = dfn [3] =6, no path can point to another node when traversing to node 3, and thus the value of low [3] is unchanged. The value of low Output is 7. Then low 3 dfn 4 in the figure, so node 4 is a cut point and Set 4= [3], even if node 4 becomes a child node of the cut point, 3. The number child of the root node 5 is greater than 1, so the root node is also a cut point, and since low [4] = dfn [5], low [ Output ] > dfn [5], set [5] = [ Output ], i.e. the node that cannot return to the node 5 in the subtree of the node 5 is node Output.
After obtaining the cut point and the sub-node set thereof, the search path needs to be recursively restored to obtain the set of nonfunctional components. Fig. 11 is a schematic diagram of a recursive reduction search path in the present embodiment. As shown in fig. 11, the Set is traversed: the method comprises the steps of { '4': 3], '5': output ] }, firstly, finding two Components dD2 and dD1 connected with node dictionary set Nodes according to the node 3 in the node dictionary set Nodes, storing the two Components dD2 and dD1 in a result set nonfunctional component set B, then, finding the Components dD2 and dD1 in component dictionary set Components, finding back to a cut point, and stopping finding. Two Components cC3 and rR3 connected with the node dictionary set Nodes are found according to the node Output, the node dictionary set Nodes stores the node dictionary set Nodes into a non-functional component set B, the node dictionary set Nodes returns to the Components of the component dictionary set, the other node of the component cC3 is a cutting point, the searching is stopped, the other node of the component rR3 is R3-OPEN_2, and only one component rR3 is connected in the component dictionary set Nodes, so that the searching is completed. Obtaining a final result set B: { 'dD1', 'rR3', 'cC3', 'dD 2'.
Because the circuit structure is actually a black box, in practical application, it is not known whether the node 5 is a short-circuited node, so that another different node needs to be selected to be the root node to execute the algorithm again from the beginning, and the process is similar and will not be repeated here.
The invention was next applied to experimental verification in a large circuit containing 1229 components. The large-scale circuit comprises two conditions of open circuit and short circuit, and the components are two-port components such as capacitance and resistance and three-port components such as MOS (metal oxide semiconductor) tubes. The test results were as follows:
Figure BDA0004066687580000101
the test result shows that the running time of the invention is ideal, for thousands of rows of netlists, only 0.02S is used for obtaining all results from reading, 115 short-circuit and open-circuit nonfunctional components are identified, the nonfunctional components account for 9.4% of the total circuit, and the nonfunctional components are consistent with the actual results after one-to-one verification. The number of the two-end devices is 95, the number of the three-end devices is 20, and because each two-port device has two hard faults of open circuit and short circuit, each three-port device has one open circuit fault and one short circuit fault between every two ports, the total number of fault simulation is reduced by 95 multiplied by 2 multiplied by 20 multiplied by (3 multiplied by 3) multiplied by 310, and the fault simulation time of the analog circuit is quite considerable.
While the foregoing describes illustrative embodiments of the present invention to facilitate an understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, but is to be construed as protected by the accompanying claims insofar as various changes are within the spirit and scope of the present invention as defined and defined by the appended claims.

Claims (2)

1. A method for identifying nonfunctional devices in an analog circuit, comprising the steps of:
s1: extracting element information and node information of the analog circuit according to a netlist file of the analog circuit to obtain element dictionary set Components and node dictionary set Nodes, wherein keys in the element dictionary set Components are element names, values are arrays and are used for storing node names connected with the element, keys in the node dictionary set Nodes are node names, values are arrays and are used for storing element names connected with the node;
s2: traversing Components of the dictionary set of Components, comparing node names of each component, and adding the component into the short-circuit device set A when the same node names exist in a plurality of node names connected with a certain component;
s3: k nodes are selected from the nodes of the analog circuit as root nodes according to actual needs.
S4: let k=1;
s5: the cutting point in the analog circuit is identified by adopting a Tarjan algorithm based on the kth root node, and the specific method is as follows:
s5.1: based on the kth root node, the keys in the node dictionary set Nodes are used as Nodes, the keys in the component dictionary set Components are used as the connection lines between the Nodes, and the connection relation between different Nodes is determined by the mutual search of the Components and the node dictionary sets, so that a node tree is obtained k
S5.2: each node in the node tree is searched in a depth-first mode, and each node x in the node tree is obtained i The order accessed during the depth-first search is taken as node x i Time stamp dfn [ x ] of (2) i ]I=1, 2, …, N represents the number of nodes;
s5.3: according to each node x i Time stamp dfn [ x ] of (2) i ]Traversing each node, and determining each node x based on Tarjan algorithm i Is a trace-back value low x i ]The specific method comprises the following steps:
the current node is recorded as now, and a traceability value low [ now ] is initialized]=dfn[now]The subtree number child=0, and the parent node fa and all child nodes to of the node now are obtained d D=1, 2, …, D representing the number of sub-nodes of the node now, to for each sub-node d If the sub-node to d Timestamp dfn [ to ] d ]Timestamp low [ now ] less than node now]Then node to d Is an ancestor node, further judges whether to d =fa, if not, update the trace back value low [ now ] of node now]=min(low[now],dfn[to d ]) Otherwise, do nothing; if the sub-node to d Timestamp dfn [ to ] d ]Timestamp Low [ now ] greater than node now]Let child tree number child=child+1 of node now, then sub-node to d Determining its traceback value low to by using improved Tarjan algorithm d ]Then updating the traceability value low no of node noww]=min(low[now],low[to d ]);
After all nodes determine the traceability value, judging whether each node is a cut point or not in sequence, wherein the specific method comprises the following steps:
when node x i Judging whether the number of subtrees is more than or equal to 2 if the number is the root node, if so, node x i If the cutting point is the cutting point, otherwise, the cutting point is not the cutting point;
when node x i Not the root node, if node x i The trace back value of some sub-nodes in the sub-nodes of (a) is larger than the node x i Node x i As cut point, otherwise node x i Is not a cutting point;
node tree k The number of the obtained cutting points is M, and for the mth cutting point
Figure FDA0004066687570000021
i m The node sequence number of the mth cut point is represented, and the child nodes with the trace back value larger than the time stamp of the cut point in the child nodes are constructed to obtain +.>
Figure FDA0004066687570000022
Sub-node set toSet as cut point k,m M=1, 2, …, M;
s6: m cutting points obtained according to the step S5
Figure FDA0004066687570000023
Sub-node set toSet k,m Searching to obtain a nonfunctional component set B k The specific method comprises the following steps: for each cut point->
Figure FDA0004066687570000024
Optionally selecting a sub-node set toSet thereof k,m Taking one node as a sub-node to perform path searching, and ending the path searching when the searched sub-node is a cutting point or the sub-node does not exist; will be according to M cut points->
Figure FDA0004066687570000025
Sub-node set toSet k,m All the components passing through the paths obtained by searching form a tree according to the current node k The obtained nonfunctional component set B k
S7: judging whether K is less than K, if yes, entering a step S8, otherwise, entering a step S9;
s8: let k=k+1, return to step S5;
s9: obtaining a short circuit device set A and K nonfunctional element sets B k To obtain the nonfunctional component set F of the analog circuit, i.e. F=A U.B 1 ∪B 2 ∪…∪B K
2. The method for identifying non-functional devices in an analog circuit according to claim 1, wherein K root nodes in the step S3 include a ground node and a power node.
CN202310078259.7A 2023-02-08 2023-02-08 Method for identifying nonfunctional device in analog circuit Pending CN116050333A (en)

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