CN116047265A - Wafer testing system and testing method - Google Patents

Abstract

The invention discloses a wafer testing system and a testing method, wherein the wafer testing system comprises the following components: a signal source for providing a test signal; the switching circuit is provided with a first input end and N first output ends, the first input end is used for receiving a test control signal, the switching circuit is used for sequentially transmitting the test signal to the N first output ends under the control of the test control signal, and N is a positive integer greater than 1; the probe module is provided with N second input ends and N probes, the N second input ends are connected with the N first output ends in a one-to-one correspondence manner, the N probes are connected with the N second input ends in a one-to-one correspondence manner, and the N probes are used for being electrically connected with N chips on a wafer to be tested in a one-to-one correspondence manner. By using the technical scheme, the moving times of the wafer can be reduced, so that the time spent on moving the wafer is shortened, the time cost of wafer testing is reduced, and the testing efficiency of the wafer is improved.

Description

Wafer testing system and testing method

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a wafer testing system and a testing method.

Background

In order to guarantee the quality of the individual chips (die) on the wafer (wafer) and to determine possible problems in the manufacturing process, it is necessary to perform parameter measurements and functional tests on the chips before shipping in order to check the functional integrity of the chips. The test specification used in the test procedure will vary with the purpose of the test.

However, the wafer testing method in the prior art takes a long test time, resulting in lower test efficiency.

Disclosure of Invention

The invention solves the technical problem of improving the testing efficiency of the wafer.

In order to solve the above technical problems, the present invention provides a wafer testing system, which includes: a signal source for providing a test signal; the switching circuit is provided with a first input end and N first output ends, the first input end is used for receiving a test control signal, the switching circuit is used for sequentially transmitting the test signal to the N first output ends under the control of the test control signal, and N is a positive integer greater than 1; the probe module is provided with N second input ends and N probes, the N second input ends are connected with the N first output ends in a one-to-one correspondence manner, the N probes are connected with the N second input ends in a one-to-one correspondence manner, and the N probes are used for being electrically connected with N chips on a wafer to be tested in a one-to-one correspondence manner.

Optionally, the arrangement of the N probes is adapted to the arrangement of the N wafers.

Optionally, the N probes are arranged in an array or in a straight line.

Optionally, the wafer test system further comprises: the wafer carrier is used for carrying the wafer to be tested; and the driving module is used for driving the wafer carrier to move.

Optionally, the arrangement length of the N chips in the test travelling direction is a first distance, and the distance that the driving module drives the wafer carrier to move in the test travelling direction each time is equal to the first distance.

Optionally, the probe module includes M probe cards, each probe card having N/M second input terminals and N/M probes, where n=2 ⁱ ，M＝2 ^j I, j are positive integers and i>j。

Optionally, the switching circuit includes: the first switching unit comprises a third input end and M third output ends, wherein the third input end is connected with the first input end, and the first switching unit is used for sequentially transmitting the test signals to the M third output ends under the control of the test control signals.

Optionally, the switching circuit further includes: the M second switching units comprise fourth input ends and N/M fourth output ends, the fourth input ends are connected with the corresponding third output ends, the fourth output ends are connected with the corresponding first output ends, and each second switching unit is used for sequentially transmitting the test signals to the N/M fourth output ends under the control of the test control signals.

Optionally, the wafer test system further comprises: and the control host is used for providing the test control signal and controlling the signal source to provide the test signal for the switching circuit.

Optionally, the wafer is a laser wafer.

The invention also discloses a testing method based on the wafer testing system, which comprises the following steps: providing a wafer to be tested, and electrically connecting the N probes with N chips on the wafer to be tested in a one-to-one correspondence manner; controlling the signal source to provide the test signal; and controlling the switching circuit to sequentially transmit the test signals to N second input ends of the probe module.

Optionally, after the probe module finishes testing the N chips, the wafer to be tested is controlled to move a first distance in a test running direction, where the first distance is an arrangement length of the N chips in the test running direction.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

the invention provides a wafer test system, which comprises a signal source for providing a test signal; the switching circuit is used for sequentially transmitting the test signals to the N first output ends under the control of the test control signals; the probe module is provided with N second input ends and N probes, the N second input ends are connected with the N first output ends in a one-to-one correspondence mode, the N probes are connected with the N second input ends in a one-to-one correspondence mode, and the N probes are used for being electrically connected with the N chips on the wafer to be tested in a one-to-one correspondence mode. According to the technical scheme, the switching circuit is arranged between the signal source and the probes, and the plurality of probes which are electrically connected with the chips one by one are arranged on the wafer, so that the test signals provided by the signal source can be sequentially transmitted to the plurality of probes by using the switching circuit. After the current chip is tested, the next chip can be tested by controlling the switching circuit to input a test signal into the next probe of the probe module, namely, the test of N chips can be finished by moving the wafer each time, the test speed of each chip in the wafer is greatly improved, the time cost of the wafer test is reduced, and the test efficiency of the wafer test is improved.

Further, the probe module may include a plurality of probe cards, and the switching circuit may include a first switching unit and a plurality of second switching units, the second switching units being connected to the probe cards. By disposing a plurality of probe cards, a first switching unit and a plurality of second switching units, signals can be input into different probe cards by controlling the switching circuit, so that wafers corresponding to different probe cards can be tested. Under the condition that the number of probes of a single probe card is limited, the number of probes participating in the test can be further increased by adopting the scheme, so that the moving times of the wafer are reduced, and the test efficiency of the wafer test is improved.

Drawings

FIG. 1 is a schematic diagram of a wafer test system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another wafer test system according to an embodiment of the present invention;

FIG. 3 is a block diagram of a wafer test system according to an embodiment of the present invention;

FIG. 4 is a flow chart of a testing method based on a wafer testing system according to an embodiment of the present invention;

fig. 5 is a schematic view of a usage scenario of a wafer testing system according to an embodiment of the present invention.

Detailed Description

As described in the background, the efficiency of the wafer test method is to be improved.

The inventors of the present application have noted that the main reason for the inefficiency of the testing method is that the dies on the wafer are often tested alone, requiring that the wafer be moved after the current die test is completed and the next die be tested using the probes. Each die requires moving the wafer after testing, which takes additional time, resulting in long wafer testing time and low testing efficiency. Since the signal sources used for Laser testing have high cost, the deployment of multiple signal sources will increase the production cost, and thus when the product on the wafer is a Laser, such as a Vertical-Cavity Surface-Emitting Laser (VCSEL), only a single signal source is typically deployed for wafer testing, and the problem of testing efficiency is particularly pronounced.

In the invention, the wafer test system comprises a signal source for providing a test signal; the switching circuit is used for sequentially transmitting the test signals to the N first output ends under the control of the test control signals; the probe module is provided with N second input ends and N probes, the N second input ends are connected with the N first output ends in a one-to-one correspondence mode, the N probes are connected with the N second input ends in a one-to-one correspondence mode, and the N probes are used for being electrically connected with the N chips on the wafer to be tested in a one-to-one correspondence mode. According to the technical scheme, the switching circuit is arranged between the signal source and the probes, and the plurality of probes which are electrically connected with the chips one by one are arranged on the wafer, so that the test signals provided by the signal source can be sequentially transmitted to the plurality of probes by using the switching circuit. After the current chip is tested, the next chip can be tested by controlling the switching circuit to input a test signal into the next probe of the probe module, namely, the test of N chips can be finished by moving the wafer each time, the test speed of each chip in the wafer is greatly improved, the time cost of the wafer test is reduced, and the test efficiency of the wafer test is improved.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Fig. 1 is a schematic structural diagram of a wafer testing system according to an embodiment of the present invention.

As shown in fig. 1, the wafer test system includes a switching circuit 10, a probe module 20, and a signal source 30.

The switching circuit 10 has a first input terminal O and N first output terminals, for example, a first output terminal a1, a first output terminal b1, and a first output terminal c1. The first input terminal O is configured to receive a test control signal and a test signal provided by the signal source 30. The switching circuit 10 is configured to sequentially transmit the test signals to N first output terminals under the control of the test control signals, where N is a positive integer greater than 1. For example, the test signal is sequentially transmitted to the first output terminal a1, the first output terminal b1, and the first output terminal c1.

In a specific embodiment, a switching path is provided between the first input terminal O and each first output terminal, and when the switching path is turned on, a test signal may be output from the first input terminal O to the first output terminal corresponding to the turned-on switching path. For example, the switching circuit 10 further has a first switch s2 and a second switch s3, respectively, with a first switch s1 between the first input terminal O and the first output terminal a1. The test control signal can control the first switch s1 to be turned on, and control the first switch s2 and the second switch s3 to be turned off, so that the test signal is input into the first output end a1 from the first input end O.

In the present embodiment, in the switching circuit 10, only one switching path is turned on at a time, that is, the first input terminal O transmits the test signal to only one first output terminal at a time.

In other embodiments, in the switching circuit 10, a plurality of switch paths may be turned on at the same time, that is, the first input terminal O transmits the test signal to a plurality of first output terminals at a time, and the number of turned-on switch paths is less than or equal to N. The on and off of the switching paths in the switching circuit 10 may be determined according to actual conditions, which is not limited in the present application.

The probe module 20 has N second input terminals and N probes, for example, a second input terminal a2, a second input terminal b2, and a second input terminal c2; probe a, probe B and probe C. The N second input ends are connected in one-to-one correspondence with the N first output ends, one end of the N probes is connected in one-to-one correspondence with the N second input ends, and the other end of the N probes is electrically connected in one-to-one correspondence with the N dies on the wafer 110 to be tested, for example, the first output ends a1, B1, C1 are respectively connected in one-to-one correspondence with the second input ends a2, B2, C2, and the second input ends a2, B2, C2 are respectively connected in one-to-one correspondence with the probe a, the probe B, and the probe C. In particular, the probes may be contacted with contacts on the wafer to make electrical connection.

In the present embodiment, the die on the wafer 110 to be tested is a laser die. In particular, the laser wafer may be a vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser, VCSEL).

In a specific embodiment, after the signal source 30 inputs the test signal to the first input terminal O, the first switch s1 between the first input terminal O and the first output terminal a1 may be controlled to be turned on. At this time, the first switch s2 between the first input terminal O and the first output terminal b1 is turned off, and the first switch s3 between the first input terminal O and the first output terminal c1 is turned off. The test signal is input from the first input terminal O to the first output terminal a1 and is input to the probe a via the second input terminal a2 of the probe module, and the probe a can test the wafer to which it is electrically connected with the test signal.

Further, after the probe a finishes testing the corresponding wafer, the first switch s1 is turned off, the first switch s2 is turned on, a test signal is transmitted from the first input end O to the first output end B1, and the probe B is input through the second input end B2 of the probe module, so that the probe B can test the wafer electrically connected with the probe B by using the test signal. Accordingly, after the probe B completes the test on the corresponding wafer, the first switch s2 is turned off, and the first switch s3 is turned on, so that the probe C can test the wafer electrically connected with the probe C by using the test signal.

The signal source 30 is used for providing a test signal to the first input terminal O.

In one non-limiting embodiment, the N probes may belong to the same probe card, with the N probes being adapted to the arrangement of the N wafers to which they are correspondingly electrically connected. Specifically, the N probes and the N wafers corresponding thereto are arranged at the same positions, and the spacing distance between the adjacent probes is identical to the spacing distance between the adjacent wafers corresponding to the adjacent probes. Through setting up the arrangement looks adaptation of N probes and N wafer, can make each probe all can be accurately with its corresponding wafer electricity connection to guarantee that each probe can transmit test signal to in the wafer.

In a specific embodiment, the N probes may be arranged in a straight line, i.e. the arrangement of the N probes is 1*N or n×1; the N probes may also be arranged in an array, i.e. the N probes are arranged in X Y or Y X, X y=n, and X and Y are positive integers greater than 1.

In this embodiment, by controlling the on/off of each switch path in the switching circuit 10, the test signals can be sequentially transmitted to each first output end, and the test signals can be respectively provided to the plurality of probes via the second input end, so as to ensure that the plurality of probes test the corresponding wafers one by one. The test signals can be switched to control different probes to finish the test on the corresponding chips, the wafer does not need to be moved after each chip is tested, the test time can be shortened, and the test efficiency is greatly improved.

Fig. 2 is a schematic structural diagram of another wafer testing system according to an embodiment of the present invention.

Unlike the wafer test system shown in fig. 1, the probe module in fig. 2 includes M probe cards, each having N/M second inputs and N/M probes, for example, second input v1, second input v2, second input v3, and second input v4; probes A ', B', C 'and D'. N=2 ⁱ ，M＝2 ^j I, j are positive integers and i>j, the scheme shown in FIG. 2 is a non-limiting example, N being4, M is 2.

In a specific embodiment, the switching circuit includes a first switching unit 101 and M second switching units 102. The first switching unit 101 includes a third input terminal O1 and M third output terminals, for example, a third output terminal x1 and a third output terminal y1. The third input terminal O is connected to the first input terminal O. The first switching unit 101 is configured to sequentially transmit the test signals transmitted from the signal source 30 to the third input terminal O1 via the first input terminal O to the M third output terminals under the control of the test control signal.

The second switching units 102 comprise a fourth input and N/M fourth outputs, for example, one of the second switching units 102 has a fourth input x2, a fourth output z1 and a fourth output z2, and the other second switching unit 102 has a fourth input y2, a fourth output z3 and a fourth output z4. Each fourth input end is connected with the corresponding third output end, and each fourth output end is connected with the corresponding first output end. The second switching unit 102 is configured to sequentially transmit the test signals to the N/M fourth output terminals under the control of the test control signal.

In a specific embodiment, a switching path is provided between the third input terminal O1 and each third output terminal, and when the switching path is turned on, a test signal may be output from the third input terminal O1 to the third output terminal corresponding to the turned-on switching path.

Further, a switching path is also provided between the fourth input terminal and each fourth output terminal, and when the switching path is turned on, the test signal may be output from the fourth input terminal to the fourth output terminal corresponding to the turned-on switching path.

In the present embodiment, in the first switching unit 101, only one switching path is turned on at a time, that is, the third input terminal O1 transmits the test signal to only one third output terminal at a time. In the second switching unit 102, only one switching path is turned on at a time, i.e. the fourth input terminal transmits the test signal to only one fourth output terminal at a time.

In other embodiments, in the first switching unit 101 and the second switching unit 102, a plurality of switch paths may be turned on at the same time, that is, the third input terminal O1 may transmit the test signal to a plurality of third output terminals at a time, and the number of turned-on switch paths is less than or equal to M; the fourth input end can transmit test signals to a plurality of fourth output ends at a time, and the number of the conducted switch paths is less than or equal to N/M. The on and off of the switching paths in the first switching unit 101 and the second switching unit 102 may be determined according to actual conditions, which is not limited in the present application.

In a specific embodiment, the second switch s '1 and the third switch s "1 are controlled to be turned on, and the other switch paths are controlled to be turned off, and the test signal is transmitted from the third input terminal O1 to the third output terminal x1, and is transmitted to the fourth output terminal z1 through the fourth input terminal x2, and finally the test signal is provided to the probe a' through the second input terminal v 1; after the probe a 'completes the test, the third switch s "1 is controlled to be turned off, and the third switch s"2 is controlled to be turned on, and a control signal is transmitted from the fourth output terminal z2 to the second input terminal v2, and a test signal is provided to the probe B'.

Further, after the probe cards to which the probes a ' and B ' belong complete the test, the second switch s '1 is controlled to be turned off, the second switch s '2 and the third switch s "3 are controlled to be turned on, the test signal is transmitted from the third input end O1 to the third output end y1, and is transmitted to the fourth output end z3 through the fourth input end y2, and finally the test signal is provided to the probe C ' through the second input end v 3; after the probe C 'completes the test, the third switch s "3" is controlled to be turned off, and the third switch s "4" is controlled to be turned on, and the control signal is transmitted from the fourth output terminal z4 to the second input terminal v4, and the test signal is provided to the probe D'.

In particular embodiments, the number of probes on each probe card may be the same. Each probe card has N/M probes, and the M probe cards have N probes in total. Wherein n=2 ⁱ ，M＝2 ^j I, j are positive integers and i>j to be equally distributed for the number of probes on each probe card. For example, the probe module has 2 probe cards and 8 probes in total, and the first probe card and the second probe card have 4 probes, respectively.

Alternatively, the number of probes on each probe card may be different. For example, the probe module has a total of 2 probe cards and 8 probes, the first probe card may have 2 probes, and the second probe card may have 6 probes.

It should be noted that the number of probes on the probe card may be selected according to practical situations, which is not limited in this application.

In this embodiment, by providing a plurality of probe cards in the probe module, wafer testing can be performed using the plurality of probe cards. Under the condition that the number of probes of a single probe card is limited, the number of probes can be further increased, the moving times of the wafer are reduced, and the testing efficiency of the wafer test is improved. And through setting up first switching unit and second switching unit, can control the transmission of test signal under the condition that the probe module has a plurality of probe cards, transmit test signal to different probe cards in proper order to test the wafer that different probe cards correspond.

Fig. 3 is a block diagram of a wafer testing system according to an embodiment of the present invention.

The wafer test system includes a switching circuit 10, a probe module 20, a signal source 30, a wafer stage 40, a driving module 50, and a control host 60.

The wafer carrier 40 is used for carrying a wafer to be tested; the driving module 50 is used for driving the wafer carrier 40 to move; the control host 60 is used for providing a test control signal, and the control signal source 30 provides the test signal to the switching circuit 10.

In a specific embodiment, the control host 60 may also be used to control the driving module 50 to drive the wafer stage 40 to move.

Referring now to fig. 4 for describing a testing process of the wafer testing system, fig. 4 is a flowchart of a testing method based on the wafer testing system according to an embodiment of the present invention.

In practice, the test methods described in steps 401 to 403 below may be used in a wafer test system.

Specifically, as shown in fig. 4, the testing method based on the wafer testing system may include the following steps:

in step 401, a wafer to be tested is provided, and the N probes are electrically connected with N chips on the wafer to be tested in a one-to-one correspondence manner;

in step 402, controlling the signal source to provide the test signal;

in step 403, the switching circuit is controlled to sequentially transmit the test signals to N second input terminals of the probe module.

In the embodiment of step 401, the wafer to be tested is placed on the wafer stage 40, and N probes in the probe module 20 are electrically connected to N dies on the wafer to be tested in a one-to-one correspondence manner, so that the probes can transmit the test signals to the dies.

In the embodiment of step 402, the control host 60 controls the signal source 30 to provide the test signal to the switching circuit 10.

In a specific embodiment of step 403, the control host 60 controls the switching circuit 10 to sequentially transmit the test signals to the N second input terminals of the probe module 20, so as to control the probe to test the corresponding wafer.

In one non-limiting embodiment, after the probe module 20 completes testing N dies, the control host 60 controls the driving module 50 to drive the wafer carrier 40 to move a first distance in the testing traveling direction, so as to test other dies on the wafer to be tested by using the probe module 20, where the first distance is an arrangement length of outer contours of the N dies in the testing traveling direction.

Referring specifically to fig. 5, the probe module 20 has two probes, two wafers at a time can be tested. After the probe module 20 finishes testing the die P1 and the die P2 on the wafer 110 to be tested, the wafer 110 to be tested can be moved by taking the x-axis direction as the test traveling direction, and at this time, the first distance moved by the wafer stage 40 is the distance L1 from the center point of the die P1 to the center point of the die P3; alternatively, the y-axis direction may be used as the test traveling direction, and the first distance traveled by the wafer stage 40 is the distance L2 from the center point of the wafer P1 to the center point of the wafer P5 (i.e., the distance from the center point of the wafer P4 to the center point of the wafer P8). After each movement, the current die is tested until all dies on the wafer 110 to be tested have been tested.

In a preferred embodiment, the movement of the wafer 110 to be tested may include a plurality of movement periods, each movement period including: after the test of the first group of wafers is completed, moving along a first direction and testing the second group of wafers; then moving along a second direction and testing a third group of wafers, wherein the second direction is perpendicular to the first direction; then moving in the opposite direction of the first direction and testing the fourth group of wafers; and then moves in a first direction. That is, the moving path of the probe module 20 on the wafer 110 to be tested is S-shaped. For example, the test sequence of the probe modules 20 may be: first, a wafer P1 and a wafer P2; a second step, wafer P5 and wafer P6; third, wafer P7 and wafer P8; fourth, wafer P3 and wafer P4. Since the wafers in the wafer are generally close to each other due to problems caused by special conditions (such as wafer contamination caused by dust), the wafer carrier 40 can more quickly find the wafers with problems and close positions by using the square wave-shaped moving path, so as to determine and solve the problems of the wafers as soon as possible, and improve the efficiency of wafer testing.

Further, the testing process for the wafer includes a preliminary test in which test items are set for a wafer that is defect-free and a further test in which test items are set for a wafer that is defect-free. If the current wafer reaches the test standard in the preliminary test, the next wafer is tested, otherwise, the current wafer is further tested to judge which grade of defective wafer the current wafer belongs to. Correspondingly, the embodiment also provides a method for testing the wafer: after each movement of the wafer to be tested, if one of the dies fails the preliminary test and further tests are used, the subsequent die directly performs the further tests without performing the preliminary tests until the test result of the further tests of the dies is optimal (i.e., belongs to the best class among the defective dies), and then resumes the preliminary tests. The method can save the time of repeated testing when a plurality of chips with problems appear in the same range, reduce the time cost of wafer testing and improve the efficiency of wafer testing.

With respect to each of the apparatuses and each of the modules/units included in the products described in the above embodiments, it may be a software module/unit, a hardware module/unit, or a software module/unit, and a hardware module/unit. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the rest (if any) of the modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented by using hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, or the like) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program, where the software program runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules/units may be implemented by using hardware such as a circuit.

The term "plurality" as used in the embodiments herein refers to two or more.

The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order division is used, nor does it indicate that the number of the devices in the embodiments of the present application is particularly limited, and no limitation on the embodiments of the present application should be construed.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present application are all or partially produced. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more sets of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus, and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may be physically included separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A wafer testing system, comprising:

a signal source for providing a test signal;

the switching circuit is provided with a first input end and N first output ends, the first input end is used for receiving a test control signal, the switching circuit is used for sequentially transmitting the test signal to the N first output ends under the control of the test control signal, and N is a positive integer greater than 1;

the probe module is provided with N second input ends and N probes, the N second input ends are connected with the N first output ends in a one-to-one correspondence manner, the N probes are connected with the N second input ends in a one-to-one correspondence manner, and the N probes are used for being electrically connected with N chips on a wafer to be tested in a one-to-one correspondence manner.

2. The wafer test system of claim 1, wherein the arrangement of the N probes is adapted to the arrangement of the N dies.

3. The wafer test system of claim 1, wherein the N probes are arranged in an array or a straight line.

4. The wafer testing system of claim 1, further comprising:

the wafer carrier is used for carrying the wafer to be tested;

and the driving module is used for driving the wafer carrier to move.

5. The wafer test system of claim 4, wherein,

the arrangement length of the N wafers in the test travelling direction is a first distance, and the distance that the driving module drives the wafer carrier to move in the test travelling direction each time is equal to the first distance.

6. The wafer test system of claim 1, wherein the probe module comprises M probe cards, each probe card having N/M second inputs and N/M probes, wherein N = 2 ⁱ ，M＝2 ^j I, j are positive integers and i>j。

7. The wafer test system of claim 6, wherein the switching circuit comprises: the first switching unit comprises a third input end and M third output ends, wherein the third input end is connected with the first input end, and the first switching unit is used for sequentially transmitting the test signals to the M third output ends under the control of the test control signals.

8. The wafer test system of claim 7, wherein the switching circuit further comprises:

the M second switching units comprise fourth input ends and N/M fourth output ends, the fourth input ends are connected with the corresponding third output ends, the fourth output ends are connected with the corresponding first output ends, and each second switching unit is used for sequentially transmitting the test signals to the N/M fourth output ends under the control of the test control signals.

9. The wafer testing system of claim 1, further comprising:

and the control host is used for providing the test control signal and controlling the signal source to provide the test signal for the switching circuit.

10. The wafer testing system of claim 1, wherein the die is a laser die.

11. A testing method based on the wafer testing system according to any one of claims 1 to 10, comprising:

providing a wafer to be tested, and electrically connecting the N probes with N chips on the wafer to be tested in a one-to-one correspondence manner;

controlling the signal source to provide the test signal;

and controlling the switching circuit to sequentially transmit the test signals to N second input ends of the probe module.

12. The method of testing a wafer test system of claim 11, further comprising:

after the probe module finishes testing the N chips, controlling the wafer to be tested to move a first distance in the testing travelling direction, wherein the first distance is the arrangement length of the N chips in the testing travelling direction.

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