CN116033783A - Display substrate, preparation method thereof and display device - Google Patents

Abstract

A display substrate, a manufacturing method thereof and a display device. The display substrate includes: the light-emitting device comprises a substrate, a light-emitting structure layer arranged on the substrate and a light treatment layer arranged on one side of the light-emitting structure layer far away from the substrate; the light-emitting structure layer comprises a plurality of light-emitting areas, the light-emitting areas comprise a first light-emitting area and a second light-emitting area, and the brightness of the first light-emitting area is smaller than that of the second light-emitting area; the light treatment layer comprises a first light treatment layer, which is positioned on the light emitting side of the first light emitting subarea and is configured to improve the light emitting efficiency of the first light emitting subarea.

Description

Display substrate, preparation method thereof and display device

Technical Field

The embodiment of the disclosure relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

Background

The organic light emitting diode (Organic Light Emitting Diode, OLED) display screen has the advantages of wide color gamut, high resolution, capability of controlling each pixel independently and the like, and the occupancy rate is higher and higher in the terminal market. Compared with the traditional evaporation technology, the technology for preparing the organic light-emitting diode by adopting the ink-jet printing has the advantages of high material utilization rate and low product manufacturing cost, and has been widely applied.

The inventor of the application researches and discovers that the display substrate prepared by adopting the ink-jet printing technology has the problem of uneven luminescence.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a display substrate, a preparation method thereof and a display device, and aims to solve the problem of uneven light emission of the display substrate prepared by adopting an ink-jet printing technology.

In a first aspect, an embodiment of the present disclosure provides a display substrate, including: the light-emitting device comprises a substrate, a light-emitting structure layer arranged on the substrate and a light treatment layer arranged on one side of the light-emitting structure layer away from the substrate; the light-emitting structure layer comprises a plurality of light-emitting areas, wherein the light-emitting areas comprise a first light-emitting sub-area and a second light-emitting sub-area, and the brightness of the first light-emitting sub-area is smaller than that of the second light-emitting sub-area; the light treatment layer comprises a first light treatment layer, which is positioned at the light emitting side of the first light emitting sub-region and is configured to improve the light emitting efficiency of the first light emitting sub-region.

In an exemplary embodiment, the light treatment layer further comprises a second light treatment layer, which is located at the light emitting side of the second light emitting sub-region and configured to increase the light emitting efficiency of the second light emitting sub-region; the effect of the second light treatment layer for improving the light-emitting efficiency is smaller than that of the first light treatment layer for improving the light-emitting efficiency.

In an exemplary embodiment, the first light management layer includes a plurality of first lens structures, and orthographic projections of the plurality of first lens structures on the substrate at least partially overlap orthographic projections of the first light emitting sub-regions on the substrate.

In an exemplary embodiment, the second light treatment layer comprises a plurality of second lens structures, the orthographic projections of the plurality of second lens structures on the substrate at least partially overlapping with the orthographic projections of the second light emitting sub-regions on the substrate.

In an exemplary embodiment, a ratio of an area of orthographic projection of the plurality of first lens structures on the substrate to an area of orthographic projection of the first light-emitting sub-region on the substrate is a first filling rate; the ratio of the orthographic projection area of the plurality of second lens structures on the substrate to the orthographic projection area of the second luminous subarea on the substrate is a second filling rate; the first filling rate is greater than the second filling rate.

In an exemplary embodiment, the first filling rate is greater than or equal to 40% and the second filling rate is less than or equal to 30%.

In an exemplary embodiment, the refractive index of the first lens structure is greater than the refractive index of the second lens structure.

In an exemplary embodiment, the first lens structure has a semicircular cross-sectional shape in a plane perpendicular to the substrate, and the second lens structure has a cross-sectional shape different from the first lens structure.

In an exemplary embodiment, the first light treatment layer and the second light treatment layer are arranged in the same layer.

In an exemplary embodiment, the second lens structure has a larger particle size than the first lens structure.

In an exemplary embodiment, the display substrate includes an encapsulation layer, the encapsulation layer is located on a side of the light emitting structure layer away from the substrate, and the light treatment layer is located on a side of the encapsulation layer away from the substrate.

In a second aspect, embodiments of the present disclosure provide a display device including a display substrate as described above.

In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a display substrate, including: forming a light emitting structure layer on a substrate, the light emitting structure layer comprising a plurality of light emitting regions, the light emitting regions comprising a first light emitting sub-region and a second light emitting sub-region, the first light emitting sub-region having a brightness less than the second light emitting sub-region; forming a light treatment layer on one side of the light emitting structure layer away from the substrate; the light treatment layer comprises a first light treatment layer, which is positioned at the light emitting side of the first light emitting sub-region and is configured to improve the light emitting efficiency of the first light emitting sub-region.

In an exemplary embodiment, the light emitting structure layer includes an organic light emitting layer, the organic light emitting layer is formed by adopting an inkjet printing mode, and the morphology of the film formed by printing the organic light emitting layer is recorded; the light treatment layer further comprises a second light treatment layer, the second light treatment layer is positioned on the light emergent side of the second light-emitting subarea and is configured to improve the light emergent efficiency of the second light-emitting subarea; the forming a light treatment layer on the side of the light emitting structure layer away from the substrate comprises the following steps: determining the first light-emitting subarea and the second light-emitting subarea according to the shape of the organic light-emitting layer printed film, forming a first light treatment layer on the light-emitting side of the first light-emitting subarea, and forming a second light treatment layer on the light-emitting side of the second light-emitting subarea.

In an exemplary embodiment, the light treatment layer further comprises a second light treatment layer, which is located at the light emitting side of the second light emitting sub-region and configured to increase the light emitting efficiency of the second light emitting sub-region; the forming a light treatment layer on the side of the light emitting structure layer away from the substrate comprises the following steps: and determining the first light-emitting subarea and the second light-emitting subarea according to the light-emitting condition of the light-emitting area, forming a first light treatment layer on the light-emitting side of the first light-emitting subarea, and forming a second light treatment layer on the light-emitting side of the second light-emitting subarea.

According to the display substrate provided by the embodiment of the disclosure, the first light treatment layer is arranged on the light emitting side of the first light emitting sub-region with darker brightness, so that the light extraction effect and the light emitting efficiency of the first light emitting sub-region are improved by utilizing the first light treatment layer, the brightness of the first light emitting sub-region with darker brightness is further improved, and the brightness level of the first light emitting sub-region is equivalent to that of the second light emitting sub-region. The problem of uneven luminescence of the display substrate prepared by adopting the ink-jet printing technology is solved.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the disclosed embodiments.

FIG. 1 is a schematic diagram of an electronic device;

FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 3 is a schematic plan view of a display substrate according to the present disclosure;

FIG. 4 is a schematic front projection of a single light emitting region and lens structure on a substrate in an exemplary embodiment;

FIG. 5 is a schematic front projection of a single light emitting region and lens structure onto a substrate in yet another exemplary embodiment;

Fig. 6 is a schematic cross-sectional view of a substrate in an exemplary embodiment.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

The scale of the drawings in this disclosure may be referred to in the actual process, but is not limited thereto. For example: the width-to-length ratio of the channel, the thickness and the spacing of each film layer, and the width and the spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings, the drawings described in the present disclosure are only schematic structural drawings, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged, and "source terminal" and "drain terminal" may be exchanged.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit an electric signal between the connected constituent elements. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The triangle, rectangle, trapezoid, pentagon or hexagon, etc. in this specification are not strictly defined, but may be approximated to triangle, rectangle, trapezoid, pentagon or hexagon, etc., and there may be some small deformation due to tolerance, and there may be lead angles, arc edges, deformation, etc.

The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

Fig. 1 is a schematic structural diagram of an electronic device. As shown in fig. 1, the electronic device may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn), the scan driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include a pixel driving circuit connected to the scan signal line, the data signal line and the light emitting signal line. In an exemplary embodiment, the timing controller may provide gray values and control signals suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate the data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray values and the control signals received from the timing controller. For example, the data driver may sample the gray value using a clock signal, and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may generate the scan signal in such a manner that the scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, and m may be a natural number. The light emitting driver may generate the emission signals to be supplied to the light emitting signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission driver may sequentially supply the emission signal having the off-level pulse to the light emission signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, o may be a natural number.

Fig. 2 is an equivalent circuit schematic diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, or 7T1C structure. As shown in fig. 2, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit includes a data signal terminal D, a first scan signal terminal S1, a second scan signal terminal S2, a light emitting signal terminal E, an initial signal terminal INIT, a first power supply terminal VDD, and a second power supply terminal VSS, each of which is connected to a corresponding signal line or power supply line, respectively.

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, the second node N2 is connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the first power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, i.e., a second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the turn-on level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

The control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 with the second electrode.

The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines an amount of driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between a control electrode and the first electrode thereof.

The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal terminal D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When the on-level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 emit light by forming a driving current path between the first power line VDD and the second power line VSS.

The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scanning signal is applied to the second scanning signal line S2, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light emitting device to initialize or release the amount of charge accumulated in the first electrode of the light emitting device.

In an exemplary embodiment, the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or may be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously supplied high level signal. The first scanning signal end S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal end S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal end S1 is S (n), the second scanning signal end S2 is S (n-1), the second scanning signal end S2 of the display line and the first scanning signal end S1 in the pixel driving circuit of the previous display line are the same signal line, so that signal lines of the display panel can be reduced, and a narrow frame of the display panel can be realized.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include a P-type transistor and an N-type transistor.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the Oxide thin film transistor adopts an Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charge and the like, the oxide thin film transistor has the advantages of low leakage current and the like, the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor are integrated on one display substrate to form a low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) display substrate, the advantages of the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In an exemplary embodiment, taking an example that 7 transistors in the pixel driving circuit shown in fig. 2 are P-type transistors, the operation of the pixel driving circuit may include:

the first phase A1, referred to as a reset phase, signals of the second scanning signal line S2 are low-level signals, and signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scan signal terminal S2 is a low level signal, so that the first transistor T1 is turned on, the signal of the initial signal terminal INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The signals of the first scanning signal terminal S1 and the light emitting signal terminal E are high level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light at this stage.

The second phase A2, called a data writing phase or a threshold compensation phase, the signal of the first scanning signal terminal S1 is a low level signal, the signals of the second scanning signal terminal S2 and the light emitting signal terminal E are high level signals, and the data signal terminal D outputs a data voltage. At this stage, since the second terminal of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scan signal terminal S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on such that the data voltage output from the data signal terminal D is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and a difference between the data voltage output from the data signal terminal D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second terminal (second node N2) of the storage capacitor C is vd—vth|, vd is the data voltage output from the data signal terminal D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal terminal INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, empty the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal at the second scan signal terminal S2 is a high level signal, so that the first transistor T1 is turned off. The signal of the light emitting signal terminal E is a high level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off.

The third stage A3 is called a light emitting stage, the signal of the light emitting signal terminal E is a low level signal, and the signals of the first scanning signal terminal S1 and the second scanning signal terminal S2 are high level signals. The signal of the light emitting signal terminal E is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage outputted from the first power terminal VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, thereby driving the OLED to emit light.

During driving of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is vd—|vth|, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth) ² ＝K*[(Vdd-Vd+|Vth|)-Vth] ² ＝K*(Vdd-Vd) ²

where I is a driving current flowing through the third transistor T3, that is, a driving current for driving the OLED, K is a constant, vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, vth is a threshold voltage of the third transistor T3, vd is a data voltage outputted from the data signal terminal D, and Vdd is a power voltage received from the first power line 81 by the first power terminal Vdd.

Fig. 3 is a schematic plan view of a display substrate. As shown in fig. 3, the display substrate may include a plurality of pixel units P regularly arranged, at least one pixel unit P of the plurality of pixel units P may include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color, each sub-pixel may include a circuit unit and a light emitting device, the circuit unit may include a pixel driving circuit, and a scan signal line, a data signal line, a light emitting signal line, and the like connected to the pixel driving circuit, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line and output a corresponding current to the light emitting device under control of the scan signal line and the light emitting signal line. The light emitting devices in each sub-pixel are respectively connected with the pixel driving circuits of the sub-pixels, and the light emitting devices are configured to emit light with corresponding brightness in response to the current output by the pixel driving circuits of the sub-pixels.

In an exemplary embodiment, the pixel unit P may include red (R), green (G) and blue (B) sub-pixels therein, or may include red, green, blue and white sub-pixels therein, which are not limited herein. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagonal, or hexagonal. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or delta manner, and when the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel or Square (Square) manner, which is not limited herein.

The Ink Jet Printing (IJP) technology has the advantages of high material utilization rate, low cost and the like, and becomes a key technology for mass production of large-size OLEDs in the future. The printing modes include side by side (sbs) and line-bank. The traditional sbs printing mode has the phenomenon of coffee ring, so that the uniformity of film formation in pixels is poor, and the line-bank printing mode improves the uniformity of film formation in pixels, but the uniformity of film formation of pixels positioned at the edge of a display substrate is still poor, and the problem of film formation uniformity cannot be thoroughly solved. In addition, the inkjet printing technology also has a problem of uneven joints (swath mura) at the printing intersections, and these problems all cause uneven light emission of the display substrate.

According to the research of the inventor, when ink-jet printing is performed, after printing liquid drops are dripped into corresponding sub-pixels on a display substrate, the solvent near the edge positions of the sub-pixels volatilizes faster, and the solute is driven to move, so that finally, film forming at the edge positions of the sub-pixels is thicker, and the uneven film forming thickness is a root cause of uneven luminescence of the display substrate.

The embodiment of the disclosure provides a display substrate, comprising: the light-emitting device comprises a substrate, a light-emitting structure layer arranged on the substrate and a light treatment layer arranged on one side of the light-emitting structure layer away from the substrate; the light-emitting structure layer comprises a plurality of light-emitting areas, wherein the light-emitting areas comprise a first light-emitting sub-area and a second light-emitting sub-area, and the brightness of the first light-emitting sub-area is smaller than that of the second light-emitting sub-area; the light treatment layer comprises a first light treatment layer, which is positioned at the light emitting side of the first light emitting sub-region and is configured to improve the light emitting efficiency of the first light emitting sub-region.

According to the display substrate provided by the embodiment of the disclosure, the first light treatment layer is arranged on the light emitting side of the first light emitting sub-zone with darker brightness, the light extraction effect and the light emitting efficiency of the first light emitting sub-zone are improved by using the first light treatment layer, and the brightness of the first light emitting sub-zone which is darker originally is further improved, so that the brightness levels of the first light emitting sub-zone and the second light emitting sub-zone are equivalent, and the problem of uneven light emission of the display substrate is solved.

In an exemplary embodiment, the first light treatment layer may use an existing efficiency enhancement structure to enhance the light extraction effect of the first light emitting sub-region, and the present disclosure is not limited to the structure of the first light treatment layer.

In an exemplary embodiment, the light emitting structure layer includes a pixel defining layer including a plurality of pixel openings, the pixel openings forming the light emitting region.

In an exemplary embodiment, the light treatment layer further includes a second light treatment layer, where the second light treatment layer is located on a light emitting side of the second light emitting sub-area and configured to increase light emitting efficiency of the second light emitting sub-area, and an effect of the second light treatment layer for increasing light emitting efficiency is smaller than an effect of the first light treatment layer for increasing light emitting efficiency.

In this embodiment, the light treatment layer includes first light treatment layer and second light treatment layer, through setting up first light treatment layer at the play light side of first luminous subregion, set up the second light treatment layer at the play light side of second luminous subregion, the effect that the second light treatment layer promoted the luminous efficacy is less than the effect that first light treatment layer promoted the luminous efficacy, can promote the whole luminous efficacy of display substrate on the basis of compensative display substrate luminescence inequality, helps promoting the display effect of display substrate.

In an exemplary embodiment, the first light management layer includes a plurality of first lens structures, and an orthographic projection of the plurality of first lens structures onto the substrate at least partially overlaps an orthographic projection of the first light emitting sub-region onto the substrate.

In an exemplary embodiment, the orthographic projection of the plurality of first lens structures on the substrate may be within the range of the orthographic projection of the first light emitting sub-region on the substrate.

In an exemplary embodiment, the cross-sectional shape of the first lens structure may be semicircular, semi-elliptical, triangular, trapezoidal, or may be other shapes in a plane perpendicular to the substrate, which is not limited by the present disclosure.

In an exemplary embodiment, the second light-processing layer comprises a plurality of second lens structures, the orthographic projection of the second lens structures onto the substrate at least partially overlapping with the orthographic projection of the second light-emitting sub-regions onto the substrate.

In an exemplary embodiment, the orthographic projection of the second lens structure onto the substrate is within the range of the orthographic projection of the second light emitting sub-region onto the substrate.

In an exemplary embodiment, the cross-sectional shape of the second lens structure may be semicircular, semi-elliptical, triangular, trapezoidal, or may be other shapes in a plane perpendicular to the substrate, which is not limited by the present disclosure.

In an exemplary embodiment, a ratio of an area of orthographic projection of the plurality of first lens structures on the substrate to an area of orthographic projection of the first light emitting sub-region on the substrate is a first filling rate; the ratio of the orthographic projection area of the plurality of second lens structures on the substrate to the orthographic projection area of the second light emitting sub-region on the substrate is a second filling rate, and the first filling rate is larger than the second filling rate.

The inventor of the application researches find that the higher the filling rate of the lens structure is, the better the corresponding light extraction effect is. In this embodiment, by setting the first filling rates of the plurality of first lens structures to be greater than the second filling rates of the plurality of second lens structures, it is possible to ensure that the light extraction effect of the first light treatment layer on the first light emitting sub-region is higher than the light extraction effect of the second light treatment layer on the second light emitting sub-region, and further ensure that the brightness of the first light emitting sub-region and the second light emitting sub-region is equivalent.

In an exemplary embodiment, the first filling rate may be greater than or equal to 40% and the second filling rate may be less than or equal to 30%.

In an exemplary embodiment, the first fill rate may be greater than or equal to 50%.

The inventors of the present application have studied and found that the filling rate of the lens structure is related to the current production process level, and the higher the filling rate, the better the process conditions allow, and the present disclosure is not limited thereto.

In an exemplary embodiment, the refractive index of the first lens structure is greater than the refractive index of the second lens structure.

In an exemplary embodiment, the refractive index of the first lens structure may be greater than or equal to 1.6, and the refractive index of the second lens structure may be greater than or equal to 1.5 and less than or equal to 1.6.

The inventor of the application researches find that the higher the refractive index of the lens structure is, the better the corresponding light extraction effect is, and the light is easy to be totally reflected from the optically dense medium to the optically sparse medium, and the light is lost. In this embodiment, by setting the refractive index of the first lens structure to be greater than the refractive index of the second lens structure, it is possible to ensure that the light extraction effect of the first light-processing layer on the first light-emitting sub-region is higher than the light extraction effect of the second light-processing layer on the second light-emitting sub-region, and further ensure that the brightness of the first light-emitting sub-region and the second light-emitting sub-region are equivalent. The refractive index of the first lens structure and the refractive index of the second lens structure may be both greater than the refractive index of other film layers on the display substrate, and in practical applications, the refractive index value of the first lens structure and the refractive index value of the second lens structure may be set as required, which is not limited in this disclosure.

In an exemplary embodiment, the cross-sectional shape of the first lens structure is semicircular in a plane perpendicular to the substrate, and the cross-sectional shape of the second lens structure is different from the cross-sectional shape of the first lens structure.

The inventors of the present application have found that, with the same other parameters, the light extraction effect of a lens structure having a semicircular cross-sectional shape is higher than that of a lens structure having other cross-sectional shapes in a plane perpendicular to the substrate. In this embodiment, the cross-sectional shape of the first lens structure is semicircular, and the cross-sectional shape of the second lens structure is different from the cross-sectional shape of the first lens structure, so that the light extraction effect of the first light treatment layer on the first light emitting sub-region is higher than the light extraction effect of the second light treatment layer on the second light emitting sub-region, and the brightness of the first light emitting sub-region and the second light emitting sub-region is guaranteed to be equivalent.

In practical applications, parameters such as the filling rate, the refractive index, and the cross-sectional shape in a plane perpendicular to the substrate of the first lens structure and the second lens structure may be set as needed, which is not limited by the present disclosure.

In an exemplary embodiment, the materials of the first and second lens structures may be organic materials. In an exemplary embodiment, the materials of the first lens structure and the second lens structure may be, for example, acrylic, polyimide, or the like, and in practical applications, the first lens structure and the second lens structure may be made of a suitable material according to needs, and the materials of the first lens structure and the second lens structure may not be limited to organic materials, which is not limited in the disclosure.

In an exemplary embodiment, the first lens structure has a particle size dimension of greater than or equal to 1 micron and less than or equal to 10 microns.

In an exemplary embodiment, the first lens structure has a particle size dimension of greater than or equal to 3 microns and less than or equal to 5 microns.

In an exemplary embodiment, the particle size of the second lens structure is greater than or equal to the particle size of the first lens structure.

According to the research of the inventor, under the condition that the first lens structure is arranged to be hemispherical, the diameter of the first lens structure can be valued between 1 micron and 10 microns, when the valued is between 3 microns and 5 microns, the corresponding light extraction effect is better, and when the grain size is above a certain grain size, the smaller the grain size of the lens structure is, the better the corresponding light extraction effect is, the sizes of the corresponding first lens structure and the second lens structure can be set according to the size of the sub-pixel, and the invention is not limited. By setting the particle size of the second lens structure to be larger than or equal to that of the first lens structure, the light extraction effect of the first light treatment layer on the first light-emitting sub-area is ensured to be higher than that of the second light treatment layer on the second light-emitting sub-area, and the brightness of the first light-emitting sub-area and the second light-emitting sub-area are further ensured to be equivalent.

In an exemplary embodiment, the first light management layer and the second light management layer are co-layer.

In an exemplary embodiment, the first light treatment layer may include a single layer of the first lens structure in a direction away from the substrate, and the second light treatment layer may include a single layer of the second lens structure.

In an exemplary embodiment, the thickness of the first light management layer is about 5 microns, equal to the radius of the first lens structure, when the diameter of the first lens structure is 10 microns. When the diameter of the second lens structure is 10 micrometers, the thickness of the second light treatment layer is about 5 micrometers, which is equal to the radius of the second lens structure.

In an exemplary embodiment, the display substrate includes an encapsulation layer, the encapsulation layer is located on a side of the light emitting structure layer away from the substrate, and the light treatment layer is located on a side of the encapsulation layer away from the substrate.

In an exemplary embodiment, the display substrate includes an encapsulation layer, the encapsulation layer is located on a side of the light emitting structure layer away from the substrate, and the first light treatment layer and the second light treatment layer are located on a side of the encapsulation layer away from the substrate.

Fig. 4 is a schematic front projection of a single light emitting region and lens structure on a substrate in an exemplary embodiment. As shown in fig. 4, the orthographic projection shape of the light emitting region on the substrate may be elliptical, the light emitting region includes a first light emitting sub-region 101 located in the middle and a second light emitting sub-region 102 located around, the brightness of the first light emitting sub-region 101 is smaller than the brightness of the second light emitting sub-region 102, and the orthographic projection shapes of the first light emitting sub-region 101 and the second light emitting sub-region 102 on the substrate may be elliptical. A first light treatment layer is provided at the light exit side of the first light emitting sub-region 101, which may comprise a plurality of first lens structures 11, and a second light treatment layer is provided at the light exit side of the second light emitting sub-region 102, which may comprise a plurality of second lens structures 12. In a direction away from the substrate, the first light treatment layer may include a single layer of the first lens structure, the second light treatment layer may include a single layer of the second lens structure, and the first light treatment layer and the second light treatment layer may be disposed in the same layer. The effect of the second light treatment layer for improving the light extraction efficiency is smaller than that of the first light treatment layer for improving the light extraction efficiency. The front projections of the plurality of first lens structures 11 onto the substrate at least partly overlap with the front projections of the first light emitting sub-regions 101 onto the substrate and the front projections of the plurality of second lens structures 12 onto the substrate at least partly overlap with the front projections of the second light emitting sub-regions 102 onto the substrate.

In an exemplary embodiment, the shape of the first lens structure 11 may be a hemisphere, a bottom surface of the hemisphere may face one side of the substrate, a grain size of the hemisphere may be about 3 to 5 micrometers, an orthographic projection of the first lens structure 11 on the substrate may be a circle, and a cross-sectional shape of the first lens structure 11 may be a semicircle in a plane perpendicular to the substrate. The second lens structure 12 may have other shapes, the orthographic projection of the second lens structure 12 on the substrate may have a triangular shape, and the particle size of the second lens structure 12 may be larger than the particle size of the first lens structure 11. The cross-sectional shape of the first lens structure 11 is semicircular by being arranged in a plane perpendicular to the substrate, the cross-sectional shape of the second lens structure 12 is different from the cross-sectional shape of the first lens structure 11, the light extraction effect of the first light treatment layer on the first light emitting sub-region 101 is ensured to be higher than the light extraction effect of the second light treatment layer on the second light emitting sub-region 102, and the particle size of the second lens structure is greater than or equal to the particle size of the first lens structure by setting the particle size of the first lens structure 11 to be 3 to 5 micrometers, the light extraction effect of the first light treatment layer on the first light emitting sub-region is ensured to be higher than the light extraction effect of the second light treatment layer on the second light emitting sub-region, and accordingly the brightness of the first light emitting sub-region 101 and the second light emitting sub-region 102 is ensured to be equivalent.

In an exemplary embodiment, the ratio of the area of orthographic projection of the plurality of first lens structures 11 on the substrate to the area of orthographic projection of the first light emitting sub-region 101 on the substrate is the first filling rate; the ratio of the orthographic projection area of the plurality of second lens structures 12 on the substrate to the orthographic projection area of the second light emitting sub-region 102 on the substrate is the second filling rate. As shown in fig. 4, the first filling rate may be greater than or equal to 40%, the second filling rate may be less than or equal to 30%, and the first filling rate is greater than the second filling rate. By setting the first filling rate of the plurality of first lens structures to be larger than the second filling rate of the plurality of second lens structures, the light extraction effect of the first light treatment layer on the first light-emitting sub-region can be ensured to be higher than the light extraction effect of the second light treatment layer on the second light-emitting sub-region, and the brightness of the first light-emitting sub-region and the second light-emitting sub-region can be ensured to be equivalent.

In an exemplary embodiment, the refractive index of the first lens structure 11 is greater than the refractive index of the second lens structure 12. For example, the refractive index of the first lens structure may be greater than or equal to 1.6, the refractive index of the second lens structure may be greater than or equal to 1.5 and less than or equal to 1.6, and the refractive index of the first lens structure and the refractive index of the second lens structure may both be greater than the refractive index of other film layers on the display substrate. By setting the refractive index of the first lens structure to be larger than that of the second lens structure, the light extraction effect of the first light treatment layer on the first light-emitting sub-region can be ensured to be higher than that of the second light treatment layer on the second light-emitting sub-region, and the brightness of the first light-emitting sub-region and the second light-emitting sub-region can be ensured to be equivalent.

Fig. 5 is a schematic front projection of a single light emitting region and lens structure on a substrate in yet another exemplary embodiment. The difference between the figure and fig. 4 is that the front projection shape of the light emitting area on the substrate in fig. 5 is rectangular, the front projection shapes of the first light emitting sub-area 101 and the second light emitting sub-area 102 on the substrate are also rectangular, and the shape of the second lens structure 12 in fig. 5 is the same as the shape of the first lens structure 11, and is hemispherical, the front projections of the plurality of first lens structures 11 on the substrate are located in the front projection range of the first light emitting sub-area 101 on the substrate, and the front projections of the plurality of second lens structures 12 on the substrate are located in the front projection range of the second light emitting sub-area 102 on the substrate. Other content may refer to the description of fig. 4 and will not be described in detail herein.

In an exemplary embodiment, the orthographic projection of the light emitting region on the substrate may also be other shapes, such as a triangle, a square, a pentagon, a polygon of other shapes, or an irregular shape, and the projected shapes of the first light emitting sub-region 101 and the second light emitting sub-region 102 may also be other shapes, which the present disclosure is not limited to.

In the exemplary embodiment, the light emitting region is located in each sub-pixel, and the first light emitting sub-region 101 and the second light emitting sub-region 102 are caused by uneven film formation thickness after inkjet printing, and generally, the sub-region having a larger film thickness emits light darker, so that after film formation, film formation may be thinner at the middle position of a single sub-pixel, thicker at the edge position of a single sub-pixel, or thicker at the middle position of a single sub-pixel, and thinner at the edge position of a single sub-pixel, i.e., the positions of the first light emitting sub-region 101 and the second light emitting sub-region 102 may be interchanged. In practical application, parameters such as a shape, a size, a filling rate, a refractive index and the like of the corresponding lens structure can be set according to the film forming thickness condition of the sub-pixel, and parameters such as a shape, a size, a filling rate, a refractive index and the like of the corresponding lens structure can also be set according to the light emitting condition of the sub-pixel.

In an exemplary embodiment, a single light emitting region may be divided into a plurality of light emitting sub-regions according to a film formation thickness condition of a sub-pixel, or a sub-pixel light emitting condition, and the divided sub-regions may not be limited to the first light emitting sub-region 101 and the second light emitting sub-region 102. The corresponding lens structures may be provided according to the brightness of the plurality of light emitting sub-areas, which is not limited by the present disclosure.

Fig. 6 is a schematic cross-sectional view of a display substrate in an exemplary embodiment, illustrating the structure of one sub-pixel. As shown in fig. 6, the display substrate provided by the embodiments of the present disclosure may include a base 10, a driving circuit layer 20, a planarization layer 60, a light emitting structure layer 30, an encapsulation layer 40, and a light treatment layer 50 sequentially disposed on the base 10 on a plane perpendicular to the display substrate.

In an exemplary embodiment, the driving circuit layer 20 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and only one transistor 21A and storage capacitor 21B are exemplified in fig. 6 as the pixel driving circuit.

In an exemplary embodiment, the light emitting structure layer 30 includes a pixel defining layer 31 and a light emitting device 32, the pixel defining layer 31 includes a plurality of pixel openings, and the pixel openings form a light emitting region including at least a first light emitting sub-region and a second light emitting sub-region. Between the adjacent light emitting areas is a pixel dam, and the light emitting areas may include a red light emitting area, a green light emitting area, and a blue light emitting area, or the light emitting areas may include a red light emitting area, a green light emitting area, a blue light emitting area, and a white light emitting area, which is not limited in this disclosure. The light emitting device 32 may include an anode 301, an organic light emitting layer 302, and a cathode 303.

In an exemplary embodiment, the light treatment layer 50 may enhance light extraction efficiency, and the light treatment layer 50 may include a first light treatment layer and a second light treatment layer. The first light treatment layer comprises a plurality of first lens structures, and the orthographic projection of the plurality of first lens structures on the substrate 10 is positioned within the range of the orthographic projection of the first light emitting sub-region on the substrate 10. The second light management layer comprises a plurality of second lens structures whose orthographic projection onto the substrate 10 is within the range of the orthographic projection of the second light emitting sub-region onto the substrate 10.

In an exemplary embodiment, the light from the light emitting region is deflected in a direction toward the center of the light emitting region after passing through the light treatment layer 50, and the light emitting efficiency of the sub-pixel can be improved. In an exemplary embodiment, the light emitting region center may be a geometric center of the light emitting region.

In an exemplary embodiment, the cross-sectional shape of the first lens structure may be semicircular in a plane perpendicular to the substrate, and the cross-sectional shape of the second lens structure may be different from the cross-sectional shape of the first lens structure. The present disclosure is not limited in this regard.

In an exemplary embodiment, a ratio of an area of orthographic projection of the plurality of first lens structures on the substrate to an area of orthographic projection of the first light emitting sub-region on the substrate is a first fill factor; the ratio of the orthographic projection area of the plurality of second lens structures on the substrate to the orthographic projection area of the second light emitting sub-region on the substrate is a second filling rate, and the first filling rate is larger than the second filling rate.

In an exemplary embodiment, the refractive index of the first lens structure is greater than the refractive index of the second lens structure.

In an exemplary embodiment, other film layers such as a touch structure layer may be further disposed on a side of the encapsulation structure layer 40 away from the substrate 10, which is not limited in the present disclosure.

The structure of the display substrate of the present disclosure is described below by way of an example of a display substrate preparation process. The "patterning process" referred to in this disclosure includes processes such as depositing a film, coating a photoresist, mask exposing, developing, etching, and stripping the photoresist. The deposition may be any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may be any one or more selected from spray coating and spin coating, and the etching may be any one or more selected from dry etching and wet etching. "film" refers to a layer of film made by depositing or coating a material onto a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process throughout the fabrication process. When the "thin film" is also subjected to a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The phrase "a and B are co-layer disposed" in this disclosure means that a and B are formed simultaneously by the same patterning process. "the front projection of A includes the front projection of B" means that the front projection of B falls within the front projection range of A, or that the front projection of A covers the front projection of B.

In an exemplary embodiment, the manufacturing process of the display substrate shown in fig. 6 may include the following steps.

(1) The driving circuit layer and the planarization layer pattern are formed. In an exemplary embodiment, forming the driving circuit layer pattern may include:

a first insulating film and a semiconductor film are sequentially deposited on the substrate 10, the semiconductor film is patterned through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer pattern disposed on the first insulating layer, and the semiconductor layer pattern of each sub-pixel may include at least a plurality of active layers.

Subsequently, a second insulating film and a first conductive film are sequentially deposited, the first conductive film is patterned through a patterning process, a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, and the first conductive layer pattern of each sub-pixel may include at least a plurality of gate electrodes and first electrode plates.

Then, a third insulating film and a second conductive film are sequentially deposited, the second conductive film is patterned through a patterning process, a third insulating layer covering the first conductive layer and a second conductive layer pattern arranged on the third insulating layer are formed, the second conductive layer pattern of each sub-pixel can at least comprise a second polar plate, and the orthographic projection of the second polar plate on the substrate at least partially overlaps with the orthographic projection of the first polar plate on the substrate.

And then, depositing a fourth insulating film, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the second conductive layer pattern, wherein two active through holes are formed on the fourth insulating layer of each sub-pixel, and the two active through holes respectively expose two ends of the active layer.

Then, depositing a third conductive film, patterning the third conductive film by a patterning process, and forming a third conductive layer pattern on the fourth insulating layer, wherein the third conductive layer pattern at least comprises: and the source electrode and the drain electrode are positioned on each sub-pixel and are respectively connected with the active layer through the active via hole.

Subsequently, a flat film is coated on the substrate on which the patterns are formed, the flat film is patterned by a patterning process to form a pattern of a third conductive layer pattern 60, and at least one connection via hole is formed on the flat layer of each sub-pixel, and the connection via hole exposes the surface of the drain electrode.

Thus, the driving circuit layer 20 and the planarization layer 60 are patterned.

In an exemplary embodiment, the driving circuit layer 20 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and only one transistor 21A and storage capacitor 21B are exemplified in fig. 6 as the pixel driving circuit.

In an exemplary embodiment, the transistor 21A may include an active layer, a gate electrode, a source electrode, and a drain electrode, and the storage capacitor 21B may include a first plate and a second plate. In an exemplary embodiment, the transistor 21A may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (Thin Film Transistor, abbreviated as TFT).

In an exemplary embodiment, the substrate may be a rigid substrate, or may be a flexible substrate. The rigid substrate may be made of glass or quartz, the flexible substrate may be made of Polyimide (PI) or the like, the flexible substrate may be a single-layer structure, or a laminated structure formed by an inorganic material layer and a flexible material layer, which is not limited herein.

In an exemplary embodiment, the first, second, third, and fourth insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer may be referred to as a Buffer (Buffer) layer, the second and third insulating layers may be referred to as (GI) layers, and the fourth insulating layer may be referred to as an interlayer Insulating (ILD) layer. The first, second, and third conductive layers may be made of a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure such as Ti/Al/Ti, or the like. The planarization layer may be made of an organic material such as resin. The semiconductor layer may be made of various materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on Oxide technology, silicon technology, and organic technology, and the present disclosure is not limited thereto.

(2) Forming a light emitting structure layer pattern. In an exemplary embodiment, forming the light emitting structure layer pattern may include:

a fourth conductive film is deposited on the substrate on which the foregoing pattern is formed, and patterned by a patterning process to form an anode electrode layer pattern, and the anode electrode layer pattern of each sub-pixel may include at least an anode 301, and the anode 301 is connected to the drain electrode of the transistor 21A through a connection via.

Subsequently, a pixel defining film is coated on the substrate on which the foregoing pattern is formed, the pixel defining film is patterned by a patterning process to form a pixel defining layer 31, the pixel defining layer of each sub-pixel is provided with a pixel opening, the pixel defining film in the pixel opening is removed, and the surface of the anode 301 is exposed.

Subsequently, on the substrate on which the foregoing pattern is formed, an organic light emitting layer 302 is formed at each sub-pixel by an inkjet printing method, and the organic light emitting layer 302 is connected to the anode 301 through a pixel opening. After printing is completed, recording the morphology of the printed film.

Then, on the substrate with the patterns, the cathode 303 is formed by an evaporation method of an open mask, the cathode 303 with the whole surface structure is connected with the organic light-emitting layer 302, and the organic light-emitting layer 303 is connected with the anode 301 and the cathode 303 simultaneously.

Thus, the light emitting structure layer 30 pattern is prepared.

In an exemplary embodiment, the fourth conductive thin film may employ a metal material, a transparent conductive material, or a multi-layered composite structure of a metal material and a transparent conductive material, the metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, the transparent conductive material may include Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), the multi-layered composite structure may be ITO/Al/ITO, or the like.

In an exemplary embodiment, the pixel definition layer may be a pixel bank or a line bank. The material of the pixel defining film may include polyimide, acryl, or the like. The material of the pixel defining film may also be an inorganic material, which is not limited by the present disclosure.

In an exemplary embodiment, the organic light emitting layer may include an emitting layer (EML), and any one or more of the following: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL).

In an exemplary embodiment, the organic light emitting layer may be prepared in the following manner: firstly, a hole injection layer, a hole transport layer and an electron blocking layer are sequentially formed by adopting an ink-jet printing process, and a common layer of the hole injection layer, the hole transport layer and the electron blocking layer is formed on a display substrate. The light emitting layers of adjacent sub-pixels may be slightly overlapped (e.g., overlapping portions occupy less than 10% of the area of the respective light emitting layer pattern) or may be isolated, using an inkjet printing process to form different light emitting layers at different sub-pixels. And then sequentially forming a hole blocking layer, an electron transport layer and an electron injection layer by adopting an ink-jet printing process, and forming a common layer of the hole blocking layer, the electron transport layer and the electron injection layer on the display substrate.

In an exemplary embodiment, a microcavity conditioning layer may be included in the organic light-emitting layer such that the thickness of the organic light-emitting layer between the cathode and anode meets the design of microcavity length. In some exemplary embodiments, a hole transport layer, an electron blocking layer, a hole blocking layer, or an electron transport layer may be employed as the microcavity conditioning layer, and the disclosure is not limited herein.

In an exemplary embodiment, the light emitting layer may include a Host (Host) material and a guest (guest) material doped in the Host material, and the doping ratio of the guest material of the light emitting layer is 1% to 20%. In the doping proportion range, on one hand, the light-emitting layer host material can effectively transfer exciton energy to the light-emitting layer guest material to excite the light-emitting layer guest material to emit light, and on the other hand, the light-emitting layer host material 'dilutes' the light-emitting layer guest material, so that the fluorescent quenching caused by the mutual collision between molecules of the light-emitting layer guest material and the mutual collision between energies is effectively improved, and the light-emitting efficiency and the service life of a device are improved. In an exemplary embodiment, the doping ratio refers to a ratio of the mass of the guest material to the mass of the light emitting layer, i.e., mass percent. In an exemplary embodiment, the host material and the guest material may be co-evaporated by a multi-source evaporation process to uniformly disperse the host material and the guest material in the light emitting layer, and the doping ratio may be controlled by controlling the evaporation rate of the guest material during the evaporation process or by controlling the evaporation rate ratio of the host material and the guest material. In an exemplary embodiment, the thickness of the light emitting layer may be about 10nm to 50nm.

In an exemplary embodiment, the hole injection layer may use an inorganic oxide such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or may use a p-type dopant of a strong electron withdrawing system and a dopant of a hole transport material, and the hole injection layer may have a thickness of about 5nm to 20nm.

In an exemplary embodiment, a material having higher hole mobility, such as an arylamine compound, may be used as the hole transport layer, and a substituent group thereof may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, furan, or the like, and the hole transport layer may have a thickness of about 40nm to 150nm.

In an exemplary embodiment, the hole blocking layer and the electron transporting layer may employ aromatic heterocyclic compounds, such as imidazole derivatives, for example, benzimidazole derivatives, imidazopyridine derivatives, benzimidazole benzophenanthridine derivatives, and the like; pyrimidine derivatives, triazine derivatives and other oxazine derivatives; compounds containing a nitrogen-containing six-membered ring structure such as quinoline derivatives, isoquinoline derivatives and phenanthroline derivatives (including compounds having a phosphine oxide substituent on the heterocycle). In an exemplary embodiment, the hole blocking layer may have a thickness of about 5nm to 15nm, and the electron transport layer may have a thickness of about 20nm to 50nm.

In an exemplary embodiment, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or a compound of these alkali metals or metals, and the thickness of the electron injection layer may be about 0.5nm to 2nm.

In an exemplary embodiment, the cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

(3) And forming a packaging structure layer pattern. In an exemplary embodiment, forming the encapsulation structure layer pattern may include:

on the substrate with the patterns, a first packaging film is deposited by using an open mask plate in a deposition mode to form a first sub-layer pattern, then a second packaging material is printed by using the open mask plate in an ink-jet printing process to form a second sub-layer pattern, and then a third packaging film is deposited by using the open mask plate in a deposition mode to form a third sub-layer pattern. Thus, the encapsulation layer pattern is prepared. Other structures may be used for the encapsulation layer 40, and the disclosure is not limited thereto.

In an exemplary embodiment, the first and third encapsulation films may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), may be a single layer, a multi-layer or a composite layer, may ensure that external water oxygen cannot enter the light emitting structure layer, and may be deposited by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The second encapsulation film may be made of an organic material, such as a resin, and functions to encapsulate each film layer of the display substrate, so as to improve structural stability and flatness.

Thus, the packaging structure layer pattern is prepared.

(4) Forming a pattern of the light treatment layer. In an exemplary embodiment, forming the light treatment layer pattern may include:

and determining a first luminous subarea and a second luminous subarea according to the recorded morphology of the printed film, wherein the subarea with larger film thickness is the first luminous subarea, and the subarea with smaller film thickness is the second luminous subarea. For example, the light-emitting area of a single sub-pixel has a thick film shape in the middle and thin edges, the first light-emitting sub-area is in the middle of the light-emitting area, and the second light-emitting sub-area is at the edge of the light-emitting area. Alternatively, the first light emitting sub-region and the second light emitting sub-region may be determined according to the light emitting condition of the light emitting region, where the sub-region with lower luminance is the first light emitting sub-region and the sub-region with higher luminance is the second light emitting sub-region.

And forming a first light treatment layer on the substrate with the patterns, wherein the first light treatment layer comprises a plurality of first lens structures, and the second light treatment layer comprises a plurality of second lens structures.

In an exemplary embodiment, the first and second lens structures may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), may be a single layer, a multi-layer, or a composite layer, and may be deposited by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), etc.

Thus, the light treatment layer 50 pattern is prepared.

After the above preparation, the structure of the obtained display substrate is shown in fig. 6. The display substrate may further include other film structures, such as a touch structure layer, a protective layer, etc., which may be prepared according to actual needs, and will not be described herein.

The structures shown in the exemplary embodiments of the present disclosure and the processes for preparing them are merely exemplary illustrations. In actual implementation, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs, which is not limited in this disclosure.

The embodiment of the disclosure also provides a display device, which comprises the display substrate according to any one of the embodiments. The display device may be: the embodiments of the present disclosure are not limited to any products or components with display functions, such as OLED displays, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigator, etc.

The embodiment of the disclosure also provides a preparation method of the display substrate, which comprises the following steps: forming a light emitting structure layer on a substrate, the light emitting structure layer comprising a plurality of light emitting regions, the light emitting regions comprising a first light emitting sub-region and a second light emitting sub-region, the first light emitting sub-region having a brightness less than the second light emitting sub-region; forming a light treatment layer on one side of the light-emitting structure layer far away from the substrate; the light treatment layer comprises a first light treatment layer, which is positioned at the light emitting side of the first light emitting sub-region and is configured to improve the light emitting efficiency of the first light emitting sub-region.

In an exemplary embodiment, the light emitting structure layer comprises an organic light emitting layer, the organic light emitting layer is formed by adopting an inkjet printing mode, and the morphology of the film formed by printing the organic light emitting layer is recorded; the light treatment layer further comprises a second light treatment layer, the second light treatment layer is positioned on the light emergent side of the second light-emitting subarea and is configured to improve the light emergent efficiency of the second light-emitting subarea;

the forming a light treatment layer on the side of the light emitting structure layer away from the substrate comprises the following steps:

determining the first light-emitting subarea and the second light-emitting subarea according to the shape of the organic light-emitting layer printed film, forming a first light treatment layer on the light-emitting side of the first light-emitting subarea, and forming a second light treatment layer on the light-emitting side of the second light-emitting subarea.

In an exemplary embodiment, the light treatment layer further comprises a second light treatment layer located on the light exit side of the second light emitting sub-region, configured to increase the light exit efficiency of the second light emitting sub-region;

the forming a light treatment layer on the side of the light emitting structure layer away from the substrate comprises the following steps:

and determining the first light-emitting subarea and the second light-emitting subarea according to the light-emitting condition of the light-emitting area, forming a first light treatment layer on the light-emitting side of the first light-emitting subarea, and forming a second light treatment layer on the light-emitting side of the second light-emitting subarea.

In an exemplary embodiment, the first light management layer includes a plurality of first lens structures and the second light management layer includes a plurality of second lens structures.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims (15)

1. A display substrate, comprising: the light-emitting device comprises a substrate, a light-emitting structure layer arranged on the substrate and a light treatment layer arranged on one side of the light-emitting structure layer away from the substrate;

the light-emitting structure layer comprises a plurality of light-emitting areas, wherein the light-emitting areas comprise a first light-emitting sub-area and a second light-emitting sub-area, and the brightness of the first light-emitting sub-area is smaller than that of the second light-emitting sub-area; the light treatment layer comprises a first light treatment layer, which is positioned at the light emitting side of the first light emitting sub-region and is configured to improve the light emitting efficiency of the first light emitting sub-region.

2. The display substrate of claim 1, wherein the light management layer further comprises a second light management layer positioned on a light-emitting side of the second light-emitting sub-region configured to enhance light-emitting efficiency of the second light-emitting sub-region;

the effect of the second light treatment layer for improving the light-emitting efficiency is smaller than that of the first light treatment layer for improving the light-emitting efficiency.

3. The display substrate of claim 2, wherein the first light management layer comprises a plurality of first lens structures, an orthographic projection of the plurality of first lens structures onto the substrate at least partially overlapping an orthographic projection of a first light emitting sub-region onto the substrate.

4. A display substrate according to claim 3, characterized in that the second light-handling layer comprises a plurality of second lens structures, the orthographic projections of the plurality of second lens structures on the substrate at least partly overlapping the orthographic projections of the second light-emitting sub-areas on the substrate.

5. The display substrate of claim 4, wherein a ratio of an area of orthographic projection of the plurality of first lens structures on the base to an area of orthographic projection of the first light-emitting sub-region on the base is a first fill factor; the ratio of the orthographic projection area of the plurality of second lens structures on the substrate to the orthographic projection area of the second luminous subarea on the substrate is a second filling rate; the first filling rate is greater than the second filling rate.

6. The display substrate of claim 5, wherein the first fill rate is greater than or equal to 40% and the second fill rate is less than or equal to 30%.

7. The display substrate of claim 4, wherein the refractive index of the first lens structure is greater than the refractive index of the second lens structure.

8. The display substrate of claim 4, wherein the first lens structure has a semicircular cross-sectional shape in a plane perpendicular to the base, and the second lens structure has a cross-sectional shape different from the first lens structure.

9. The display substrate of claim 4, wherein the second lens structure has a particle size greater than a particle size of the first lens structure.

10. The display substrate according to claim 4, wherein the first light treatment layer and the second light treatment layer are provided in the same layer.

11. The display substrate of claim 1, wherein the display substrate comprises an encapsulation layer on a side of the light emitting structure layer away from the base, and the light treatment layer is on a side of the encapsulation layer away from the base.

12. A display device comprising the display substrate according to any one of claims 1 to 11.

13. A method for manufacturing a display substrate, the method comprising: forming a light emitting structure layer on a substrate, the light emitting structure layer comprising a plurality of light emitting regions, the light emitting regions comprising a first light emitting sub-region and a second light emitting sub-region, the first light emitting sub-region having a brightness less than the second light emitting sub-region;

forming a light treatment layer on one side of the light emitting structure layer away from the substrate; the light treatment layer comprises a first light treatment layer, which is positioned at the light emitting side of the first light emitting sub-region and is configured to improve the light emitting efficiency of the first light emitting sub-region.

14. The method according to claim 13, wherein the light-emitting structure layer comprises an organic light-emitting layer, the organic light-emitting layer is formed by means of inkjet printing, and the morphology of the film formed by the organic light-emitting layer is recorded; the light treatment layer further comprises a second light treatment layer, the second light treatment layer is positioned on the light emergent side of the second light-emitting subarea and is configured to improve the light emergent efficiency of the second light-emitting subarea;

The forming a light treatment layer on the side of the light emitting structure layer away from the substrate comprises the following steps:

determining the first light-emitting subarea and the second light-emitting subarea according to the shape of the organic light-emitting layer printed film, forming a first light treatment layer on the light-emitting side of the first light-emitting subarea, and forming a second light treatment layer on the light-emitting side of the second light-emitting subarea.

15. The method of manufacturing according to claim 13, wherein the light treatment layer further comprises a second light treatment layer, the second light treatment layer being located on the light-emitting side of the second light-emitting sub-region and configured to increase the light-emitting efficiency of the second light-emitting sub-region;

the forming a light treatment layer on the side of the light emitting structure layer away from the substrate comprises the following steps:

and determining the first light-emitting subarea and the second light-emitting subarea according to the light-emitting condition of the light-emitting area, forming a first light treatment layer on the light-emitting side of the first light-emitting subarea, and forming a second light treatment layer on the light-emitting side of the second light-emitting subarea.

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