CN116033737A

CN116033737A - Semiconductor structure and forming method thereof

Info

Publication number: CN116033737A
Application number: CN202111238920.3A
Authority: CN
Inventors: 李双; 洪海涵; 王晓玲
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2023-04-28

Abstract

The present application relates to a semiconductor structure and a method of forming the same. The method for forming the semiconductor structure comprises the following steps: forming a base, wherein the base comprises a substrate and a plurality of capacitance contact structures positioned on the substrate; forming a first support layer covering the top surface of the substrate, wherein the first support layer comprises a first sub-layer and a second sub-layer which are alternately stacked; forming a second supporting layer covering the surface of the first supporting layer; and forming a capacitor hole penetrating the second supporting layer and the first supporting layer and exposing the capacitor contact structure. The method ensures stable and reliable contact of the capacitor and the capacitor contact structure formed later, and can reduce leakage current.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor structure commonly used in electronic devices such as computers and is composed of a plurality of memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected with the word line, the source is electrically connected with the bit line, the drain is electrically connected with the capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that the data information stored in the capacitor can be read through the bit line or written into the capacitor.

With the shrinking of semiconductor process dimensions, the size of the capacitor hole is gradually reduced and the aspect ratio of the etched capacitor hole is gradually increased in the process of manufacturing the dynamic random access memory. The traditional capacitor hole etching process can cause insufficient etching, and the conductive contact performance and stability of the capacitor are affected; or may cause excessive leakage current that affects the electrical performance of the capacitor.

Therefore, how to improve the etching process of the capacitor hole, and reduce the leakage current on the basis of ensuring the capacitor to have good conductive contact performance, thereby realizing the improvement of the electrical performance of the semiconductor structure is a technical problem to be solved at present.

Disclosure of Invention

The semiconductor structure and the forming method thereof provided by some embodiments of the present application are used for reducing the leakage current of the capacitor, improving the conductive contact performance of the capacitor, and ensuring the performance stability of the semiconductor structure

According to some embodiments, the application provides a method for forming a semiconductor structure, including the following steps:

forming a base, wherein the base comprises a substrate and a plurality of capacitance contact structures positioned on the substrate;

forming a first support layer covering the top surface of the substrate, wherein the first support layer comprises a first sub-layer and a second sub-layer which are alternately stacked;

forming a second supporting layer covering the surface of the first supporting layer;

and forming a capacitor hole penetrating the second supporting layer and the first supporting layer and exposing the capacitor contact structure.

In some embodiments, the specific steps of forming the substrate include:

providing a substrate, wherein the substrate is provided with a plurality of capacitance contact areas;

and forming a plurality of capacitor contact structures electrically connected with the capacitor contact areas respectively, and an isolation layer filled between the adjacent capacitor contact structures.

In some embodiments, the specific step of forming a first support layer overlying the top surface of the substrate comprises:

the first sub-layer and the second sub-layer are formed to be alternately stacked in a direction perpendicular to a top surface of the substrate.

In some embodiments, the specific step of forming the first sub-layer and the second sub-layer alternately stacked in a direction perpendicular to the top surface of the substrate comprises:

transmitting a raw material gas and a doping source gas to the surface of the substrate to form the first sub-layer comprising a main component material and a doping element;

and transmitting the raw material gas to the surface of the first sub-layer to form the second sub-layer which comprises the main component material and does not comprise the doping element.

delivering a source gas comprising a nitrogen source and a silicon source, and a dopant source gas to the substrate surface to form the first sub-layer comprising a dopant element and silicon nitride;

and transmitting raw material gas comprising the nitrogen source and the silicon source to the surface of the first sub-layer to form the second sub-layer with pure silicon nitride as a material.

In some embodiments, the doping element is any one or a combination of two or more of C, B, as, P.

In some embodiments, the doping element has a doping concentration of 5% to 65%.

In some embodiments, the capacitive aperture includes a first portion in the first support layer and a second portion in the second support layer;

the width of the first portion is equal to the width of the second portion; or alternatively, the process may be performed,

the width of the first portion is greater than the width of the second portion, and the difference between the width of the first portion and the width of the second portion is less than or equal to 5nm.

According to further embodiments, the present application also provides a semiconductor structure, including:

a base comprising a substrate and a plurality of capacitive contact structures located on the substrate;

the first supporting layer covers the top surface of the substrate and comprises a first sub-layer and a second sub-layer which are alternately stacked;

the second supporting layer is covered on the surface of the first supporting layer;

and the capacitor hole penetrates through the first supporting layer and the second supporting layer.

In some embodiments, the substrate comprises:

the substrate is internally provided with a plurality of capacitance contact areas, and a plurality of capacitance contact structures are respectively and electrically connected with the capacitance contact areas;

and the isolation layer is filled between the adjacent capacitor contact structures.

In some embodiments, the first sub-layer and the second sub-layer are alternately stacked in a direction perpendicular to the top surface of the substrate.

In some embodiments, the material of the first sub-layer comprises a main constituent material and a doping element, and the material of the second sub-layer comprises the main constituent material and does not comprise the doping element.

In some embodiments, the material of the first sub-layer comprises silicon nitride and a doping element, and the material of the second sub-layer is pure silicon nitride.

According to the semiconductor structure and the forming method thereof, the first supporting layer is formed on the surface of the substrate, the first supporting layer is limited to comprise the first sub-layer and the second sub-layer which are alternately stacked, the first sub-layer is used for increasing the etching rate of the first supporting layer along the direction perpendicular to the top surface of the substrate, and the second sub-layer is used for reducing the etching rate of the first supporting layer along the direction parallel to the top surface of the substrate, so that in the process of forming the capacitor hole through etching, on one hand, the first supporting layer can be fully penetrated, the capacitor contact structure at the bottom of the first supporting layer is completely exposed, and stable and reliable contact between a capacitor formed subsequently and the capacitor contact structure is ensured; on the other hand, the lateral expansion of the bottom of the capacitor hole can be reduced, and the oversized bottom of the capacitor hole is avoided, so that leakage current is reduced, and the electrical performance of the semiconductor structure is improved.

Drawings

FIG. 1 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present application;

FIGS. 2A-2F are schematic cross-sectional views of the main process during formation of a semiconductor structure in accordance with embodiments of the present application;

fig. 3 is a schematic diagram of a semiconductor structure in an embodiment of the present application.

Detailed Description

Specific embodiments of a semiconductor structure and a method for forming the same provided herein are described in detail below with reference to the accompanying drawings.

The present embodiment provides a method for forming a semiconductor structure, fig. 1 is a flowchart of a method for forming a semiconductor structure in the embodiment of the present application, and fig. 2A-2F are schematic cross-sectional views of main processes in forming a semiconductor structure in the embodiment of the present application. The semiconductor structure provided in this embodiment may be, but is not limited to, a DRAM. As shown in fig. 1 and fig. 2A to fig. 2F, the method for forming the semiconductor structure includes the following steps:

in step S11, a base is formed, where the base includes a substrate and a plurality of capacitor contact structures 20 located on the substrate, as shown in fig. 2A.

In some embodiments, the specific steps of forming the substrate include:

a plurality of the capacitor contact structures 20 electrically connected to the plurality of the capacitor contact regions, respectively, and an isolation layer 21 filled between the adjacent capacitor contact structures 20 are formed.

Specifically, the substrate may be, but is not limited to, a silicon substrate, and this embodiment will be described by taking the example in which the substrate is a silicon substrate. In other examples, the substrate may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate is internally provided with a plurality of active areas which are arranged in an array, and each active area comprises a bit line contact area and a capacitor contact area. Before forming the plurality of capacitor contact structures 20, a capacitor transfer layer may be formed on the surface of the substrate, where the capacitor transfer layer has capacitor contact points 24 electrically connected to the plurality of capacitor contact regions one by one and bit line contact points electrically connected to the plurality of bit line contact regions one by one. The material of the capacitor contact 24 and the bit line contact may be polysilicon. Thereafter, a plurality of the capacitor contact structures 20 electrically connected to the plurality of the capacitor contact points 24 in one-to-one correspondence, and a plurality of bit lines 23 electrically connected to the plurality of the bit line contact points in one-to-one correspondence are formed. The material of the capacitor contact structure 20 and the bit line 23 may be conductive metal material, such as tungsten. A diffusion barrier layer 22 may also be provided between the capacitive contact structure 20 and the capacitive contact 24, and between the bit line 23 and the bit line contact, for blocking out diffusion of conductive particles in the capacitive contact structure 20 and the bit line 23. Also included in the substrate are a plurality of barrier structures 25 for isolating adjacent ones of the capacitive contact points 24 from the bit line contact points and isolating adjacent ones of the capacitive contact structures 20 from the bit line 23. The material of the barrier structure 25 may be, but is not limited to, an oxide material, such as silicon dioxide. The plurality of capacitor contact structures 20 are independent of each other, i.e. adjacent capacitor contact structures 20 are arranged apart. In order to avoid the influence between adjacent ones of the capacitance contact structures 20, an isolation layer 21 as shown in fig. 2A is also formed in the space between adjacent ones of the capacitance contact structures 20. The material of the isolation layer 21 may be an oxide material (e.g., silicon dioxide) or a nitride material (e.g., silicon nitride). This embodiment is described by taking pure silicon nitride (i.e., undoped silicon nitride) as an example of the material of the isolation layer 21.

In step S12, a first supporting layer 26 is formed to cover the top surface of the substrate, where the first supporting layer 26 includes a first sub-layer 261 and a second sub-layer 262 that are alternately stacked, as shown in fig. 2D.

In this embodiment, the first sublayer 261 is used to increase the etching rate of the first support layer 26 in a direction perpendicular to the top surface of the substrate (e.g., the Z-axis direction in fig. 2D), and the second sublayer 262 is used to decrease the etching rate of the first support layer 26 in a direction parallel to the top surface of the substrate (e.g., the X-axis direction or the Y-axis direction in fig. 2D). Specifically, by providing the first sub-layer 261 and the second sub-layer 262 that are alternately stacked in the first supporting layer 26, the etching rate of the first supporting layer 26 along the direction perpendicular to the top surface of the substrate (for example, the Z-axis direction in fig. 2D) is increased by the first sub-layer 261, so that the first supporting layer 26 is fully penetrated in the subsequent process of etching to form the capacitor hole, and the capacitor contact structure 20 at the bottom of the first supporting layer 26 is fully exposed, so that stable and reliable contact between the capacitor formed subsequently and the capacitor contact structure 20 is ensured. By reducing the etch rate of the first support layer 26 in a direction parallel to the top surface of the substrate (e.g., the X-axis direction or the Y-axis direction in fig. 2D) by the second sub-layer 262, the lateral expansion of the bottom of the capacitor hole can be reduced, avoiding an oversized bottom of the capacitor hole, and thus reducing leakage current. In one embodiment, the overall etch rate of the first sub-layer 261 (including the etch rate in a direction perpendicular to the top surface of the substrate and the etch rate in a direction parallel to the top surface of the substrate) is greater than the overall etch rate of the second sub-layer 262 (including the etch rate in a direction perpendicular to the top surface of the substrate and the etch rate in a direction parallel to the top surface of the substrate) to facilitate flexible adjustment of the film thicknesses of the first and

second sub-layers

261, 262, as well as the number of layers alternately stacked, depending on the size of the capacitor hole to be etched.

The specific materials of the first sublayer 261 and the second sublayer 262 may be selected by those skilled in the art according to actual needs, for example, according to the specific type of etchant used in the subsequent process of etching the capacitor hole, which is not limited in this embodiment.

In some embodiments, the specific step of forming the first support layer 26 overlying the top surface of the substrate includes:

the first sub-layer 261 and the second sub-layer 262 alternately stacked in a direction perpendicular to the top surface of the substrate (for example, a Z-axis direction in fig. 2D) are formed as shown in fig. 2D.

In some embodiments, the specific step of forming the first sub-layer 261 and the second sub-layer 262 alternately stacked in a direction perpendicular to the top surface of the substrate includes:

delivering a source gas and a dopant source gas to the substrate surface to form the first sub-layer 261 including a main constituent material and a dopant element, as shown in fig. 2B;

the source gas is transferred to the surface of the first sub-layer 261 to form the second sub-layer 262 including the main component material and excluding the doping element, as shown in fig. 2C.

delivering a source gas comprising a nitrogen source and a silicon source, and a dopant source gas to the substrate surface, forming the first sub-layer 261 comprising a dopant element and silicon nitride;

the source gases including the nitrogen source and the silicon source are transferred to the surface of the first sub-layer 261 to form the second sub-layer 262 of pure silicon nitride.

The material of the first sub-layer 261 includes silicon nitride and doping elements, and the material of the second sub-layer 262 is pure silicon nitride. After forming the substrate, a dopant source gas (e.g., BCl ₃ 、CH ₃ Cl、AsH ₄ Or PCl ₃ ) To the surface of the substrate, then N ₂ Purging and then introducing NH ₃ And Si (Si) ₂ H ₄ Cl ₆ And forming a silicon nitride film doped with BN, siC, P or As on the substrate surface by an atomic layer deposition process, and taking the formed silicon nitride film doped with BN, siC, P or As the first sub-layer 261, as shown in fig. 2B. Thereafter, N is performed on the surface of the first sub-layer 261 ₂ And purging to remove impurities such as residual dopant source gases, and by-products generated during the formation of the first sub-layer 261. Next, NH is introduced ₃ To the surface of the first sub-layer 261, N is performed ₂ After purging, then Si is introduced ₂ H ₄ Cl ₆ A pure silicon nitride layer is formed on the surface of the first sub-layer 261 by an atomic layer deposition process, and the formed pure silicon nitride layer is used as the second sub-layer 262. After forming the second sub-layer 262, the second sub-layer 262 is again N ₂ Purging to remove residual of the raw material gas (including NH ₃ And Si (Si) ₂ H ₄ Cl ₆ ) And impurities such as byproducts generated during the formation of the second sub-layer 262. Repeating the forming step of the first sub-layer 261 and the forming step of the second sub-layer 262 a plurality of times, a plurality of the first sub-layers 261 and a plurality of theThe second sub-layer 262, and the first sub-layer 261 and the second sub-layer 262 are alternately stacked in a direction perpendicular to the top surface of the substrate, as shown in fig. 2D. The plural numbers described in this embodiment mode refer to two or more.

In some embodiments, the doping element has a doping concentration of 5% to 65%. In one embodiment, the doping concentration of the doping element is 10% -30%. The doping concentration in this embodiment refers to the mass concentration of the doping element in the first sub-layer 261.

In step S13, a second supporting layer 27 is formed to cover the surface of the first supporting layer 26, as shown in fig. 2E.

The material of the second support layer 27 may be the same as the material of the second sub-layer 262 in order to accurately control the etching rate of the first support layer 26 during the etching process of forming the capacitor hole 28. Taking the material of the second support layer 27 as pure silicon nitride material as an example, after forming the first support layer 26, NH is introduced ₃ To the surface of the first support layer 26, N is applied ₂ After purging, then Si is introduced ₂ H ₄ Cl ₆ A pure silicon nitride layer is formed on the surface of the first support layer 26 by an atomic layer deposition process, and the pure silicon nitride layer formed on the first support layer 26 is used as the second support layer 27, as shown in fig. 2E.

In step S14, a capacitor hole 28 is formed through the second support layer 27 and the first support layer 26 and exposes the capacitor contact structure 20, as shown in fig. 2F.

Specifically, the second support layer 27 and the first support layer 26 may be etched using a dry etching process, the capacitor hole 28 penetrating the second support layer 27 and the first support layer 26 in a direction perpendicular to the top surface of the substrate (for example, a Z-axis direction in fig. 2F) is formed, and the bottom of the capacitor hole 28 enables the capacitor contact structure 20 to be completely exposed. The first support layer 26 and the second support layer 27 remaining after etching together serve as bottom support layers for the capacitor holes 28.

In some embodiments, the capacitive aperture 28 includes a first portion 281 located in the first support layer 26 and a second portion 282 located in the second support layer 27;

the width W1 of the first portion 281 is equal to the width W2 of the second portion 282; or alternatively, the process may be performed,

the width W1 of the first portion 281 is greater than the width W2 of the second portion 282, and the difference between the width W1 of the first portion 281 and the width W2 of the second portion 282 is less than 5nm.

Specifically, by selecting appropriate types of the first sub-layer 261, the second sub-layer 262, the second support layer 27, and the etchant, the width W1 of the first portion 281 in the capacitor hole 28 formed by etching may be made equal to the width W2 of the second portion 282, so as to ensure the vertical topography of the capacitor hole 28. Alternatively, the width W1 of the first portion 281 is greater than the width W2 of the second portion 282, and the difference between the width W1 of the first portion 281 and the width W2 of the second portion 282 is less than or equal to 5nm, to ensure that the bottom of the capacitive hole 28 fully exposes the capacitive contact structure 20. The width W1 of the first portion 281 may be 20nm to 45nm in this embodiment.

In this embodiment, during the process of etching the second supporting layer 27 and the first supporting layer 26 by using a dry etching process to form the capacitor hole 28, a part of the first sub-layer 261 is etched back, so that the sidewall of the first portion 281 is in a zigzag shape. When the sidewall of the first portion 281 is zigzag, the width W1 of the first portion 281 refers to the width of the second portion 281 in the second sub-layer 262.

The embodiment also provides a semiconductor structure. Fig. 3 is a schematic diagram of a semiconductor structure in an embodiment of the present application. The semiconductor structure provided in this embodiment may be formed by a method for forming a semiconductor structure as shown in fig. 1 and fig. 2A to fig. 2F. As shown in fig. 3, the semiconductor structure includes:

a base comprising a substrate and a plurality of capacitive contact structures 20 located on the substrate;

a first supporting layer 26 covering the top surface of the substrate, wherein the first supporting layer 26 includes a first sub-layer 261 and a second sub-layer 262 stacked alternately, the first sub-layer 261 is used for increasing the etching rate of the first supporting layer 26 along the direction perpendicular to the top surface of the substrate, and the second sub-layer 262 is used for reducing the etching rate of the first supporting layer 26 along the direction parallel to the top surface of the substrate;

a second supporting layer 27 covering the surface of the first supporting layer 26;

a capacitor hole 28 penetrates the first support layer 26 and the second support layer 27.

In some embodiments, the substrate comprises:

a substrate, in which a plurality of capacitance contact areas are provided, and a plurality of capacitance contact structures 20 are electrically connected with a plurality of capacitance contact areas one by one;

and an isolation layer 21 filled between adjacent capacitor contact structures 20.

In some embodiments, the first sub-layer 261 and the second sub-layer 262 are alternately stacked in a direction perpendicular to the top surface of the substrate.

In some embodiments, the material of the first sub-layer 261 includes a main constituent material and a doping element, and the material of the second sub-layer 262 includes the main constituent material and does not include the doping element.

In some embodiments, the material of the first sub-layer 261 includes silicon nitride and doping elements, and the material of the second sub-layer 262 is pure silicon nitride.

the width W1 of the first portion 281 is greater than the width W2 of the second portion 282, and the difference between the width W1 of the first portion 281 and the width W2 of the second portion 282 is less than or equal to 5nm.

According to the semiconductor structure and the forming method thereof, the first supporting layer is formed on the surface of the substrate, the first supporting layer is limited to comprise the first sub-layer and the second sub-layer which are alternately stacked, the first sub-layer is used for increasing the etching rate of the first supporting layer along the direction perpendicular to the top surface of the substrate, and the second sub-layer is used for reducing the etching rate of the first supporting layer along the direction parallel to the top surface of the substrate, so that in the process of forming the capacitor hole by etching, on one hand, the first supporting layer can be fully penetrated, the capacitor contact structure at the bottom of the first supporting layer is completely exposed, and the capacitor formed subsequently is ensured to be in stable and reliable contact with the capacitor contact structure; on the other hand, the lateral expansion of the bottom of the capacitor hole can be reduced, and the oversized bottom of the capacitor hole is avoided, so that leakage current is reduced, and the electrical performance of the semiconductor structure is improved.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application and are intended to be comprehended within the scope of the present application.

Claims

1. A method of forming a semiconductor structure, comprising the steps of:

forming a base, wherein the base comprises a substrate and a plurality of capacitance contact structures positioned on the substrate; forming a first support layer covering the top surface of the substrate, wherein the first support layer comprises a first sub-layer and a second sub-layer which are alternately stacked;

2. The method of forming a semiconductor structure of claim 1, wherein the forming a substrate comprises:

3. The method of claim 1, wherein the forming a first support layer overlying the top surface of the substrate comprises:

4. The method of forming a semiconductor structure of claim 3, wherein the specific step of forming the first sub-layer and the second sub-layer alternately stacked in a direction perpendicular to the top surface of the substrate comprises:

5. The method of forming a semiconductor structure of claim 3, wherein the specific step of forming the first sub-layer and the second sub-layer alternately stacked in a direction perpendicular to the top surface of the substrate comprises:

6. The method of claim 4 or 5, wherein the doping element is one or a combination of two or more of C, B, as, P.

7. The method of claim 6, wherein the doping element has a doping concentration of 5% to 65%.

8. The method of claim 1, wherein the capacitor hole comprises a first portion in the first support layer and a second portion in the second support layer;

9. A semiconductor structure, comprising:

10. The semiconductor structure of claim 9, wherein the substrate comprises:

11. The semiconductor structure of claim 9, wherein the first sub-layer and the second sub-layer are alternately stacked in a direction perpendicular to a top surface of the substrate.

12. The semiconductor structure of claim 11, wherein the material of the first sub-layer comprises a main constituent material and a doping element, and the material of the second sub-layer comprises the main constituent material and does not comprise the doping element.

13. The semiconductor structure of claim 11, wherein the material of the first sub-layer comprises silicon nitride and a doping element and the material of the second sub-layer is pure silicon nitride.

14. The semiconductor structure of claim 12 or 13, wherein the doping element is any one or a combination of two or more of C, B, as, P.

15. The semiconductor structure of claim 14, wherein a doping concentration of the doping element is between 5% and 65%.

16. The semiconductor structure of claim 9, wherein the capacitive aperture comprises a first portion in the first support layer and a second portion in the second support layer;