CN116032861A - Message processing method and device - Google Patents

Abstract

This application proposes a message processing method and device, including: when the information sending and receiving module receives the message packet, if the packet receiving queue is not congested, the information sending and receiving module writes the message header of the message packet into the first target address section, write the message body of the message packet into the second target address section; the information sending and receiving module writes the first address information and the second address information into the first target receiving packet descriptor; the information sending and receiving module receives the first target The packet descriptor is marked as occupied; after the processor processes the packet header corresponding to the occupied descriptor in the preset order, based on the first address information and the second address information corresponding to the packet descriptor Update the packet sending queue to complete packet forwarding. The delay for the processor to access the first memory is less than the delay for the processor to access the second memory. It can reduce the memory access delay of the processor, thereby improving the overall forwarding efficiency.

Description

A message processing method and device

technical field

The present application relates to the technical field of communications, and in particular, to a message processing method and device.

Background technique

With the advancement of science and technology, especially the advancement of communication technology, the receiving, processing and forwarding of data packets has attracted more and more attention. For example, with the rapid development of communication technology at present, people have higher and higher requirements for communication speed, which needs to have the characteristics of high speed. The extremely fast network speed can provide users with high-speed upload and download experience. Moreover, the communication network will also carry more and more rich services. On this basis, a large amount of data traffic will inevitably be generated, which poses higher requirements and challenges to the network forwarding and processing performance.

Therefore, how to improve the performance of network forwarding processing has become a difficult problem that those skilled in the art pay attention to.

Contents of the invention

The purpose of the present application is to provide a message processing method and device, so as to at least partially improve the above problems.

In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

In the first aspect, the embodiment of the present application provides a message processing method, which is applied to a message processing device, and the message processing device includes an information sending and receiving module, a processor, a first memory, and a second memory, and the second memory A packet receiving queue is set in the packet receiving queue, and the packet receiving queue includes a pre-configured packet receiving descriptor, and the method includes:

When the information transceiver module receives a message packet, if the packet receiving queue is in a non-crowded state, the information transceiver module writes the message header of the message packet into the first target address segment, and writes the The message body of the message packet is written into the second target address segment, wherein the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory;

The information transceiving module writes the first address information and the second address information into the first target receiving packet descriptor, wherein the first target receiving packet descriptor is any receiving packet currently in an idle state in the packet receiving queue Descriptor, the first address information is the identification information of the write address of the message header, and the second address information is the identification information of the write address of the message body;

The information transceiving module marks the first target receiving packet descriptor as an occupied state;

After the processor processes the packet headers corresponding to the packet receiving descriptors in the occupied state according to a preset order, update the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptors, to complete message forwarding.

In the second aspect, the embodiment of the present application provides a message processing method, which is applied to a message processing device, and the message processing device includes an information sending and receiving module, a processor, a first memory, and a second memory, and the second memory A packet sending queue is set in, and the packet sending queue includes a pre-configured packet sending descriptor, and the method includes:

After the processor processes the packet header of the receiving packet descriptor in the occupied state, writes the first address information and the second address information corresponding to the receiving packet descriptor into the first target sending packet descriptor;

Wherein, the first address information initially written into the first target sending packet descriptor belongs to the first memory, and the first address information is an identifier of the writing address of the packet header corresponding to the receiving packet descriptor information, the second address information is the identification information of the write address of the message body corresponding to the packet receiving descriptor, and the first target packet sending descriptor is any packet sending descriptor that is currently idle in the packet sending queue ;

The processor adjusts the first target send packet descriptor to an occupied state;

When the sending packet queue is in a congested state, the information transceiving module moves the message headers corresponding to the second target sending packet descriptor of the difference amount to the second memory, wherein the second target sending packet descriptor is in Sending descriptors that occupy the state and are sorted later;

The information transceiving module updates the first address information in the second target sending packet descriptor, and the updated first address information in the second target sending packet descriptor belongs to the second memory;

The information transceiving module forwards the packets of the packet sending descriptors in the occupied state in the packet sending queue based on a preset order.

In a third aspect, an embodiment of the present application provides a device, the device includes: an information transceiving module, a processor, a first memory, and a second memory, and the device can execute the above message processing method.

Compared with the prior art, the message processing method and device provided by the embodiment of the present application include: when the information sending and receiving module receives the message packet, if the packet receiving queue is in a non-congested state, the information sending and receiving module sends the message packet The message header of the packet is written into the first target address segment, and the message body of the message packet is written into the second target address segment, wherein the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory ; The information transceiving module writes the first address information and the second address information into the first target receiving packet descriptor, wherein the first target receiving packet descriptor is any receiving packet descriptor currently in an idle state in the packet receiving queue, The first address information is the identification information of the write address of the message header, and the second address information is the identification information of the write address of the message body; the information transceiver module marks the first target receiving packet descriptor as an occupied state; the processor After processing the packet headers corresponding to the packet receiving descriptors in the occupied state according to the preset sequence, the packet sending queue is updated based on the first address information and the second address information corresponding to the packet receiving descriptors, so as to complete packet forwarding. The delay for the processor to access the first memory is less than the delay for the processor to access the second memory. It can reduce the memory access delay of the processor, thereby improving the overall forwarding efficiency.

In order to make the above-mentioned purpose, features and advantages of the present application more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, so It should be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a message processing device provided in an embodiment of the present application;

FIG. 2 is one of the schematic flow charts of the message processing method provided by the embodiment of the present application;

FIG. 3 is the second schematic flow diagram of the message processing method provided by the embodiment of the present application;

FIG. 4 is the third schematic flow diagram of the message processing method provided by the embodiment of the present application;

FIG. 5 is the fourth schematic flow diagram of the message processing method provided by the embodiment of the present application;

FIG. 6 is the fifth schematic flow diagram of the message processing method provided by the embodiment of the present application;

FIG. 7 is a sixth schematic flowchart of a packet processing method provided by an embodiment of the present application.

In the figure: 10-information transceiver module; 20-processor; 30-first memory; 40-second memory.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer" etc. is based on the orientation or positional relationship shown in the drawings, or the The usual orientation or positional relationship of the application product when used is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, therefore It should not be construed as a limitation of the application.

In the description of this application, it should also be noted that, unless otherwise clearly stipulated and limited, the terms "setting" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection, or Integral connection; it can be mechanical connection or electrical connection; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

Some implementations of the present application will be described in detail below in conjunction with the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

An embodiment of the present application provides a packet processing device, such as a router device or an intelligent network card device. Please refer to FIG. 1 , which is a schematic structural diagram of a message processing device. The message processing device comprises an information transceiving module 10, a processor 20, a first memory 30 and a second memory 40, and the processor 20 is respectively connected to the information transceiving module 10, the first memory 30 and the second memory 40 in communication, and the information transceiving module 10 They are respectively connected in communication with the first memory 30 and the second memory 40 . Optionally, the information transceiving module 10, the processor 20, the first memory 30 and the second memory 40 are connected through a bus. The first memory 30 is, for example, a static random access memory (SRAM for short), and the second memory 40 is, for example, a dynamic random access memory (also called a memory or DRAM). The second memory 40 may specifically choose DDR. The latency for the processor 20 to access the first memory 30 is less than the latency for the processor 20 to access the second memory 40 .

The processor 20 can be a central processing unit (Central Processing Unit, referred to as CPU), a network processor (Network Processor, referred to as NP), etc.; it can also be a digital signal processor (Digital Signal Processor, referred to as DSP), an application-specific integrated circuit (Application Specific Integrated Circuit (ASIC for short), Field Programmable Gate Array (Field-Programmable Gate Array, FPGA for short) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

The information transceiving module 10 may be a hardware device, such as a Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA for short) or a network card. It should be understood that the information transceiving module 10 can directly access the first memory 30 and the second memory 40 .

In an optional scenario, the workflow of the packet processing device provided in the embodiment of the present application is as follows.

In the first step, the information transceiving module 10 completes the line side message receiving and sending;

In the second step, the information transceiver module 10 stores the message into the DDR;

In the third step, the processor 20 perceives the packet reception through software;

In the fourth step, the processor 20 parses the message through software;

In the fifth step, the processor 20 performs business table lookup through software;

In the sixth step, the processor 20 performs business processing through software (such as flow learning, statistics, in-depth analysis, security policies, encryption and decryption, etc.);

In the seventh step, the processor 20 performs forwarding decision-making (for example, determining the forwarding network port) through software;

In the eighth step, the processor 20 edits the message through software (for example, editing the message header);

In the ninth step, the processor 20 issues the processed message through the software, and completes the message sending through the information sending and receiving module 10 .

In the above process, after the message is received, it needs to be identified based on the message header information, and then the software looks up the table and forwards it. The message header is usually in a storage device, such as DDR, which is a type of DRAM. There is a delay in accessing the DRAM by the processor 20 (CPU). If the packet rate to be processed is high, for example reaching the Mpps level, the CPU access delay is a key point affecting the forwarding performance.

In an optional scenario, in order to improve the forwarding efficiency, some key services can be offloaded to the hardware (information transceiving module 10) for execution, and the information transceiving module 10 completes matters such as parsing table lookup messages and editing.

However, routers have large service specifications, and hardware entries are usually stored in SRAM, resulting in high hardware costs. And this method can only offload some services. For example, the access router hardware entries are usually below the MB (million byte) level, and a large number of service entries are still on the DDR. The entries on the DDR can easily reach M/even G level, most services can only be sent to the CPU for processing, resulting in low overall forwarding efficiency.

In order to overcome the above problems, the embodiment of the present application provides a message processing method, which is based on the message forwarding architecture of the front and rear first memory 30 and the second memory 40, and cooperates with the CPU Core dedicated to receiving packets to perform packet receiving or sending tasks Distribution can effectively improve the overall performance of soft forwarding.

In the embodiment of the present application, the second memory 40 is provided with a packet receiving queue and a packet sending queue, the packet receiving queue includes a preconfigured packet receiving descriptor, and the packet sending queue includes a preconfigured packet sending descriptor.

Optionally, a queue space is set in the first memory 30, which may be a circular queue (Ring Buffer), and is used to store a header of a part of the packet.

It should be understood that the structure shown in FIG. 1 is only a schematic structural diagram of a part of the message processing device, and the message processing device may also include more or less components than those shown in FIG. different configurations. Each component shown in Fig. 1 may be implemented by hardware, software or a combination thereof.

A message processing method provided in the embodiment of the present application can be applied to, but not limited to, the message processing device shown in Figure 1. For the specific process, please refer to Figure 2. The message processing method includes: S115, S117, S118, and S211, specifically described as follows.

S115, when the information sending and receiving module receives the message packet, if the packet receiving queue is in a non-crowded state, the information sending and receiving module writes the message header of the message packet into the first target address segment, and writes the message body of the message packet Enter the second target address segment.

Wherein, the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory.

It should be noted that when the processor 20 performs service processing, it only needs to edit the packet header in the packet. The information transceiving module 10 writes the packet header into the first target address segment in the first memory 30 , and writes the message body of the packet into the second target address segment in the second memory 40 . When processing, the processor 20 can directly access the first memory 30 without accessing the second memory 40 , because the delay for the processor 20 to access the first memory 30 is shorter than the delay for the processor 20 to access the second memory 40 . Therefore, through S115, the memory access delay of the processor 20 can be reduced, thereby improving the overall forwarding efficiency.

In a possible scenario, when the message packet is short, it may be necessary to store the corresponding message header, but the message body does not need to be stored, so the second destination address segment can be configured as empty.

S117. The information transceiving module writes the first address information and the second address information into the first target packet receiving descriptor.

Wherein, the first target packet receiving descriptor is any packet receiving descriptor that is currently idle in the packet receiving queue, the first address information is the identification information of the write address of the message header, and the second address information is the message body The identification information of the write address.

Optionally, a certain number of packet receiving descriptors are pre-configured in the packet receiving queue, and each packet receiving descriptor is set with a first field and a second field, the first field is used to fill in the first address information, and the second field Used to fill in the second address information. So that the processor 20 can obtain the packet header corresponding to the packet receiving descriptor through the first address information when performing service processing. The second address information is used to obtain the message body (body) during forwarding.

Optionally, the first address information may be the start address of the storage address segment used to store the message header, and the second address information may be the start address of the storage address segment used to store the message body. When the packet receiving queue is in a non-congested state, the written first address information belongs to the first memory 30, and when the packet receiving queue is in a crowded state, the written first address information may belong to the second memory 40, See below for details. Since the processor 20 does not need to use the message body during service processing, the written second address information belongs to the second memory 40 no matter what state the packet receiving queue is in.

Optionally, the information transceiving module 10 may access the packet receiving queue, and then know the current state of each packet receiving descriptor in the packet receiving queue. Optionally, after determining the last packet receiving descriptor in the packet receiving queue that is switched to the occupied state, the information transceiving module 10 determines the first packet receiving descriptor that is in the idle state behind it as the first target receiving descriptor. package descriptor.

Optionally, each receiving packet descriptor is provided with a third field, and the third field is used to store the offset, the offset between the actual write address of the message header and the starting address of the storage address segment storing the message header. displacement. It should be understood that when the processor 20 edits the message header, the length of the message header may change, such as becoming longer or shorter, so it is necessary to reserve a certain space in the storage address segment for storing the message header, that is, the offset.

By writing the offset into the first target packet receiving descriptor, it is convenient for the CPU to quickly determine the beginning of the packet header during processing.

Optionally, the first offset represents the offset between the actual write address of the message header and the first start address; the second offset represents the actual write address of the processed message header and the first start address offset.

S118. The information transceiving module marks the first target packet receiving descriptor as occupied.

Optionally, the purpose of marking the first target packet receiving descriptor as an occupied state is to inform the processor 20 that the information stored in the address segment of the first target packet receiving descriptor needs to be processed for packet receiving.

S211. After the processor processes the packet headers corresponding to the packet receiving descriptors in the occupied state according to the preset sequence, it updates the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptors, so as to complete Packet forwarding.

Optionally, the information transceiving module 10 may send the first type of trigger instruction to the processor 20 after updating the status of a received packet descriptor. The processor 20 (CPU) can determine whether there is an occupied packet receiving descriptor in the packet receiving queue when receiving the first type of trigger instruction or according to one cycle, and if so, process it.

It should be understood that when the processor 20 is processing, it can directly access the first memory 30 without accessing the second memory 40, because the time delay for the processor 20 to access the first memory 30 is shorter than the time for the processor 20 to access the second memory 40 delay. The memory access delay of the processor 20 can be reduced, thereby improving the overall forwarding efficiency.

Optionally, the packet sending queue is updated based on the first address information, the second address information and the second offset corresponding to the packet receiving descriptor, so as to complete packet forwarding.

To sum up, the embodiment of the present application provides a message processing method, including: when the information sending and receiving module receives the message packet, if the packet receiving queue is in a non-congested state, the information sending and receiving module sends the message of the message packet The header is written into the first target address segment, and the message body of the message packet is written into the second target address segment, wherein the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory; the information transceiver module Write the first address information and the second address information into the first target packet receiving descriptor, wherein the first target packet receiving descriptor is any packet receiving descriptor that is currently idle in the packet receiving queue, and the first address information It is the identification information of the write address of the message header, and the second address information is the identification information of the write address of the message body; the information sending and receiving module marks the first target receiving packet descriptor as an occupied state; After sequentially processing the packet headers corresponding to the packet receiving descriptors in the occupied state, the packet sending queue is updated based on the first address information and the second address information corresponding to the packet receiving descriptors, so as to complete packet forwarding. The delay for the processor to access the first memory is less than the delay for the processor to access the second memory. It can reduce the memory access delay of the processor, thereby improving the overall forwarding efficiency.

Optionally, regarding how to complete writing of message information when a message is received, this embodiment of the present application also provides an optional implementation manner, please refer to FIG. 3 , the message processing method further includes: S111, S112, S113, S114 and S116 are specifically described as follows.

S111. When the information sending and receiving module receives the packet, the information sending and receiving module determines whether the packet receiving queue is in a crowded state. If yes, execute S113; if not, execute S112.

Optionally, a status flag can be set on the packet receiving queue to indicate whether the packet receiving queue is in a congested state, and the information transceiving module 10 can determine whether it is in a congested state by reading the status flag, without repeatedly calculating the threshold Compare.

If it is in a crowded state, it means that the header information stored in the first memory 30 (SRAM) is more, in order to avoid excessive occupation of the resources of the first memory 30, the header needs to be stored in the second memory 40 (internal memory, DRAM) ), so execute S113. If it is in a non-congested state, in order to save the memory access delay of the processor 20 when performing business processing, the packet header may be directly stored in the first memory 30, that is, S112 is executed.

S112. The information transceiving module determines the first target address segment in the first memory as the write address of the packet header.

Optionally, an address manager is also provided in the message processing device, and the address manager can query the packet receiving queue and the packet sending queue, and determine whether the address occupied by it has been returned based on the state of the packet receiving descriptor and the packet sending descriptor therein , and then a free address segment in the first memory 30 can be determined and used as the first target address.

S113. The information transceiving module determines the third target address segment in the second memory as the write address of the packet header.

Optionally, the address manager can query the packet receiving queue and the packet sending queue, and determine whether the occupied address has been returned based on the state of the packet receiving descriptor and the packet sending descriptor therein, and then can determine the idle address in the second memory 40. The address segment is used as the third target address.

S114. The information transceiving module determines the second target address segment in the second memory as the write address of the message body.

Optionally, when the address manager receives the address distribution request corresponding to the information transceiving module 10, it may send the corresponding first target address segment, second target address segment, and third target address segment to it.

It should be noted that S114 may be executed directly when the message is received, or may be executed before S112 or S113, or may be executed synchronously therewith, and the execution sequence thereof is not limited here. After executing S112 and S114, execute S115; after executing S113 and S114, execute S116.

S116. The information transceiving module writes the message header of the message packet into the third target address segment, and writes the message body of the message packet into the second target address segment.

It should be understood that, when in a crowded state, the information transceiving module 10 writes the message header of the message packet into the third target address segment, and writes the message body of the message packet into the second target address segment, so as to avoid excessive occupation space in the first memory 30 .

When the packet receiving queue is in a congested state, regarding how to further reduce the delay, the embodiment of the present application also provides an optional implementation, please refer to Figure 4, in the case of a congested packet receiving queue, the message processing The method also includes: S121 and S122, specifically described as follows.

S121. If the processor updates the packet receiving descriptor in the occupied state to the idle state, the information transceiving module moves the packet header corresponding to the second target packet receiving descriptor from the second memory to the first memory.

Wherein, the second target packet receiving descriptor is a descriptor stored in the corresponding packet header and stored in the second memory.

Optionally, the processor 20 updates the packet receiving descriptor in the occupied state to the idle state, that is, the processor 20 returns any packet receiving descriptor when the packet receiving queue is in a crowded state, and at this time, the second target receiving The packet header corresponding to the packet descriptor is moved from the second memory 40 to the first memory 30 . Specifically, the transfer target address may be acquired by the information transceiving module 10 upon request from the address manager.

It should be understood that after the move, the original occupied address of the packet header corresponding to the second target receiving packet descriptor in the second memory 40 is released and returned, and is in an idle state.

S122. The information transceiving module updates the first address information in the second target packet receiving descriptor.

Optionally, the first address information in the second target receiving packet descriptor is changed from the identification information of the original occupied address to the identification information of the moving target address.

It should be understood that as the processor 20 updates the receiving packet descriptor in the occupied state to the idle state, the information transceiving module 10 will move the packet headers corresponding to all the second target receiving packet descriptors from the second memory 40 to the first memory 30. Therefore, when the processor 20 performs business processing, it always accesses the first memory 30, thereby reducing the time delay and improving the overall forwarding efficiency.

5. It should be understood that at the initial moment, the packet receiving queue is in a non-congested state. Regarding how to switch the packet receiving queue, this embodiment of the present application also provides a possible implementation. Please refer to FIG. 5. The message processing method also includes: S131 and S132, specifically described as follows.

S131. When the packet receiving queue is in a non-congested state, the information transceiving module marks the packet receiving queue as a congested state when the monitored amount is greater than a preset first threshold.

0 Wherein, the monitoring amount is the number of packet receiving descriptors in the occupied state in the packet receiving queue, or the number of packet headers stored in the first memory, or the number of storage units occupied by the packet. The first threshold can be a global configuration or a per queue configuration.

It should be understood that, when the packet receiving queue is in a non-congested state, all packet headers are written into the first memory 30 .

S132. When the packet receiving queue is in a congested state, the information transceiving module marks the packet receiving queue as a non-congested state when the packet header corresponding to the packet receiving descriptor is not stored in the second memory.

Optionally, when the packet receiving queue is in a congested state, all newly received headers are written into the second memory 40. After the successive moves of S121, when the packet receiving description is not stored in the second memory 40 When the packet header corresponding to the symbol is used, the packet receiving queue is marked as non-congested.

It should be noted that, in the embodiment of the present application, the message body may be stored in a continuous space on the second memory 40, or in multiple spaces (link-list of addresses). When stored in multiple spaces, the second address information corresponding to the packet receiving descriptor may include a plurality of sub-information, and each sub-information represents identification information of a space.

Optionally, corresponding RingBuffers are set in the first memory 30 and the second memory 40 according to packet receiving queues for storing packet headers. The Ring Buffer can be divided into a preset number of sub-segments, the idle sub-segments in the first memory 30 can be used as the first target address segment, and the idle sub-segments in the second memory 40 can be used as the third target address segment. In this embodiment of the application, the message header and the message body are stored separately. Each sub-section is set with a reserved space (Headroom), that is, the offset. When the packet is received and written to the header, the header is written from the headroom.

Optionally, the embodiment of the present application further provides a message processing method. Please refer to FIG. 6 . The message processing method further includes: S221, S222, S143, S144, and S146, which are described in detail as follows.

S221. After the processor processes the packet header of the packet receiving descriptor in the occupied state, writes the first address information and the second address information corresponding to the packet receiving descriptor into the first target sending packet descriptor.

Wherein, the first address information initially written in the first target sending packet descriptor belongs to the first memory, the second address information belongs to the second memory, and the first address information is the write address of the message header corresponding to the receiving packet descriptor. The identification information, the second address information is the identification information of the write address of the message body corresponding to the receiving packet descriptor, and the first target sending packet descriptor is any sending packet descriptor that is currently idle in the sending packet queue.

Optionally, the processor 20 may access the packet sending queue, and then know the current state of each packet sending descriptor in the packet sending queue. Optionally, after the processor 20 determines the latest packet sending descriptor switched to the occupied state in the packet sending queue, it determines the first packet sending descriptor that is in the idle state behind it as the first target packet sending descriptor.

Optionally, the packet sending descriptor is also provided with a first field, a second field and a third field, whose functions are the same as those of the first field, second field and third field in the above packet receiving descriptor.

It should be understood that the first address information initially written by the processor 20 into the first field of the first target send packet descriptor belongs to the first memory. That is, the initial packet headers are all stored in the first memory 30 .

In a possible implementation manner, the processor 20 also writes the second offset into the third field of the first target send packet descriptor.

Optionally, the processor 20 also writes the forwarding decision (forwarding network port) into the fourth field of the first target sending packet descriptor.

S222. The processor adjusts the first target sending descriptor to an occupied state.

Optionally, the purpose of adjusting the first target packet sending descriptor to the occupied state is to facilitate notifying the information transceiving module 10 that the information stored in the address segment of the first target sending packet descriptor needs to be sent a packet.

It should be understood that the information transceiving module 10 will perform packet sending processing on the packet sending descriptors in the occupied state according to the order in which they are arranged in the packet sending queue. However, the packet sending speed of the information transceiving module 10 may be lower than the packet receiving speed of the processor 20, which may cause the packet sending queue to be in a congested state. If this state is ignored, the space in the first memory 30 may be over-occupied, resulting in the inability to write a newly received message into the first memory 30, so that the processor 20 cannot process subsequent messages. In order to overcome this problem, it is necessary to execute S143.

S143. When the packet sending queue is in a crowded state, the information sending and receiving module moves the message headers corresponding to the second target sending packet descriptors with a difference amount to the second memory.

It should be understood that the packet headers corresponding to the second target sending packet descriptors of the difference amount are moved from the first memory 30 to the second memory 40 . The space of the first memory 30 can be released for receiving new message information, so that the processor 20 can continue to process subsequent messages.

Optionally, under what circumstances will the information transceiving module 10 determine that the packet sending queue is in a congested state, and this embodiment of the present application also provides a possible implementation. The information transceiving module 10 may query the packet sending queue according to a predetermined period, and determine its status by polling everything.

It should be understood that non-stop polling will occupy the hardware resources of the information transceiving module 10. In order to avoid occupying hardware resources, the embodiment of the present application also provides a possible implementation method, which may be that the processor 20 is executing S222 to update the packet sending description After the symbol, send the second type of trigger instruction to the information transceiving module 10, so that the information transceiving module 10 can determine whether the packet sending queue is in a crowded state.

In a possible scenario, the second type of trigger instruction also includes the number of currently updated packet sending descriptors; furthermore, the information transceiving module 10 can determine the amount of difference based on the current update amount and the number of original remaining unsent packet sending descriptors , and move the difference quantity of the lower sort to the second memory 40 .

It should be understood that the destination address of the transfer may be the destination address of the difference amount allocated by the address manager after the information transceiving module 10 sends a request to the address manager.

S144. The information transceiving module updates the first address information in the second target packet sending descriptor, and the updated first address information in the second target packet sending descriptor belongs to the second memory.

Wherein, the second target packet sending descriptor is a packet sending descriptor that is in an occupied state and is sorted lower.

It should be understood that in order to ensure the correctness of the content of the packet, the first address information in the second target packet descriptor needs to be updated, specifically, the original first address information in the first field will be replaced with the newly allocated destination address , the updated first address information in the second target sending packet descriptor belongs to the second memory.

Optionally, after the update is completed, the space of the first memory 30 may be released, and the originally occupied address space becomes free and available, and the address manager may allocate it again. For example, it is used to receive new message information, so that the processor 20 can continue to process subsequent messages.

S146. The information transceiving module forwards the packets of the packet sending descriptors in the occupied state in the packet sending queue based on the preset sequence.

Optionally, after the message forwarding is completed, the occupied space in the corresponding first memory 30 or the second memory 40 can be returned, and the originally occupied address space becomes free and available, and the address manager can allocate it again .

On the basis of FIG. 6 , this embodiment of the present application also provides an optional implementation manner. Referring to FIG. 7 , the message processing method further includes: S141 , S142 and S145 , which are described in detail as follows.

S141. The information transceiving module determines whether the number of third target packet sending descriptors in the packet sending queue is greater than a preset second threshold. If yes, execute S142; if not, execute S145.

Wherein, the third target packet sending descriptor is a packet sending descriptor that is in an occupied state and whose corresponding packet header is stored in the first memory. The second threshold may be a global configuration or a per queue configuration, and of course, may also be a fixed value.

Optionally, S141 is not necessarily executed after S222, and S141 may be executed when the information transceiving module 10 receives the second type of trigger instruction.

S142. Determine that the packet sending queue is in a congested state.

S145. Determine that the packet sending queue is in a non-congested state.

After S142, execute S143, and after S145, directly execute S146.

Optionally, S146 is independent from the preceding steps. Regardless of whether the information is moved or not, the information transceiving module 10 will forward packets based on the preset sequence to the packet sending descriptors in the packet sending queue that are occupied.

It should be understood that the message processing method provided in the present application is assisted by application specific integrated circuit hardware (Application Specific Integrated Circuit, ASIC). (SRAM), after the CPU finishes filling out the packet sending DMA TX descriptor, the hardware automatically releases the SRAM space where the packet header is located. It can effectively reduce the memory access delay when the CPU processes packets and reduce the CPU waiting time, thereby greatly improving the soft forwarding efficiency and increasing the overall forwarding bandwidth.

A packet processing device, such as a router device or an intelligent network card device, is provided below. As shown in FIG. 1 , the message processing device can implement the above message processing method; specifically, the message processing device includes: an information transceiving module 10 , a processor 20 , a first memory 30 and a second memory 40 . Processor 20 may be a CPU. The packet processing device may execute the packet processing method in the foregoing embodiments.

In the embodiments provided in this application, it should be understood that the disclosed devices and methods may also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functions and possible implementations of devices, methods and computer program products according to multiple embodiments of the present application. operate. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or part of code that includes one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

In addition, each functional module in each embodiment of the present application may be integrated to form an independent part, each module may exist independently, or two or more modules may be integrated to form an independent part.

If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc., which can store program codes. .

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.

It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, but that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and not restrictive in all points of view, and the scope of the application is defined by the appended claims rather than the foregoing description, and it is intended that the scope of the present application be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in this application. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. A message processing method, characterized in that it is applied to a message processing device, and the message processing device includes an information transceiver module, a processor, a first memory and a second memory, and the second memory is provided with A packet receiving queue, the packet receiving queue includes a pre-configured packet receiving descriptor, and the method includes: When the information transceiver module receives a message packet, if the packet receiving queue is in a non-crowded state, the information transceiver module writes the message header of the message packet into the first target address segment, and writes the The message body of the message packet is written into the second target address segment, wherein the first target address segment belongs to the first memory, and the second target address segment belongs to the second memory; The information transceiving module writes the first address information and the second address information into the first target receiving packet descriptor, wherein the first target receiving packet descriptor is any receiving packet currently in an idle state in the packet receiving queue Descriptor, the first address information is the identification information of the write address of the message header, and the second address information is the identification information of the write address of the message body; The information transceiving module marks the first target receiving packet descriptor as an occupied state; After the processor processes the packet headers corresponding to the packet receiving descriptors in the occupied state according to a preset order, update the packet sending queue based on the first address information and the second address information corresponding to the packet receiving descriptors, to complete message forwarding. 2. The message processing method according to claim 1, wherein the method further comprises: When the information transceiver module receives a message packet, the information transceiver module determines whether the packet receiving queue is in a crowded state; If the packet receiving queue is in a non-congested state, the information transceiving module determines the first target address segment in the first memory as the write address of the packet header; The information transceiving module determines the second target address segment in the second memory as the write address of the message body. 3. The message processing method according to claim 2, wherein the method further comprises: If the packet receiving queue is in a crowded state, the information transceiving module determines the third target address segment in the second memory as the write address of the message header; The information transceiving module determines the second target address segment in the second memory as the write address of the message body; The information transceiving module writes the message header of the message packet into the third target address segment, and writes the message body of the message packet into the second target address segment. 4. The message processing method according to claim 3, wherein, when the packet receiving queue is in a crowded state, the method further comprises: If the processor updates the receiving packet descriptor in the occupied state to the idle state, the information sending and receiving module moves the packet header corresponding to the second target receiving packet descriptor from the second memory to the first a memory; The information transceiving module updates the first address information in the second target packet receiving descriptor. 5. The message processing method according to claim 1, wherein, when the packet receiving queue is in a non-crowded state, the method further comprises: The information transceiving module marks the packet receiving queue as a congested state when the monitored amount is greater than a preset first threshold, wherein the monitored amount is the number of packet receiving descriptors in the occupied state in the packet receiving queue The quantity is either the quantity of packet headers stored in the first memory, or the quantity of storage units occupied by the packet. 6. The message processing method according to claim 5, wherein, when the packet receiving queue is in a crowded state, the method further comprises: The information transceiving module marks the packet receiving queue as a non-congested state when the packet header corresponding to the packet receiving descriptor is not stored in the second memory. 7. A message processing method, characterized in that it is applied to a message processing device, and the message processing device includes an information transceiver module, a processor, a first memory and a second memory, and the second memory is provided with A packet sending queue, the packet sending queue includes a pre-configured packet sending descriptor, and the method includes: After the processor processes the packet header of the receiving packet descriptor in the occupied state, writes the first address information and the second address information corresponding to the receiving packet descriptor into the first target sending packet descriptor; Wherein, the first address information initially written into the first target sending packet descriptor belongs to the first memory, and the first address information is an identifier of the writing address of the packet header corresponding to the receiving packet descriptor information, the second address information is the identification information of the write address of the message body corresponding to the packet receiving descriptor, and the first target packet sending descriptor is any packet sending descriptor that is currently idle in the packet sending queue ; The processor adjusts the first target send packet descriptor to an occupied state; When the sending packet queue is in a congested state, the information transceiving module moves the message headers corresponding to the second target sending packet descriptor of the difference amount to the second memory, wherein the second target sending packet descriptor is in Sending descriptors that occupy the state and are sorted later; The information transceiving module updates the first address information in the second target sending packet descriptor, and the updated first address information in the second target sending packet descriptor belongs to the second memory; The information transceiving module forwards the packets of the packet sending descriptors in the occupied state in the packet sending queue based on a preset sequence. 8. The message processing method according to claim 7, characterized in that, before moving the message headers corresponding to the second target sending packet descriptors of the difference amount to the second memory, the method further comprises : The information transceiving module determines that the packet sending queue is in a congested state when the number of third target sending packet descriptors in the sending packet queue is greater than a preset second threshold; Wherein, the third target packet sending descriptor is a packet sending descriptor that is in an occupied state and whose corresponding packet header is stored in the first memory. 9. The message processing method according to claim 8, wherein the method further comprises: When the information transceiving module is in the non-congested state in the packet sending queue, the information sending and receiving module directly forwards the packets of the packet sending descriptors in the occupied state in the packet sending queue based on a preset order. 10. A message processing device, characterized in that it comprises: an information transceiving module, a processor, a first memory, and a second memory, and the message processing is used to execute the method described in any one of claims 1-9. Packet processing method.

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