CN102098221A - Message query method and device - Google Patents
Message query method and device Download PDFInfo
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- CN102098221A CN102098221A CN2011100316087A CN201110031608A CN102098221A CN 102098221 A CN102098221 A CN 102098221A CN 2011100316087 A CN2011100316087 A CN 2011100316087A CN 201110031608 A CN201110031608 A CN 201110031608A CN 102098221 A CN102098221 A CN 102098221A
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Abstract
The embodiment of the invention provides a message query method and device. The message query method comprises the steps: receiving a message and writing the message into a cache; sending a message query request which comprises the address information of a message header of the message in the cache; receiving a feedback query result, and acquiring the address information of the message header of the message in the cache in the query result; and reading the message from the cache according to the address information of the message header of the message in the cache. The embodiment of the invention supports a bybass scene in multi-flow cache management and simplifies the complexity of logic design. Compared with linked list management, the invention removes the idle address cache and linked list pointer cache, thus saving resources, reducing the read-write operation of an internal memory and being in accordance with the demand of low power consumption.
Description
Technical field
The present invention relates to communication technique field, relate in particular to a kind of message querying method and device.
Background technology
The basic object that router chip is handled is exactly a message, according to the priority difference, or is the type of message difference under a lot of situations, message can be divided into multiple stream.
The all types message can be shared with a slice inner buffer, and analytic message type and do different processing query requests according to type when message is write buffer memory can be postponed behind the request return results to be checked and be read message in depositing and do respective handling.Below we are called for short dissimilar messages and are homogeneous turbulence not, query requests is REQ, returning Query Result is RES.
Write buffer memory by message and initiate REQ in proper order, REQ handles needs a period of time can return RES, and handling duration is unfixing, within the specific limits fluctuation.REQ_RES between the same stream is order-preserving, promptly sends out the message of REQ earlier, obtains RES earlier.REQ_RES between the various flows is out of order, sends out REQ earlier such as the message of stream 1, sends out REQ behind the message of stream 2, and the message of stream 2 may obtain RES earlier.Same stream needs to return the sequential processes message by RES.Message between the various flows does not need order-preserving.When certain bar stream is handled REQ, may be forced to processing by another kind stream.Below this scene Bypass (force conversion) that abbreviates stream as handle.Because the REQ_RES between the various flows is out of order, this just cause write buffer memory earlier message may after the situation of reading.
For the cache management of multithread scheme commonly used now promptly is the chained list management, and each bar stream is safeguarded a chained list separately, and the address of each message in buffer memory in the stream formed catena in proper order by writing buffer memory.First message of linked list head pointed catena.When returning RES, judge stream type, obtain the address of message in buffer memory, read message, simultaneously with next jumping of linked list head pointed catena from the head pointer of corresponding chained list.Follow-up RES processing and the like.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art: the shortcoming of chained list Managed Solution maximum is to handle the pressure conversion of stream type.Illustrate: suppose stream 1 with stream 2 (two kinds of flow priorities are different) respectively safeguard a chained list, message 1,2,3,4,5,6 writes buffer memory successively, message 1 belong to stream 1, the initiation REQ1; Message 2 also belongs to stream 1, initiates REQ2.Flow 1 message processing module (MPM) and obtain REQ1, REQ2 successively, but REQ2 is stream 2 by Bypass, walk by stream 2 handling processes, because the not order-preserving of REQ_RES between the various flows, REQ2 replys RES2 and may return before RES1, the head pointer that flow 1 chained list this moment is not corresponding with the message of RES2, and the chained list management can't be handled this scene.It is many that another shortcoming of chained list Managed Solution takies resource exactly, need safeguard Free_addr_list of additional maintenance (depositing idle address) and chained list shared buffer memory (depositing the chain list index), relatively also increase the read-write operation of Memory (internal memory), strengthened power consumption.
Summary of the invention
The embodiment of the invention provides a kind of message querying method and device, the Bybass scene when supporting many stream cache managements, and simplify the logical design complexity.
On the one hand, the embodiment of the invention provides a kind of message querying method, and described method comprises: receive message and described message is write buffer memory; Send the query requests of described message, described query requests comprises the address information of heading in described buffer memory of described message; Receive the Query Result of feedback, obtain the address information of heading in described buffer memory of the described message that comprises in the described Query Result; According to the address information of heading in described buffer memory of described message, from described buffer memory, read described message.
On the other hand, the embodiment of the invention provides a kind of message inquiry unit, and described device comprises: writing unit is used to receive message and described message is write buffer memory; Transmitting element is used to send the query requests of described message, and described query requests comprises the address information of heading in described buffer memory of described message; Receiving element is used to receive the Query Result of feedback, obtains the address information of heading in described buffer memory of the described message that comprises in the described Query Result; Reading unit is used for reading described message according to the heading of the described message address information at described buffer memory from described buffer memory.
Technique scheme has following beneficial effect: receive message and described message is write buffer memory because adopt; Send the query requests of described message, described query requests comprises the address information of heading in described buffer memory of described message; Receive the Query Result of feedback, obtain the address information of heading in described buffer memory of the described message that comprises in the described Query Result; According to the address information of heading in described buffer memory of described message, from described buffer memory, read the technological means of described message, thus support the Bybass scene of many streams during cache managements, and simplified the logical design complexity.With respect to chained list management, removed idle address caching and chain list index buffer memory, saved the read-write operation that resource also reduces internal memory, meet the low-power consumption demand.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of message querying method of embodiment of the invention flow chart;
Fig. 2 writes schematic diagram for embodiment of the invention buffer memory;
Fig. 3 sends out the REQ schematic diagram for embodiment of the invention receiving literary composition back;
Fig. 4 is that the REQ schematic diagram is sent out in another receiving literary composition back of the embodiment of the invention;
Fig. 5 is a kind of message inquiry unit of embodiment of the invention structural representation;
Fig. 6 is the another kind of message inquiry unit of an embodiment of the invention structural representation.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
As shown in Figure 1, be a kind of message querying method of embodiment of the invention flow chart, described method comprises:
101, receive message and described message write buffer memory.
102, send the query requests of described message, described query requests comprises the address information of heading in described buffer memory of described message.
Be the convenient cache management scheme of describing, can set an application scenarios earlier: as shown in Figure 2, for embodiment of the invention buffer memory writes schematic diagram.
1, case of internal buffer memory bit wide is 32B (Byte), 512 addresses of the degree of depth, and total capacity is 16KB;
2, the inlet message length is unfixing, and length range is 20B～9.6KB;
3, the inlet message according to priority difference be divided into 4 kinds of streams, stream 0～stream 3.
Optionally, described register can be the register of one group of 512bit.Described message with reception writes buffer memory, can comprise: when the message that will receive write buffer memory, (First In First Out, mode FIFO) write buffer memory with described message according to the first in first out buffer memory.In addition, write buffer memory, write completely and can overturn with the circulation of address ascending order.Since when writing message according to the FIFO mode, address ascending order circulation writes, write and carry the address of heading in buffer memory when sending REQ behind the message, and with the RES return address, need not safeguard that thus chained list can guarantee the one-to-one relationship of message and RES, support stream Bypass scene, no matter how out of order also unaffected REQ and RES be.
Optionally, described message is write a address in the buffer memory, represent that with the form of map addresses dot chart (Bitmap) buffer address takies Bitmap position corresponding with described address in the register of situation and is set to 1, account for, do not allow to write again to indicate this address.Because the write address of packet buffer is pressed the management of FIFO formula, is chaotic but read the address, can not simply calculate the buffer memory remaining space by the read-write number of times, can cause write port whether to allow to write in the perception current address.For addressing this problem, introduce BitMap formula address assignment in the scheme.BitMap is corresponding one by one with the address that message writes in the buffer memory, is that 0 expression is idle, allows to write, and is that 1 expression takies, and taboo writes.
103, receive the Query Result of feedback, obtain the address information of heading in described buffer memory of the described message that comprises in the described Query Result.
As shown in Figure 3, send out the REQ schematic diagram for embodiment of the invention receiving literary composition back, hptr wherein is the address of heading in buffer memory of message, carries the address of this heading in buffer memory when sending out REQ, when returning RES this heading address is returned simultaneously.
104, according to the address information of heading in described buffer memory of described message, from described buffer memory, read described message.
Optionally, the described address information of heading in described buffer memory according to described message, from described buffer memory, read described message after, described method can also comprise: with Bitmap position zero clearing corresponding with described address in the described register.
As shown in Figure 4, send out REQ schematic diagram for the embodiment of the invention behind another literary composition of receiving telegraph, for the stream of Bypass, do not need special processing, only the address read outgoing packet that need use RES to carry is delivered to the affiliated circulation road of Bypass and is got final product.
The embodiment of the invention is supported the management of many stream shared buffer memory, and supports stream Bypass scene.The management of FIFO mode write address distributes in conjunction with the Bitmap mode address, simplifies the logical design complexity greatly; With respect to chained list management, removed idle address caching and chain list index buffer memory, saved the read-write operation that resource also reduces Memory, meet the low-power consumption demand.
Corresponding to said method embodiment, as shown in Figure 5, be a kind of message inquiry unit of embodiment of the invention structural representation, described device comprises:
Writing unit 50 is used to receive message and described message is write buffer memory;
Transmitting element 51 is used to send the query requests of described message, and described query requests comprises the address information of heading in described buffer memory of described message;
Receiving element 52 is used to receive the Query Result of feedback, obtains the address information of the heading that comprises described message in described buffer memory in the described Query Result;
Optionally, as shown in Figure 6, be the another kind of message inquiry unit of embodiment of the invention structural representation, described device can also comprise except that comprising writing unit 50, transmitting element 51, receiving element 52 and reading unit 53: zero clearing unit 54.The said write unit is further used for the mode according to first in first out buffer memory FIFO, and described message is write buffer memory.Since when writing message according to the FIFO mode, address ascending order circulation writes, write and carry the address of heading in buffer memory when sending REQ behind the message, and with the RES return address, need not safeguard that thus chained list can guarantee the one-to-one relationship of message and RES, support stream Bypass scene, no matter how out of order also unaffected REQ and RES be.
Said write unit 50, be further used for described message is write a address in the buffer memory, represent that with the form of Bitmap buffer address takies Bitmap position corresponding with described address in the register of situation and is set to 1, account for, do not allow to write again to indicate this address.Described register can be the register of one group of 512bit.Because the write address of packet buffer is pressed the management of FIFO formula, is chaotic but read the address, can not simply calculate the buffer memory remaining space by the read-write number of times, can cause write port whether to allow to write in the perception current address.For addressing this problem, introduce BitMap formula address assignment in the scheme.BitMap is corresponding one by one with the address that message writes in the buffer memory, is that 0 expression is idle, allows to write, and is that 1 expression takies, and taboo writes.Described zero clearing unit 54 is used for described reading unit according to the heading of the described message address information at described buffer memory, from described buffer memory, read described message after, with Bitmap position zero clearing corresponding in the described register with described address.
The embodiment of the invention is supported the management of many stream shared buffer memory, and supports stream Bypass scene.The management of FIFO mode write address distributes in conjunction with the Bitmap mode address, simplifies the logical design complexity greatly; With respect to chained list management, removed idle address caching and chain list index buffer memory, saved the read-write operation that resource also reduces Memory, meet the low-power consumption demand.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct related hardware to finish by program, described program can be stored in the computer read/write memory medium, this program is when carrying out, comprise above-mentioned all or part of step, described storage medium, as: ROM/RAM, disk, CD etc.
Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is the specific embodiment of the present invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a message querying method is characterized in that, described method comprises:
Receive message and described message is write buffer memory;
Send the query requests of described message, described query requests comprises the address information of heading in described buffer memory of described message;
Receive the Query Result of feedback, obtain the address information of heading in described buffer memory of the described message that comprises in the described Query Result;
According to the address information of heading in described buffer memory of described message, from described buffer memory, read described message.
2. method according to claim 1 is characterized in that, described described message is write buffer memory, comprising:
According to the mode of first in first out buffer memory FIFO, described message is write buffer memory.
3. as method as described in the claim 2, it is characterized in that described mode according to first in first out buffer memory FIFO writes buffer memory with described message, comprising:
Described message is write a address in the buffer memory, represent that with the form of map addresses dot chart Bitmap buffer address takies Bitmap position corresponding with described address in the register of situation and is set to 1, account for to indicate this address.
4. as method as described in the claim 3, it is characterized in that, the described address information of heading in described buffer memory according to described message, from described buffer memory, read described message after, described method also comprises:
With Bitmap position zero clearing corresponding in the described register with described address.
5. as method as described in claim 3 or 4, it is characterized in that,
Described register is the register of one group of 512bit.
6. a message inquiry unit is characterized in that, described device comprises:
Writing unit is used to receive message and described message is write buffer memory;
Transmitting element is used to send the query requests of described message, and described query requests comprises the address information of heading in described buffer memory of described message;
Receiving element is used to receive the Query Result of feedback, obtains the address information of heading in described buffer memory of the described message that comprises in the described Query Result;
Reading unit is used for reading described message according to the heading of the described message address information at described buffer memory from described buffer memory.
7. as device as described in the claim 6, it is characterized in that,
The said write unit is further used for the mode according to first in first out buffer memory FIFO, and described message is write buffer memory.
8. as device as described in the claim 7, it is characterized in that, the said write unit, be further used for described message is write a address in the buffer memory, represent that with the form of map addresses dot chart Bitmap buffer address takies Bitmap position corresponding with described address in the register of situation and is set to 1, account for to indicate this address.
9. as device as described in the claim 8, it is characterized in that described device also comprises:
The zero clearing unit is used for described reading unit according to the heading of the described message address information at described buffer memory, from described buffer memory, read described message after, with Bitmap position zero clearing corresponding in the described register with described address.
10. as device as described in claim 8 or 9, it is characterized in that,
Described register is the register of one group of 512bit.
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| CN2011100316087A CN102098221A (en) | 2011-01-28 | 2011-01-28 | Message query method and device |
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| CN2011100316087A CN102098221A (en) | 2011-01-28 | 2011-01-28 | Message query method and device |
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| US9471508B1 (en) | 2015-04-09 | 2016-10-18 | International Business Machines Corporation | Maintaining command order of address translation cache misses and subsequent hits |
| CN108959514A (en) * | 2018-06-27 | 2018-12-07 | 中国建设银行股份有限公司 | A kind of data processing method and device |
| CN111949568A (en) * | 2020-07-31 | 2020-11-17 | 新华三半导体技术有限公司 | Message processing method and device and network chip |
| CN113343045A (en) * | 2021-07-29 | 2021-09-03 | 阿里云计算有限公司 | Data caching method and network equipment |
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| CN1555166A (en) * | 2003-12-26 | 2004-12-15 | ƽ | Method and device for pos data filter delivering |
| CN101150525A (en) * | 2007-11-20 | 2008-03-26 | 杭州华三通信技术有限公司 | Release method, system and logic module for buffered address |
| CN101252536A (en) * | 2008-03-31 | 2008-08-27 | 清华大学 | Router multi-queue data pack buffer management and output queue scheduling system |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9471508B1 (en) | 2015-04-09 | 2016-10-18 | International Business Machines Corporation | Maintaining command order of address translation cache misses and subsequent hits |
| CN108959514A (en) * | 2018-06-27 | 2018-12-07 | 中国建设银行股份有限公司 | A kind of data processing method and device |
| CN108959514B (en) * | 2018-06-27 | 2021-02-26 | 中国建设银行股份有限公司 | Data processing method and device |
| CN111949568A (en) * | 2020-07-31 | 2020-11-17 | 新华三半导体技术有限公司 | Message processing method and device and network chip |
| CN111949568B (en) * | 2020-07-31 | 2023-07-21 | 新华三半导体技术有限公司 | Message processing method, device and network chip |
| CN113343045A (en) * | 2021-07-29 | 2021-09-03 | 阿里云计算有限公司 | Data caching method and network equipment |
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Application publication date: 20110615 |