CN116032404A - IEEE 1588 synchronous clock error correction method based on differentiated service scheduling model - Google Patents
IEEE 1588 synchronous clock error correction method based on differentiated service scheduling model Download PDFInfo
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Abstract
The invention discloses an IEEE 1588 synchronous clock error correction method based on a differentiated service scheduling model. The method comprises the following steps: establishing a DPSM mechanism, setting queue priority for different types of data messages entering and exiting the node by the DPSM mechanism, correcting the message service rate, configuring a message urgency function to determine the path delay of the synchronous message, and correcting the IEEE 1588 network clock path delay. And on the basis of eliminating the path delay of the synchronous message, the oscillation frequency difference of the master clock generator and the slave clock generator is corrected, so that the measurement of the clock offset is completed, and the high-precision network clock is realized. The network clock error generated by the method is only 50ns, the precision is high, the requirement of the intelligent substation on the time of Zhong Jingdu is completely met, the network stability corrected by the method is superior to that of the traditional algorithm, and the method can be popularized in the whole substation automation equipment.
Description
Technical Field
The invention relates to the technical field of intelligent substation clock synchronization, in particular to an IEEE 1588 synchronous clock error correction method based on a differentiated services scheduling model (DPSM)
Background
The coverage range of a modern power system is very wide, and in a modern power grid, a unified time system has important significance for ensuring the consistency of real-time data acquisition of the power system, provides accurate time basis for system fault analysis and processing, improves the running efficiency and reliability of the power grid, improves the level of power grid accident analysis and stable control, and improves the accuracy of line fault ranging, phasor and power angle dynamic monitoring and unit and power grid parameter verification. The equipment intellectualization of the transformer substation is an important basic link for realizing the intelligent power grid, and with the perfection of IEC 64850 standard, the requirements on the ground synchronous clock precision and stability of the intelligent transformer substation are higher and higher.
The IEEE 1588 accurate clock synchronization protocol is the best synchronization method in the current clock synchronization field, the IEEE 1588 synchronization process is carried out under ideal conditions, and the time synchronization precision reaches the sub microsecond level. The IEEE 1588 synchronous clock is based on network time synchronization, the transmission basis is the communication network of the substation where the network is located, the network carries all communication services in the substation, the arrival of service messages is random and uncertain, and each node has no global network information. When the line is congested, the problem of path delay inevitably occurs, if the network transmission is blocked, the service competition will occur, and the synchronous packet loss and other conditions are caused, so that the synchronous performance of the master device and the slave device is seriously affected. In practical application, the IEEE 1588 synchronous clock has the problems of unreliable synchronous message transmission, uncertain path delay and the like. And the clock generator itself also has oscillation frequency offset errors, and all factors affect the stability of the IEEE 1588 synchronous clock. Many researches have been developed for this problem at home and abroad, and some solutions are proposed, such as: the clock synchronization precision of the network clock is improved through crystal oscillator compensation and OffsetTime filtering, but the method has higher requirement on the CPU calculation speed and is difficult to realize; the influence of the oscillation frequency deviation of the clock generator on the precision is reduced by embedding the Ethernet transceiver DP83640 chip in the physical layer of the switch, but the chip is expensive, network equipment needs to be modified, and the cost is high.
To sum up: the error correction of the IEEE 1588 synchronous clock has certain difficulty, and the existing methods have certain limitations, such as: the cost is high, the requirement on the CPU calculation speed is high, the influence of path delay deviation is large, and the method is difficult to realize in reality.
Disclosure of Invention
In order to correct the IEEE 1588 synchronous clock error, and the method has the characteristics of simplicity, high practicability and strong anti-interference capability, the invention provides an IEEE 158 synchronous clock error correction method based on a differentiated services scheduling model (DPSM). The method provides a brand new DPSM algorithm, only needs a CPU to process the DPSM algorithm, sets queue priority for different types of data messages entering the node, corrects the service rate of the data messages, configures a message urgency function, can determine the path delay of the synchronous message, and effectively corrects the path delay error of the synchronous message. And on the premise of path delay correction, the oscillation frequency of the clock generator is corrected, so that the measurement of the high-precision clock offset is completed, and the high-precision network clock synchronization is realized.
In order to achieve the technical purpose, the technical scheme of the invention is that the IEEE 1588 synchronous clock error correction method based on a differentiated services scheduling model (DPSM) comprises the following steps:
step one, a DPSM mechanism is established, the DPSM mechanism sets queue priority for different types of data messages entering and exiting the node, modifies the message service rate, configures a message urgency function to determine the path delay of the synchronous message, and modifies the path delay of the IEEE 1588 synchronous message.
Step two, on the basis of realizing path delay error correction, the oscillation frequency of the clock generator can be corrected to finish the measurement of the high-precision clock offset, thereby realizing the high-precision network clock synchronization
In the first step, the DPSM is an improved real-time online packet scheduling algorithm mechanism suitable for a substation communication network, the time setting precision achieved by the algorithm can completely meet the requirement of an intelligent substation on the time setting precision, and the network stability and the path delay are superior to those of the traditional algorithm.
In the first step, the DPSM provides a network reliability guarantee mechanism (RBGM), which greatly improves the network stability of the algorithm, and the implementation principle of the RBGM is as follows:
the IEEE 1588 synchronous message is provided with a reserved field in an original header, a reliability transmission identifier is defined in the reserved field, and a master clock and a slave clock identify the synchronous message through the reliability transmission identifier. When the master clock transmits the synchronous message, the slave clock can rapidly identify and receive the synchronous message transmitted by the master clock by identifying the reliability transmission identifier, and immediately feed back a message containing the reliability transmission identifier to inform the master clock that the synchronous message is received. After a certain time, if the master clock does not receive the feedback information with the identifier, the master clock will send the synchronous message again until receiving the confirmation information.
In the first step, priorities of different types of data message queues of the ingress and egress nodes are set as follows:
grouping all service messages entering each node of the network, introducing a virtual time concept, configuring virtual system time, defining virtual starting time and virtual ending time of each data stream, setting priority according to the virtual starting time, and preferentially transmitting the packets with the minimum virtual starting time.
In the first step, the correction of the message service rate is performed as follows:
the IEEE 1588 synchronization principle is analyzed to obtain the following relationship:
wherein:
is the actual amount of path delay; t (T) delay Is ideal path delay amount
And the DPSM carries out trimming optimization on the synchronous message and establishes a bandwidth adjusting factor. When the network is normal, a bandwidth adjusting factor tau (tau is more than or equal to 0 and less than or equal to 1) is added in the virtual time of the computing system, the bandwidth proportion between the synchronous message and other service messages is represented, the larger the tau value is, the smaller the data bandwidth allocated by the synchronous message is, the larger data bandwidth is obtained by the synchronous message along with the decrease of the tau value, and the service rate of the message is faster. That is, the synchronous message can be transmitted according to the agreed speed by controlling the tau value, so that deltat/2 tends to 0. The delay error between the actual path delay and the path delay under ideal conditions is 0, so that the correction of the path delay error of the synchronous message is realized.
The IEEE 1588 synchronous clock error correction method based on differentiated services scheduling model (DPSM) comprises the following steps:
the DPSM introduces a message urgency function mu (x) in the virtual starting time, and when a network is congested, the DPSM adaptively adjusts the urgency function mu (x) of the synchronous message, and configures a larger value for the mu (x) function, so that the virtual starting time of the synchronous message is smaller than that of other data messages, and the synchronous message is sent preferentially.
An excessive μ (x) would lead to an excess bandwidth, and in order to avoid this, μ (x) should satisfy the following relationship:
wherein: l (L) min A length of a minimum data packet in the intra-station communication network; beta (beta is more than or equal to 1) is the congestion degree.
An IEEE 1588 synchronous clock error correction method based on a differentiated services scheduling model (DPSM), wherein in the second step, the oscillation frequency difference of a master clock generator and a slave clock generator is corrected according to the following mode:
transmitting and synchronizing request messages from a clock, and recording accurate transmission time T b1 The master clock receives and records the receiving time T a1 The method comprises the steps of carrying out a first treatment on the surface of the After time delta (based on the slave clock), the slave clock transmits the following message, and the master clock again records the receiving time T a2 The master clock can determine the oscillation frequency error of the clock generator of the master-slave device by the following two accurate receiving times:
ΔF＝T a2 -T a1 -δ
wherein: ΔF is the frequency difference of the oscillation frequencies of the master clock generator and the slave clock generator
After the frequency difference is determined, the frequency difference can be corrected, and finally the high-precision network clock is realized.
The invention has the technical effects that a DPSM mechanism is provided, queue priorities are set for different types of data messages entering and exiting nodes, the service rate of the data messages is corrected, a message urgency function is configured, the path delay error of the synchronous messages is corrected from the source, even the network is congested, the lower path delay error can be ensured, the oscillation frequency difference of a master clock generator and a slave clock generator can be corrected on the basis of realizing the path delay correction of the synchronous messages, the correction is carried out from two main aspects affecting the precision of the synchronous clocks, the nanosecond network time synchronization is realized, the IEC 64850 standard time synchronization precision requirement can be met, and the precision is high and the stability is good.
The invention is further described below with reference to the accompanying drawings.
Drawings
FIG. 1 is a differentiated services dispatch model diagram;
FIG. 2 is a schematic diagram of a reliability transfer identifier tag location;
FIG. 3 is a diagram of a high precision network always implementation process
FIG. 4 is a block diagram of a high precision network clock hardware circuit
FIG. 5 is a schematic diagram of an environment experiment of a wide area network of a high-precision network clock
FIG. 6 is a diagram illustrating an unmodified synchronous message path delay
FIG. 7 is a schematic diagram of a modified synchronous message path delay
Detailed Description
The basic working principle of this embodiment is as follows: aiming at the problems of difficult implementation, poor economy and the like of the existing IEEE 1588 synchronous clock error correction method, the IEEE 1588 synchronous clock error correction method based on a differentiated services scheduling model (DPSM) is provided. A DPSM mechanism is established as shown in fig. 1. DPSM is an improved real-time online packet scheduling algorithm mechanism suitable for substation communication networks. The DPSM sets queue priorities for different types of data messages that enter and exit the node. The DPSM groups the service messages entering each node of the network, introduces a virtual time concept, configures virtual system time, defines virtual starting time and virtual ending time of each data stream, sets priority according to the virtual starting time, and preferentially transmits the packets with the minimum virtual starting time. The DPSM algorithm is based on a bandwidth adjustment factor and an urgency function. Analysis of the IEEE 1588 synchronization principle yields the following relationship:
wherein:
is the actual amount of path delay; t (T) delay Is ideal path delay amount
And the DPSM carries out trimming optimization on the synchronous message and establishes a bandwidth adjusting factor. When the network is normal, a bandwidth adjusting factor tau (tau is more than or equal to 0 and less than or equal to 1) is added in the virtual time of the computing system, the bandwidth proportion between the synchronous message and other service messages is represented, the larger the tau value is, the smaller the data bandwidth allocated by the synchronous message is, the larger data bandwidth is obtained by the synchronous message along with the decrease of the tau value, and the service rate of the message is faster. Namely, synchronous messages can be transmitted according to the appointed speed by controlling the tau value, so that delta t/2 tends to 0, and the path delay error is eliminated.
The DPSM introduces a message urgency function μ (x) in the virtual start-up time. When the network is congested, the DPSM adaptively adjusts the urgency function mu (x) of the synchronous message, and configures a larger value for the mu (x) function, so that the virtual starting time of the synchronous message is smaller than that of other data messages, and the synchronous message is sent preferentially.
In order to avoid the bandwidth surplus phenomenon due to the excessively large μ (x), μ (x) should satisfy the following relationship:
wherein: l (L) min A length of a minimum data packet in the intra-station communication network; beta (beta is more than or equal to 1) is the congestion degree.
The DPSM introduces RBGM and has better network stability compared with the traditional algorithm. The IEEE 1588 sync message configures a reserved field in the original header, and defines a reliability transmission identifier in the reserved field, where the reliability transmission identifier is identified in fig. 2. The master and slave clocks identify the synchronization message by the reliability transfer identifier. When the master clock transmits the synchronous message, the slave clock can rapidly identify and receive the synchronous message transmitted by the master clock by identifying the reliability transmission identifier, and immediately feed back a message containing the reliability transmission identifier to inform the master clock that the synchronous message is received. After a certain time, if the master clock does not receive the feedback information with the identifier, the master clock sends the synchronous message again until receiving the confirmation information.
Through the steps, the determination and elimination of the path delay error of the synchronous message can be completed, the oscillation frequency difference of the master clock generator and the slave clock generator is calculated and corrected on the basis, the measurement of the high-precision clock offset is completed, and the high-precision network clock synchronization is further realized.
The high precision network clock implementation is shown in fig. 3. Time T for sending synchronous request message from clock record b1 The master clock receives and records the receiving time T a1 The method comprises the steps of carrying out a first treatment on the surface of the After time delta (based on the slave clock), the slave clock transmits the following message, and the master clock again records the receiving time T a2 The master clock can finish calculation and correction of the oscillation frequency difference of the clock generator of the master-slave device by the following two accurate receiving times:
ΔF＝T a2 -T a1 -δ
wherein: ΔF is the frequency difference of the oscillation frequencies of the master clock generator and the slave clock generator
And (3) experimental verification:
according to theory, a high-precision network clock is designed, a hardware schematic diagram is shown in fig. 4, fig. 4 (a) is a main clock hardware circuit block diagram, a GPS/Beidou dual-mode time service system is used as a main clock time service source, an accurate second pulse signal is provided for a network, time information is sent to a CPU, and second pulses are sent to an FPGA. Fig. 4 (b) is a block diagram of the slave clock hardware, the slave clock seconds time being provided by the constant temperature high precision crystal oscillator. The FPGA is used to mark the timestamp of the PHY layer. The CPU is used for processing a DPSM algorithm, setting priority for data messages entering and exiting the node, correcting the service rate of the messages, configuring a message urgency function, and realizing demonstration certainty of synchronous messages. The master-slave clock CPU uses ARM9260 chips produced by ATMEL company; the FPGA chip uses an A3P125 chip manufactured by ACTEL company; the high-precision constant-temperature crystal oscillator frequency is 100MHz. To embody the authenticity of the experiment, a wide area network is composed of 2 WAN routers, and the WAN router is realized by an ARM9260 to realize a DPSM mechanism. Fig. 5 is a high-precision network clock experimental environment.
Fig. 6 and 7 are synchronous message path delay test results: as can be seen from fig. 6, as the network load increases, the path delay error of the synchronous message is larger. Fig. 7 shows the result after the DPSM correction, and it can be seen that the corrected message has low delay and low jitter, and when the network load is too large and the network is blocked, good stability is still maintained.
Claims (7)
1. An IEEE 1588 synchronous clock error correction method based on a differentiated service scheduling model is characterized by comprising the following steps of:
step one, a DPSM mechanism is established, the DPSM mechanism sets queue priority for different types of data messages entering and exiting the node, modifies the message service rate, configures a message urgency function to determine the path delay of a synchronous message, and modifies the IEEE 1588 network clock path delay.
And secondly, correcting the oscillation frequency difference of the master clock generator and the slave clock generator on the basis of eliminating the path delay of the synchronous message, completing the clock offset measurement and realizing the high-precision network clock.
2. The IEEE 1588 synchronous clock error correction method based on differentiated service dispatch model according to claim 1, wherein in the first step, DPSM is an improved real-time online packet dispatch algorithm mechanism suitable for a substation communication network, the time setting accuracy achieved by the algorithm can completely meet the requirement of an intelligent substation on time accuracy, and both network stability and path delay are superior to those of the conventional algorithm.
3. The IEEE 1588 synchronous clock error correction method based on differentiated service scheduling model according to claim 1, wherein in the first step, the DPSM proposes a network reliability guarantee mechanism (RBGM), which greatly improves the network stability of the algorithm, and the implementation principle of the RBGM is as follows:
the IEEE 1588 synchronous message is provided with a reserved field in an original header, a reliability transmission identifier is defined in the reserved field, and a master clock and a slave clock identify the synchronous message through the reliability transmission identifier. When the master clock transmits the synchronous message, the slave clock can rapidly identify and receive the synchronous message transmitted by the master clock by identifying the reliability transmission identifier, and immediately feed back a message containing the reliability transmission identifier to inform the master clock that the synchronous message is received. After a certain time, if the master clock does not receive the feedback information with the identifier, the master clock will send the synchronous message again until receiving the confirmation information.
4. The method for correcting IEEE 1588 synchronous clock error based on differentiated services dispatch model according to claim 1, wherein in the first step, the priorities of the queues of different types of data messages entering and exiting the node are set as follows:
the DPSM groups all service messages entering each node of the network, introduces a virtual time concept, configures virtual system time, defines virtual starting time and virtual ending time of each data stream, sets priority according to the virtual starting time, and preferentially transmits the packets with the minimum virtual starting time.
5. The method for correcting IEEE 1588 synchronous clock error based on differentiated services dispatch model according to claim 1, wherein in the first step, the correction of the message service rate is performed as follows:
the IEEE 1588 synchronization principle is analyzed to obtain the following relationship:
wherein:
is the actual amount of path delay; t (T) delay Is an ideal path delay amount.
And the DPSM carries out trimming optimization on the synchronous message and establishes a bandwidth adjusting factor. When the network is normal, a bandwidth adjusting factor tau (tau is more than or equal to 0 and less than or equal to 1) is added in the virtual time of the computing system, the bandwidth proportion between the synchronous message and other service messages is represented, the larger the tau value is, the smaller the data bandwidth allocated by the synchronous message is, the larger data bandwidth is obtained by the synchronous message along with the decrease of the tau value, and the service rate of the message is faster. That is, the synchronous message can be transmitted according to the agreed speed by controlling the tau value, so that deltat/2 tends to 0. The delay error between the actual path delay and the path delay under ideal conditions is 0, so that the correction of the path delay error of the synchronous message is realized.
6. The method for correcting IEEE 1588 synchronous clock error based on differentiated services dispatch model according to claim 1, wherein in the first step, the configuring of the message urgency function is performed as follows:
the DPSM introduces a message urgency function mu (x) in the virtual starting time, and when a network is congested, the DPSM adaptively adjusts the urgency function mu (x) of the synchronous message, and configures a larger value for the mu (x) function, so that the virtual starting time of the synchronous message is smaller than that of other data messages, and the synchronous message is sent preferentially.
An excessive μ (x) would lead to an excess bandwidth, and in order to avoid this, μ (x) should satisfy the following relationship:
wherein: l (L) min A length of a minimum data packet in the intra-station communication network; beta (beta is more than or equal to 1) is the congestion degree.
7. The method for correcting the path delay error of the synchronous message based on the differentiated services dispatch model according to claim 1, wherein in the second step, the oscillation frequency difference of the master clock generator and the slave clock generator is corrected according to the following mode:
transmitting and synchronizing request messages from a clock, and recording accurate transmission time T b1 The master clock receives and records the receiving time T a1 The method comprises the steps of carrying out a first treatment on the surface of the After time delta (based on the slave clock), the slave clock transmits the following message, and the master clock again records the receiving time T a2 The master clock can determine the correction of the oscillation frequency error of the clock generator of the master-slave equipment by the following two accurate receiving times:
ΔF＝T a2 -T a1 -δ
wherein: Δf is the frequency difference of the oscillation frequencies of the master clock generator and the slave clock generator; delta is a constant value that is not required to be set again after being set by initialization.
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