CN116032388B - Chip sensitivity test method, system, device, computer equipment and medium - Google Patents
Chip sensitivity test method, system, device, computer equipment and medium Download PDFInfo
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- CN116032388B CN116032388B CN202310290149.7A CN202310290149A CN116032388B CN 116032388 B CN116032388 B CN 116032388B CN 202310290149 A CN202310290149 A CN 202310290149A CN 116032388 B CN116032388 B CN 116032388B
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Abstract
The invention relates to a method, a system, a device, computer equipment and a medium for testing the sensitivity of a chip, which are used for respectively and correspondingly acquiring first frequency domain data of a radio frequency signal and second frequency domain data of the test signal by separating the radio frequency signal and the test signal so as to determine the sensitivity of the chip to be tested. Because the radio frequency signals comprise interference signals in the environment, the test signals comprise interference signals in the environment, the first frequency domain data identify the sensitivity of the chip to be tested for receiving the radio frequency signals, and the second frequency domain data identify the sensitivity of the chip to be tested for receiving the test signals, interference of the environment in the second frequency domain data to the sensitivity of the chip to be tested can be eliminated based on the first frequency domain data, so that a more accurate sensitivity test result is obtained, the anti-interference capability of the chip sensitivity test is enhanced, the test accuracy of the chip sensitivity is improved, and the normal running of a test scene with smaller test signals is ensured.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a method, a system, an apparatus, a computer device, and a medium for testing sensitivity of a chip.
Background
In a bluetooth wireless communication system, an important indicator for measuring the performance of a receiver, namely sensitivity, is the minimum input power required for receiving under the condition of ensuring that a Bit Error Rate (BER) is satisfied. In other words, the better the reception performance of the bluetooth system, the smaller the sensitivity value thereof, and the higher the corresponding capability of detecting and demodulating the minimum input signal strength of the data. Therefore, the sensitivity test is an essential important link for testing and screening the Bluetooth chip. If the sensitivity test is absent, the yield of the chip cannot be guaranteed, and the uniformity of the chip cannot be guaranteed.
However, the receiving sensitivity of the bluetooth chip at present is often below-90 dBm, for such input power, interference of an environmental radio frequency signal outside the tester is easily received, and the signal distortion is caused by mixing the test signal and the interference signal, so that the receiver obtains an error result, and thus, the error screening of the chip is caused, the yield is abnormally reduced, and even the test cannot be realized.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, apparatus, system, computer device, storage medium, and program product for testing sensitivity of a chip, so as to improve accuracy of testing sensitivity of the chip.
In a first aspect, the present application provides a method for testing sensitivity of a chip, including:
under the condition that the radio frequency test equipment does not emit a test signal, acquiring first frequency domain data of the radio frequency signal received by the chip to be tested; the radio frequency test equipment is connected with the chip to be tested;
controlling the radio frequency test equipment to transmit the test signal to the chip to be tested, and acquiring second frequency domain data of the chip to be tested for receiving the test signal; the frequency points of the radio frequency signal and the test signal are the same;
and determining the sensitivity of the chip to be tested according to the second frequency domain data and the first frequency domain data.
In one embodiment, the acquiring the first frequency domain data of the radio frequency signal received by the chip to be tested when the radio frequency test device does not transmit the test signal includes:
under the condition that the radio frequency test equipment does not emit the test signal, respectively acquiring radio frequency domain data of the radio frequency signal received by the chip to be tested for multiple times;
screening a plurality of radio frequency domain data by using an bubbling sequencing method to determine the first frequency domain data of the radio frequency signals received by the chip to be tested; wherein the first frequency domain data is used to characterize power.
In one embodiment, the controlling the radio frequency test device to transmit the test signal to the chip to be tested and obtain the second frequency domain data of the chip to be tested to receive the test signal includes:
controlling the radio frequency test equipment to transmit the test signal to the chip to be tested for multiple times, and correspondingly acquiring test frequency domain data received by the chip to be tested for multiple times respectively;
screening a plurality of the test frequency domain data by using an bubbling sequencing method to determine the second frequency domain data of the test signal received by the chip to be tested; wherein the second frequency domain data is used to characterize power.
In one embodiment, the acquiring the first frequency domain data of the radio frequency signal received by the chip to be tested when the radio frequency test device does not transmit the test signal includes:
under the condition that the radio frequency test equipment does not emit the test signals, acquiring a plurality of first frequency domain data corresponding to the plurality of radio frequency signals received by the chip to be tested; wherein, the frequency points of the radio frequency signals are different;
the controlling the radio frequency test device to transmit the test signal to the chip to be tested and obtain second frequency domain data of the chip to be tested for receiving the test signal includes:
Controlling the radio frequency test equipment to respectively transmit a plurality of test signals to the chip to be tested, and respectively acquiring a plurality of second frequency domain data corresponding to the plurality of test signals received by the chip to be tested; the frequency points of the test signals are different, and each radio frequency signal corresponds to the test signal with the same frequency point.
In one embodiment, before controlling the radio frequency test device to respectively transmit a plurality of test signals to the chip to be tested, the chip sensitivity test method further includes:
receiving a message to be tested sent by the chip to be tested, wherein the message to be tested comprises a plurality of frequency points of the radio frequency signal; wherein, the liquid crystal display device comprises a liquid crystal display device,
the controlling the radio frequency test device to respectively transmit a plurality of test signals to the chip to be tested includes:
and controlling the radio frequency test equipment to respectively transmit a plurality of test signals corresponding to a plurality of frequency points of the radio frequency signal to the chip to be tested according to the message to be tested.
In one embodiment, the determining the sensitivity of the chip to be tested according to the second frequency domain data and the first frequency domain data includes:
calculating a frequency domain data difference value of the first frequency domain data and the second frequency domain data;
Under the condition that the frequency domain data difference value is in a preset range, determining that the sensitivity of the chip to be tested is qualified;
and under the condition that the frequency domain data difference value is not in the preset range, determining that the sensitivity of the chip to be tested is unqualified.
In one embodiment, the number of the chips to be tested is plural, and each chip to be tested is correspondingly connected with different radio frequency test devices; wherein, the liquid crystal display device comprises a liquid crystal display device,
before the first frequency domain data of the radio frequency signal received by the chip to be tested is obtained, the chip sensitivity test method further comprises the following steps:
configuring each of the radio frequency test devices to a silence state in which no test signal is transmitted;
and initializing each chip to be tested to close the transmitting passage of each chip to be tested and open the receiving passage of each chip to be tested.
In a second aspect, the present application further provides a chip sensitivity test system, including:
radio frequency test equipment;
the chip to be tested is connected with the radio frequency test equipment and is used for receiving the radio frequency signal and outputting first frequency domain data under the condition that the radio frequency test equipment does not emit a test signal; the chip to be tested is also used for receiving the test signal and outputting second frequency domain data under the condition that the radio frequency test equipment transmits the test signal;
The test machine station is respectively connected with the radio frequency test equipment and the chip to be tested, and is used for controlling the radio frequency test equipment to emit the test signal, acquiring the first frequency domain data and the second frequency domain data, and determining the sensitivity of the chip to be tested according to the first frequency domain data and the second frequency domain data.
In one embodiment, the chip sensitivity test system includes a plurality of chips to be tested and a plurality of different radio frequency test devices respectively connected with the chips to be tested; wherein, the transmitting passage of each chip to be tested is closed and the receiving passage is opened.
In one embodiment, the receiving path of the chip to be tested includes:
the antenna is connected with the radio frequency test equipment and is used for receiving radio frequency signals or receiving the test signals transmitted by the radio frequency test equipment under the condition that the radio frequency test equipment does not transmit the test signals;
the automatic gain control module is connected with the antenna, and is used for adjusting the gain of the radio frequency signal or the test signal and outputting an analog signal; the automatic gain control modules of the chips to be tested have the same receiving gain and keep the gain of the chips to be tested synchronously changed;
The analog-to-digital sampling module is connected with the automatic gain control module and is used for sampling the analog signal according to a preset sampling frequency and generating a digital signal;
and the Fourier transform module is connected with the analog-to-digital sampling module and is used for carrying out Fourier transform on the digital signals and generating frequency domain data, wherein the frequency domain data comprises first frequency domain data of the radio frequency signals or second frequency domain data of the test signals.
In a third aspect, the present application further provides a chip sensitivity test apparatus, including:
the first acquisition module is used for acquiring first frequency domain data of the radio frequency signal received by the chip to be tested under the condition that the radio frequency test equipment does not emit the test signal; the radio frequency test equipment is connected with the chip to be tested;
the second acquisition module is used for controlling the radio frequency test equipment to transmit the test signal to the chip to be tested and acquiring second frequency domain data of the chip to be tested for receiving the test signal; the frequency points of the radio frequency signal and the test signal are the same;
and the determining module is used for determining the sensitivity of the chip to be detected according to the second frequency domain data and the first frequency domain data.
In a fourth aspect, the present application also provides a computer device. The computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the chip sensitivity testing method according to any one of the embodiments.
In a fifth aspect, the present application also provides a computer-readable storage medium. The computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the chip sensitivity test method according to any one of the above embodiments.
In a sixth aspect, the present application also provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the chip sensitivity test method according to any one of the above embodiments.
The method, the system, the device, the computer equipment, the storage medium and the computer program product for testing the sensitivity of the chip are used for respectively and correspondingly acquiring the first frequency domain data of the radio frequency signal and the second frequency domain data of the test signal by separating the radio frequency signal and the test signal, so that the sensitivity of the chip to be tested is determined. Because the radio frequency signal comprises the interference signal in the environment, the test signal also comprises the interference signal in the environment, the first frequency domain data marks the sensitivity of the chip to be tested for receiving the radio frequency signal, and the second frequency domain data marks the sensitivity of the chip to be tested for receiving the test signal, the interference of the second frequency domain data on the sensitivity of the chip to be tested can be eliminated based on the first frequency domain data, so that a more accurate sensitivity test result is obtained, the anti-interference capability of the chip sensitivity test is enhanced, the test accuracy of the chip sensitivity is improved, and the normal running of a smaller test scene of the test signal is ensured.
Drawings
FIG. 1 is a flow chart of a method for testing sensitivity of a chip according to an embodiment;
FIG. 2 is a flowchart of step S101 in a method for testing sensitivity of a chip according to an embodiment;
FIG. 3 is a flowchart illustrating a step S102 in a method for testing chip sensitivity according to an embodiment;
FIG. 4 is a flowchart of step S103 in a method for testing sensitivity of a chip according to an embodiment;
FIG. 5 is a flow chart of a method for testing sensitivity of a chip according to another embodiment;
FIG. 6 is a block diagram of a chip sensitivity system provided by one embodiment;
FIG. 7 is a block diagram of a chip sensitivity system according to another embodiment;
FIG. 8 is a block diagram of a chip under test according to one embodiment;
FIG. 9 is a flow chart of a method for testing sensitivity of a chip according to another embodiment;
FIG. 10 is a block diagram of a chip sensitivity test apparatus according to one embodiment;
FIG. 11 is a block diagram of a computer device according to one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
As described in the background art, the chip sensitivity test process is easily interfered by environmental factors, resulting in poor test results. In general, whether the direct current working points of each sub-module of the chip receiving channel are in a reasonable range or not is judged by testing parameters such as voltage, current and the like, so that the quality of the receiving function of the chip to be tested is judged. However, simply testing the dc operating point only ensures the normal dc operating point of the bluetooth chip during operation, and cannot truly represent the excellent level of the performance of the chip. Or, let the radio frequency test equipment send a radio frequency signal with relatively high power such as-70 dBm to weaken the interference brought by environmental factors, then judge whether the chip to be tested normally demodulates original data or judge whether its error rate meets the requirement. However, this relatively high signal power to test the chip's receiving function can only ensure that the tested, screened chip will function properly at this high power. Or, a shielding measure is additionally arranged, and the test is performed in a shielded room, so that the outside radio frequency interference signals are shielded, but only a single chip (single test) can be tested, so that the test speed is reduced, and the test cost is increased.
In this regard, the present application provides a method, system, apparatus, computer device, storage medium, and computer program product for chip sensitivity testing to improve chip sensitivity testing accuracy.
In one embodiment, as shown in FIG. 1, a method of testing chip sensitivity is provided. The chip sensitivity test method may include the following steps S101 to S103.
S101: under the condition that the radio frequency test equipment does not emit the test signal, acquiring first frequency domain data of the radio frequency signal received by the chip to be tested.
The radio frequency test equipment is connected with the chip to be tested and is used for transmitting test signals so as to test the sensitivity of the chip to be tested. In the case where the radio frequency test equipment is not transmitting test signals, the chip under test (Device under test, DUT) may receive radio frequency signals in the environment, for example, test signal interference from radio frequency test equipment for testing other chips, or other radio frequency signals from the chip under test. Wherein the radio frequency signal comprises an interference signal in the environment. Based on the above, corresponding first frequency domain data can be obtained according to the radio frequency signal received by the chip to be tested, and the first frequency domain data is used for identifying the sensitivity of the chip to be tested to receive the radio frequency signal. The sensitivity refers to the minimum input power required for receiving under the condition of meeting the bit error rate requirement. By way of example, the first frequency domain data may be power, power consumption, etc., without any limitation herein.
S102: and controlling the radio frequency test equipment to transmit test signals to the chip to be tested, and acquiring second frequency domain data of the test signals received by the chip to be tested.
The frequency points of the radio frequency signal and the test signal are the same, which can be understood that the frequencies of the radio frequency signal and the test signal received by the chip to be tested are the same, wherein the frequency points can be the working frequency of the chip to be tested. The test signal also includes an ambient interference signal. The Radio frequency test device and the chip to be tested may be connected by a Radio Frequency (RF) feeder, and the Radio frequency test device sends a test signal to the chip to be tested through the RF feeder. The second frequency domain data is used for identifying the sensitivity of the chip to be tested to receive the test signal. By way of example, the second frequency domain data may be power, power consumption, etc., without any limitation herein.
S103: and determining the sensitivity of the chip to be tested according to the second frequency domain data and the first frequency domain data.
According to the chip sensitivity test method provided by the embodiment, the sensitivity of the chip to be tested is determined by separating the radio frequency signal from the test signal and correspondingly acquiring the first frequency domain data of the radio frequency signal and the second frequency domain data of the test signal respectively. Because the radio frequency signal comprises the interference signal in the environment when no test signal exists, the test signal also comprises the interference signal in the environment, the first frequency domain data marks the sensitivity of the chip to be tested for receiving the radio frequency signal, and the second frequency domain data marks the sensitivity of the chip to be tested for receiving the test signal, therefore, the interference of the environment in the second frequency domain data to the sensitivity of the chip to be tested can be eliminated based on the first frequency domain data, so that a more accurate sensitivity test result is obtained, the anti-interference capability of the chip sensitivity test is enhanced, the test accuracy of the chip sensitivity is improved, and the normal running of a test scene with smaller test signal is ensured.
In one embodiment, as shown in fig. 2, step S101, in a case where the radio frequency test device does not transmit a test signal, acquiring first frequency domain data of a radio frequency signal received by a chip to be tested may include the following step S201 and step S202.
S201: under the condition that the radio frequency test equipment does not emit the test signal, respectively acquiring radio frequency domain data of the radio frequency signal received by the chip to be tested for multiple times.
The number of times that the chip to be tested receives the radio frequency signal can be preset, and in the testing process, the radio frequency domain data of the radio frequency signal received by the chip to be tested can be obtained correspondingly according to the preset number of times, so that a certain statistical number of radio frequency domain data can be obtained. The frequency of acquiring the radio frequency domain data of the radio frequency signals received by the chip to be tested is not limited, and the frequency can be set according to actual requirements and test scenes.
S202: and screening the plurality of radio frequency domain data by using an bubbling sequencing method to determine first frequency domain data of the radio frequency signals received by the chip to be tested.
For example, the plurality of radio frequency domain data acquired in S201 may be sequenced by using an bubbling sequencing method, the maximum value and the minimum value are deleted, and then an average value of the remaining data is taken as the first frequency domain data of the radio frequency signal received by the chip to be tested, and is denoted as avg_1 or N. The first frequency domain data is used for representing the power of the chip to be tested for receiving the radio frequency signal. The first frequency domain data corresponds to a background noise power value, namely radio frequency interference with a certain environment.
For example, after the plurality of radio frequency domain data are sequenced by using the bubbling sequencing method, deleting the frequency domain data exceeding the preset range, and taking the intermediate value of the remaining data as the first frequency domain data of the radio frequency signal received by the chip to be tested. The method for screening the radio frequency domain data is not limited.
According to the chip sensitivity test method provided by the embodiment, a certain plurality of radio frequency domain data are obtained, and are screened by using the bubbling sequencing method to determine the first frequency domain data of the radio frequency signals received by the chip to be tested, so that errors in the test process are reduced, the reliability of the first frequency domain data is improved, and the accuracy of the sensitivity of the test chip is further improved.
In one embodiment, as shown in fig. 3, step S102, controlling the radio frequency test device to transmit a test signal to the chip under test and obtain second frequency domain data of the chip under test receiving the test signal may include the following steps S301 and S302.
S301: and controlling the radio frequency test equipment to transmit test signals to the chip to be tested for multiple times, and correspondingly acquiring test frequency domain data received by the chip to be tested for multiple times respectively.
The number of times that the radio frequency test device transmits the test signal to the chip to be tested can be preset, and in the test process, the test frequency domain data of the test signal received by the chip to be tested can be obtained correspondingly according to the preset number of times, so as to obtain a certain statistical number of test frequency domain data. It should be noted that, the frequency point of the test signal transmitted to the chip to be tested by the radio frequency test device is the same each time. The frequency of the radio frequency test equipment transmitting the test signal to the chip to be tested is not limited, and the radio frequency test equipment can be set according to actual requirements and test scenes.
S302: and screening the plurality of test frequency domain data by using an bubbling sequencing method to determine second frequency domain data of the test signals received by the chip to be tested.
For example, the multiple test frequency domain data acquired in S301 may be sorted by using an bubbling sorting method, the maximum value and the minimum value are deleted, and then the average value of the remaining data is taken as the second frequency domain data of the test signal received by the chip to be tested, and is denoted as avg_2 or. The second frequency domain data is used for representing the power of the chip to be tested for receiving the test signal. The second frequency domain data also carries the radio frequency interference of a certain environment.
For example, after the plurality of test frequency domain data are sequenced by using the bubbling sequencing method, deleting the frequency domain data exceeding the preset range, and taking the intermediate value of the residual data as the second frequency domain data of the test signal received by the chip to be tested. The screening mode of the test frequency domain data is not limited in any way.
According to the chip sensitivity test method provided by the embodiment, a certain plurality of test frequency domain data are obtained, and are screened by using the bubbling sequencing method to determine the second frequency domain data of the test signals received by the chip to be tested, so that errors in the test process are reduced, the reliability of the second frequency domain data is improved, and the accuracy of the sensitivity of the test chip is further improved.
In one embodiment, step S101, in a case where the radio frequency test device does not transmit a test signal, acquiring first frequency domain data of a radio frequency signal received by a chip to be tested may include: and under the condition that the radio frequency test equipment does not emit the test signals, acquiring a plurality of first frequency domain data corresponding to the radio frequency signals received by the chip to be tested. Wherein, the frequency points of the radio frequency signals are different.
Based on this, step S102, controlling the radio frequency test device to transmit the test signal to the chip to be tested and obtain the second frequency domain data of the test signal received by the chip to be tested may include: and controlling the radio frequency test equipment to respectively transmit a plurality of test signals to the chip to be tested, and respectively acquiring a plurality of second frequency domain data corresponding to the plurality of test signals received by the chip to be tested. The frequency points of the test signals are different, and each radio frequency signal corresponds to the test signal with the same frequency point.
For example, if the chip to be tested has a plurality of frequency points to be tested, the step of acquiring a plurality of first frequency domain data corresponding to the plurality of radio frequency signals received by the chip to be tested under the condition that the radio frequency test device does not transmit the test signals may be performed first, and then the step of controlling the radio frequency test device to respectively transmit the plurality of test signals to the chip to be tested and respectively acquire a plurality of second frequency domain data corresponding to the plurality of test signals received by the chip to be tested may be performed. Based on the above, the test of all the frequency points to be tested can be completed according to the first frequency domain data and the second frequency domain data, and the test efficiency of the sensitivity of the chip is improved.
In one embodiment, before controlling the radio frequency test device to transmit the plurality of test signals to the chip under test, the chip sensitivity test method may further include: and receiving the message to be tested sent by the chip to be tested. The message to be tested comprises a plurality of frequency points of the radio frequency signal.
Based on this, step S102, controlling the radio frequency test device to respectively transmit a plurality of test signals to the chip to be tested may include: and controlling the radio frequency test equipment to respectively transmit a plurality of test signals corresponding to a plurality of frequency points of the radio frequency signals to the chip to be tested according to the message to be tested.
According to the chip sensitivity test method provided by the embodiment, the to-be-tested chip can be determined to finish receiving and processing the radio frequency signal according to the to-be-tested message, and the to-be-tested message comprises the frequency point of the radio frequency signal, so that the radio frequency test equipment can be controlled to transmit the test message of the frequency point corresponding to the radio frequency signal to the to-be-tested chip according to the to-be-tested message, the receiving and test of the radio frequency signal and the test signal of the same frequency point are realized, and the efficiency and reliability of the chip sensitivity test are improved.
In one embodiment, as shown in fig. 4, step S103, determining the sensitivity of the chip to be tested according to the second frequency domain data and the first frequency domain data may include the following steps S401 to S403.
S401: a frequency domain data difference of the first frequency domain data and the second frequency domain data is calculated.
The frequency domain data difference value is used for identifying the receiving sensitivity of the chip to be tested, which is not interfered by the environment, and is marked as CNR. Specifically, cnr=avg_2-avg_1=-N. Illustratively, when the first frequency domain data and the second frequency domain data are both characterized as power, a power difference CNR of the first frequency domain data and the second frequency domain data is calculated.
S402: and under the condition that the frequency domain data difference value is in a preset range, determining that the sensitivity of the chip to be tested is qualified.
The preset range may be preset according to experiments and experience, which is not limited in this application. If the frequency domain data difference value is in the preset range, namely, the frequency domain data difference value is in the preset range, the receiving sensitivity of the chip to be tested meets the requirement, and in this case, the sensitivity performance of the chip to be tested can be determined to meet the requirement, and the chip to be tested is qualified.
S403: and under the condition that the frequency domain data difference value is not in a preset range, determining that the sensitivity of the chip to be tested is unqualified.
If the frequency domain data difference value is not in the preset range, namely exceeds the preset range, the receiving sensitivity of the chip to be tested does not meet the requirement, and under the condition, the fact that the sensitivity performance of the chip to be tested does not meet the requirement and the chip to be tested is unqualified can be determined.
According to the chip sensitivity test method provided by the embodiment, the frequency domain data difference value of the first frequency domain data and the second frequency domain data is calculated, and whether the frequency domain data difference value is within the preset range or not is judged, so that whether the sensitivity performance of the chip to be tested is qualified or not is judged. Because the frequency domain data difference value eliminates the environmental radio frequency interference, the sensitivity of the chip is judged based on the frequency domain data difference value, and the interference or noise in the environment is effectively avoided, thereby enhancing the anti-interference performance of the chip sensitivity test and improving the accuracy and reliability of the chip sensitivity test.
In one embodiment, the number of chips to be tested is plural, and each chip to be tested is correspondingly connected to a different radio frequency test device. Based on this, as shown in fig. 5, before the first frequency domain data of the radio frequency signal received by the chip to be tested is acquired in step S101, the chip sensitivity test method may further include the following steps S501 and S502.
S501: each radio frequency test device is configured to be in a silence state in which it does not transmit test signals.
S502: and initializing each chip to be tested to close the transmitting passage of each chip to be tested and open the receiving passage of each chip to be tested.
The chip sensitivity test method provided by the embodiment is applied to the test scenes of a plurality of chips to be tested, ensures the anti-interference performance of the chip sensitivity test, realizes the multi-site parallel test, and improves the test efficiency of the chip sensitivity.
The step S101 is performed again, to obtain the first frequency domain data of the radio frequency signals received by each chip to be tested, so as to realize synchronous testing on a plurality of chips to be tested, and improve the testing efficiency of the sensitivity of the chips.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the method for testing the sensitivity of the chip provided by the embodiment, the application also provides a system for testing the sensitivity of the chip. As shown in fig. 6, the chip sensitivity test system may include a radio frequency test device 601, a chip under test 602, and a test station 603.
Wherein the radio frequency test device 601 is arranged to transmit a test signal. The chip under test 602 is connected to the radio frequency test device 601, and illustratively, the chip under test 602 may be connected to the radio frequency test device 601 through a radio frequency feeder. The chip under test 602 is configured to receive a radio frequency signal and output first frequency domain data when the radio frequency test device 601 does not transmit a test signal. The chip under test 602 is further configured to receive the test signal and output second frequency domain data when the radio frequency test device 601 transmits the test signal. The first frequency domain data and the second frequency domain data are the same frequency point, the test machine 603 is respectively connected with the radio frequency test device 601 and the chip 602 to be tested, the test machine 603 is used for controlling the radio frequency test device 601 to emit test signals, and is also used for acquiring the first frequency domain data and the second frequency domain data, and determining the sensitivity of the chip 602 to be tested according to the first frequency domain data and the second frequency domain data.
The chip sensitivity test system provided in the above embodiment includes a radio frequency test device 601, a chip to be tested 602, and a test machine 603. Because the radio frequency signal comprises the interference signal in the environment when no test signal exists, the test signal also comprises the interference signal in the environment, the first frequency domain data marks the sensitivity of the chip to be tested for receiving the radio frequency signal, and the second frequency domain data marks the sensitivity of the chip to be tested for receiving the test signal transmitted by the radio frequency test equipment, therefore, the interference of the environment in the second frequency domain data to the sensitivity of the chip to be tested can be eliminated based on the first frequency domain data, so that a more accurate sensitivity test result is obtained, the anti-interference capability of the chip sensitivity test is enhanced, the test accuracy of the chip sensitivity is improved, and the normal running of a test scene with smaller test signal is ensured.
In one embodiment, as shown in fig. 7, the chip sensitivity test system includes a plurality of chips under test 602 and a plurality of different radio frequency test devices 601 respectively connected to the chips under test 602. Wherein each chip under test 602 and its associated radio frequency test device 601 form a very basic layout cell (SITE). Based on this, the test machine 603, the plurality of chips to be tested 602, and the plurality of radio frequency test devices 601 form a multi-SITE test scenario. Wherein the transmit path of each die under test 602 is closed and the receive path is open. Illustratively, the receive path of the chip under test 602 may be the receive path of a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART). Based on the above, the environmental interference in the chip sensitivity test process is effectively avoided, the multi-SITE parallel test is realized, namely, the multi-SITE test can be simultaneously performed by using one test machine 603, a shielding room or a shielding cover is not required to be additionally arranged, and the test efficiency and the test cost of the chip sensitivity are greatly improved.
In one embodiment, as shown in fig. 8, the receive path of the chip under test 602 may include an antenna 6021, an automatic gain control module 6022, an analog-to-digital sampling module 6023, and a fourier transform module 6024.
Wherein an antenna 6021 is connected to the radio frequency test device 601, the antenna 6021 is configured to receive a radio frequency signal if the radio frequency test device 601 does not transmit a test signal, and the antenna 6021 is further configured to receive a test signal transmitted by the radio frequency test device 601.
An automatic gain control module (Automatic Gain Control, AGC) 6022 is connected to the antenna 6021, and the automatic gain control module 6022 is configured to adjust the gain of the radio frequency signal or the test signal received by the antenna 6021 and output an analog signal. The automatic gain control modules 6022 of the chips 602 to be tested have the same receiving gain, and keep the gain of the chips 602 to be tested synchronously changed. By way of example, the automatic gain control module 6022 may include a Low noise amplifier (Low Noise Amplifier, LNA) 6022a, a Down Mixer (DM) 6022b, and a Low Pass Filter (LPF) 6022c connected in sequence. The low noise amplifier 6022a is connected to the antenna 6021 and the down-conversion mixer 6022b, and the low pass filter 6022c is connected to the down-conversion mixer 6022b and the analog-to-digital sampling module 6023.
The analog-to-digital sampling module (analog to digital converter, ADC) 6023 is connected to the automatic gain control module 6022, and the analog-to-digital sampling module 6023 is configured to sample the analog signal according to a preset sampling frequency and generate a digital signal. Wherein, by presetting the sampling frequency, the analog-to-digital sampling module 6023 is prevented from oversampling.
The fourier transform module 6024 (Fourier Transformation, FFT) is connected to the analog-to-digital sampling module 6023, and the fourier transform module 6024 is configured to fourier transform the digital signal and generate frequency domain data. The frequency domain data comprises first frequency domain data of the radio frequency signal or second frequency domain data of the test signal.
The chip sensitivity test system provided in the above embodiment, where the chip 602 to be tested includes an antenna 6021, an automatic gain control module 6022, a digital-to-analog conversion module 6023 and a fourier transform module 6024, so as to receive a radio frequency signal or a test signal, and correspondingly output first frequency domain data or second frequency domain data, thereby implementing the test of the chip sensitivity.
For better understanding, taking the chip sensitivity test system shown in fig. 7 as an example, as shown in fig. 9, another chip sensitivity test method is provided. The sensitivity test method may include the following steps S901 to S911.
S901: and starting the test, powering up each SITE at the same time, enabling the radio frequency test equipment to enter a silent state, and enabling each DUT to be in an initialized state. The radio frequency test equipment does not transmit any radio frequency signals, and meanwhile, the UART serial communication transmitting channels of all DUTs are closed, and only UART serial receiving functions are reserved, namely, after all DUTs are initialized, the UART serial receiving functions are in a state that the Bluetooth transmitting functions are closed and the receiving functions are opened. In order to make the SITE steps as uniform as possible, the step S902 is performed after a predetermined period of time.
S902: the AGC of each DUT is set to a state where the gains are the same and the gains are synchronously changed, and meanwhile, the ADC is ensured not to be over-sampled.
S903: the DUT sets the corresponding receiving frequency Freq1, and then carries out FFT conversion on the sampling data of the output of the ADC to obtain first frequency domain data, namely a power value.
S904: step S903 is repeated until a certain statistical quantity of radio frequency domain data is obtained, the maximum value and the minimum value are removed by using an bubbling sequencing method, the average value is taken and marked as avg_1 or N, and the obtained data is equivalent to a background noise power value.
S905: and repeating the step S903 and the step S904, namely only replacing the receiving frequency (channel), completing the test of different frequency points (frequencies), and respectively recording the power values of the corresponding frequency points until all the frequency points to be tested are tested.
S906: the DUT sends signals to inform the corresponding radio frequency test equipment to send test signals with corresponding frequencies to the DUT through the UART serial module, so that further testing is performed.
S907: repeating step S903 and step S904, and recording the obtained average value as avg_2 orThe power value of the test signal is obtained at this time, and the test signal also has a certain environmental radio frequency interference, namely the total power of the background noise and the test signal.
S908: calculation of avg_2-avg_1 or-N, the resulting power difference is denoted CNR, the difference being processed such that the ambient radio frequency interference cancel each other.
S909: and repeating the steps S906, S907 and S908, and respectively recording the data of the corresponding frequency points until all the frequency points to be tested are tested, thereby obtaining CNR values of different frequency points.
S910: the radio frequency test equipment enters a silent state again, the DUT pushes CNR data obtained by testing to a test machine, and the test machine performs chip card value screening; if the test value is out of the card value range, the sensitivity performance of the chip is not up to standard; otherwise, the chip is considered to meet the preset sensitivity performance requirement.
S911: the next batch of chips to be tested is replaced, and step S901 is executed again.
The conventional method is compared with the chip sensitivity test method provided by the embodiment of the application by combining a specific application scene. The sensitivity calculation formula is:
（1）
wherein, the liquid crystal display device comprises a liquid crystal display device,indicating sensitivity; k represents a Boltzmann constant; t represents absolute temperature; BW represents bandwidth; NF represents the noise figure; SNR represents the signal-to-noise ratio.
The bottom noise power measured by the chip is recorded as N (dBm), and the total power is received(dBm) in terms of a power value in mW, based on +.>Available->According to->Is available in the form ofThen->. The parameter noted "1" is from the measurement of chip 1 and the parameter noted "2" is from the measurement of chip 2. Let the noise floor power->、/>Are all-120 dBm, the receiving power of the test signal is +.>、/>Are all-90 dBm (/ -for)>The actual power of the instrument to the chip receiver, and not the background noise).
Application scenario one: the chip gains are different and it is assumed that the reception gain of chip 1 is +2dB higher than the reception gain of chip 2.
(1) In the related art, whether the receiving function of the chip to be tested is good or bad can be judged by judging whether the background noise value of the test chip is smaller than a preset value. Specifically, if the background noise power of the chip 1 is-120 dBm, and the receiving gain of the chip 1 is +2dB higher than that of the chip 2, the background noise actual measurement value of the chip 2 is-118 dBm, and the sensitivity of the chip 1 is better than that of the chip 2 by the background noise value alone, which is inconsistent with the sensitivity of the actual chip 1 and the chip 2. From this, it is clear that the test method reflects insufficient accuracy of the sensitivity of the chip because the gain is different between chips, and the noise is high and the sensitivity is not necessarily poor.
(2) Based on the chip sensitivity test method provided by the application, the sensitivity calculation formulas of the chip 1 and the chip 2 are specifically as follows:
（2）
（3）
based on the above-mentioned knowledge that,the test result accurately reflects that the sensitivity of the chip 1 and the sensitivity of the chip 2 are consistent with the actual situation. Therefore, the scheme can effectively avoid the situation that misjudgment is caused by different gains of the chips, and compared with a method for judging the sensitivity of the chips by directly adopting the bottom noise value, the accuracy of testing the sensitivity of the chips is higher.
And (2) an application scene II: the gain of the chip receiving paths is the sameBut with different noise floor>。
(1) In the related art, a test instrument transmits a test signal with a certain power to judge whether the value of the received power of a chip tested at a corresponding frequency point is in a certain range, so as to judge whether the receiving function of the chip to be tested is good or bad. That is, the sensitivity is represented by the total received power, and the sensitivities of the chip 1 and the chip 2 are respectively:
（4）
（5）/>
if it is，/>Then->、/>Both were-89.996 dB, in which case the results of the measurements were the same. However, if->= -120, and->= -122, then->Is-89.996 dB, and +.>At-89.993 dB, the difference between the two is very small, the total power difference is only 0.003dB, but the actual background noise is already 2dB different, and the test result cannot accurately show the actual value. Therefore, compared with the power of the test signal, the background noise power is much smaller, the background noise of the chip is submerged in the total receiving power, and the background noise is lower according to a sensitivity calculation formula, the sensitivity is lower, so that the accuracy of the test method for reflecting the sensitivity is insufficient.
(2) Based on the chip sensitivity test method provided by the application, assume that=-120dBm、/>= -118dBm, then the sensitivity of chip 1 and chip are respectively:
（6）
（7）
based on the above-mentioned knowledge that,the difference value is very close to the difference value of the background noise by 2dB, the actual sensitivity of the chip is well reflected, and compared with the method for judging the sensitivity of the chip by directly adopting the total power of the received signal, the method has the advantages that the testing accuracy of the sensitivity of the chip is higher, and the sensitivity error is effectively avoidedAnd (5) judging.
By combining the scenes and the specific numerical calculation process, the technical scheme solves various problems that the chip gains are different, the bottom noise is submerged in the received total power, the small signals are easy to be interfered by the environment and difficult to test, and the like, does not need to additionally add a shielding room, has no strict requirements on the test space environment, can simultaneously realize multi-SITE parallel test, reduces the test cost, improves the test efficiency, also improves the test accuracy, ensures that the chip performance obtained by screening can keep high consistency, and is simple and easy to implement.
Based on the same inventive concept, the embodiment of the application also provides a chip sensitivity testing device for realizing the above related chip sensitivity testing method. The implementation of the solution provided by the device is similar to that described in the above method, so the specific limitation of the embodiment of the device for testing the sensitivity of one or more chips provided below may be referred to the limitation of the method for testing the sensitivity of the chips hereinabove, and will not be repeated here.
In one embodiment, as shown in FIG. 10, a chip sensitivity test apparatus is provided. The chip sensitivity test apparatus 1100 may include a first acquisition module 1101, a second acquisition module 1102, and a determination module 1103.
The first obtaining module 1101 is configured to obtain, when the radio frequency test device does not transmit the test signal, first frequency domain data of the radio frequency signal received by the chip to be tested. The radio frequency test equipment is connected with the chip to be tested.
The second obtaining module 1102 is configured to control the radio frequency test device to transmit the test signal to the chip to be tested, and obtain second frequency domain data of the chip to be tested for receiving the test signal. The frequency points of the radio frequency signal and the test signal are the same.
The determining module 1103 is configured to determine the sensitivity of the chip to be tested according to the second frequency domain data and the first frequency domain data.
In one embodiment, the first obtaining module 1101 is configured to obtain, when the radio frequency test device does not transmit the test signal, radio frequency domain data of the radio frequency signal received by the chip to be tested, for multiple times; and screening a plurality of radio frequency domain data by using an bubbling sequencing method to determine first frequency domain data of radio frequency signals received by the chip to be tested, wherein the first frequency domain data is used for representing power.
In one embodiment, the second obtaining module 1102 is configured to control the radio frequency test device to transmit the test signal to the chip to be tested for multiple times, and correspondingly obtain test frequency domain data received by the chip to be tested for multiple times respectively; screening a plurality of the test frequency domain data by using an bubbling sequencing method to determine second frequency domain data of the test signals received by the chip to be tested; wherein the second frequency domain data is used to characterize power.
In one embodiment, the first obtaining module 1101 is configured to obtain, when the radio frequency test device does not transmit the test signal, a plurality of first frequency domain data corresponding to the plurality of radio frequency signals received by the chip to be tested; wherein, the frequency point of each radio frequency signal is different. The second obtaining module 1102 is configured to control the radio frequency testing device to respectively transmit a plurality of test signals to the chip to be tested, and respectively obtain a plurality of second frequency domain data corresponding to the plurality of test signals received by the chip to be tested; the frequency points of the test signals are different, and each radio frequency signal corresponds to the test signal with the same frequency point.
In one embodiment, the chip sensitivity testing apparatus 1100 may further include a receiving module, where the receiving module is configured to receive a message to be tested sent by the chip to be tested, and the message to be tested includes a plurality of frequency points of the radio frequency signal. The first obtaining module 1101 is configured to control the radio frequency test device to respectively transmit a plurality of test signals corresponding to a plurality of frequency points of the radio frequency signal to the chip to be tested according to the message to be tested.
In one embodiment, the determining module 1103 is configured to calculate a frequency domain data difference value between the first frequency domain data and the second frequency domain data; under the condition that the frequency domain data difference value is in a preset range, determining that the sensitivity of the chip to be tested is qualified; and under the condition that the frequency domain data difference value is not in the preset range, determining that the sensitivity of the chip to be tested is unqualified.
In one embodiment, the number of the chips to be tested is plural, and each chip to be tested is correspondingly connected with different radio frequency test devices. The chip sensitivity test apparatus 1100 may further include an initialization module for configuring each of the radio frequency test devices to a silent state in which no test signal is emitted; and initializing each chip to be tested to close the transmitting passage of each chip to be tested and open the receiving passage of each chip to be tested.
In one embodiment, a computer device is provided, which may be a server, and the internal structure of which may be as shown in fig. 11. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used to store frequency domain data and chip sensitivity data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of testing the sensitivity of a chip.
It will be appreciated by those skilled in the art that the structure shown in fig. 11 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the computer device to which the present application applies, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor implementing the steps of the chip sensitivity test method provided in any of the embodiments above when executing the computer program.
In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a processor implements the steps of the chip sensitivity test method provided by any of the above embodiments.
In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the chip sensitivity test method provided by any of the above embodiments.
The data (including, but not limited to, data for analysis, data stored, data displayed, etc.) referred to in this application are information and data authorized by the user or sufficiently authorized by each party.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the various embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magnetic random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (Phase Change Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like. The databases referred to in the various embodiments provided herein may include at least one of relational databases and non-relational databases. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic units, quantum computing-based data processing logic units, etc., without being limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (13)
1. A method for testing sensitivity of a chip, comprising:
under the condition that the radio frequency test equipment does not emit test signals, respectively acquiring first frequency domain data of the radio frequency signals received by the chips to be tested; the first frequency domain data are used for representing the background noise power;
Controlling each radio frequency test device to transmit the test signal to the corresponding chip to be tested, and respectively acquiring second frequency domain data of each chip to be tested for receiving the test signal; the radio frequency signal and the test signal have the same frequency point, and the second frequency domain data is used for representing the total power corresponding to the test signal comprising the background noise;
and determining the difference value of the second frequency domain data and the first frequency domain data as the sensitivity of each chip to be tested.
2. The method for testing the sensitivity of a chip according to claim 1, wherein the step of acquiring the first frequency domain data of the radio frequency signals received by the plurality of chips to be tested when the radio frequency test device does not transmit the test signals, respectively, includes:
under the condition that the radio frequency test equipment does not emit the test signals, respectively acquiring radio frequency domain data of the radio frequency signals received by the chips to be tested for multiple times;
and screening a plurality of radio frequency domain data by using an bubbling sequencing method to determine the first frequency domain data of the radio frequency signals received by each chip to be tested.
3. The method according to claim 1, wherein controlling each of the radio frequency test devices to transmit the test signal to the corresponding chip to be tested and obtain second frequency domain data of each of the chips to be tested to receive the test signal, respectively, comprises:
Controlling each radio frequency test device to transmit the test signals to the corresponding chip to be tested for multiple times, and correspondingly acquiring test frequency domain data received by each chip to be tested for multiple times respectively;
and screening a plurality of the test frequency domain data by using an bubbling sequencing method to determine the second frequency domain data of the test signals received by each chip to be tested.
4. The method for testing the sensitivity of a chip according to claim 1, wherein the step of acquiring the first frequency domain data of the radio frequency signals received by the plurality of chips to be tested when the radio frequency test device does not transmit the test signals, respectively, includes:
under the condition that the radio frequency test equipment does not transmit the test signals, respectively acquiring a plurality of first frequency domain data corresponding to the radio frequency signals received by the chips to be tested; wherein, the frequency points of the radio frequency signals are different;
the controlling each radio frequency test device to transmit the test signal to the corresponding chip to be tested, and respectively obtaining the second frequency domain data of each chip to be tested for receiving the test signal, includes:
controlling each radio frequency test device to respectively transmit a plurality of test signals to the corresponding chip to be tested, and respectively acquiring a plurality of second frequency domain data corresponding to the plurality of test signals received by each chip to be tested; the frequency points of the test signals are different, and each radio frequency signal corresponds to the test signal with the same frequency point.
5. The chip sensitivity test method according to claim 4, wherein before controlling the radio frequency test device to transmit a plurality of test signals to the chip under test, respectively, the chip sensitivity test method further comprises:
receiving a message to be tested sent by each chip to be tested, wherein the message to be tested comprises a plurality of frequency points of the radio frequency signal; wherein, the liquid crystal display device comprises a liquid crystal display device,
the controlling each radio frequency test device to transmit the test signal to the corresponding chip to be tested includes:
and controlling each radio frequency test device to respectively transmit a plurality of test signals corresponding to a plurality of frequency points of the radio frequency signals to the corresponding chip to be tested according to the message to be tested.
6. The chip sensitivity test method according to claim 1, further comprising:
under the condition that the difference value is in a preset range, determining that the sensitivity of the chip to be tested is qualified;
and under the condition that the difference value is not in the preset range, determining that the sensitivity of the chip to be tested is unqualified.
7. The method according to claim 1, wherein before the acquiring the first frequency domain data of the radio frequency signals received by the plurality of chips to be tested, the method further comprises:
Configuring each of the radio frequency test devices to a silence state in which no test signal is transmitted;
and initializing each chip to be tested to close the transmitting passage of each chip to be tested and open the receiving passage of each chip to be tested.
8. A chip sensitivity test system, comprising:
a plurality of radio frequency test devices;
the chips to be tested are correspondingly connected with the radio frequency test equipment respectively and are used for receiving radio frequency signals and outputting first frequency domain data under the condition that the radio frequency test equipment does not emit test signals; the chip to be tested is also used for receiving the test signal and outputting second frequency domain data under the condition that the radio frequency test equipment transmits the test signal; the gains of the receiving paths of at least two chips to be tested are the same and the bottom noises are different, the gains of the receiving paths of at least two chips to be tested are different and the bottom noises are the same, the first frequency domain data are used for representing the bottom noise power, and the second frequency domain data are used for representing the total power corresponding to the test signals comprising the bottom noises;
the test machine table is respectively connected with the radio frequency test equipment and the chips to be tested, and is used for controlling the radio frequency test equipment to emit the test signals, acquiring the first frequency domain data and the second frequency domain data, and determining the difference value of the first frequency domain data and the second frequency domain data as the sensitivity of the chips to be tested.
9. The chip sensitivity test system according to claim 8, wherein a transmit path and a receive path of each of the chips under test are closed and open.
10. The chip sensitivity test system according to claim 9, wherein the receiving path of the chip under test includes:
the antenna is connected with the radio frequency test equipment and is used for receiving radio frequency signals or receiving the test signals transmitted by the radio frequency test equipment under the condition that the radio frequency test equipment does not transmit the test signals;
the automatic gain control module is connected with the antenna, and is used for adjusting the gain of the radio frequency signal or the test signal and outputting an analog signal; the automatic gain control modules of the chips to be tested have the same receiving gain and keep the gain of the chips to be tested synchronously changed;
the analog-to-digital sampling module is connected with the automatic gain control module and is used for sampling the analog signal according to a preset sampling frequency and generating a digital signal;
and the Fourier transform module is connected with the analog-to-digital sampling module and is used for carrying out Fourier transform on the digital signals and generating frequency domain data, wherein the frequency domain data comprises first frequency domain data of the radio frequency signals or second frequency domain data of the test signals.
11. A chip sensitivity test apparatus, comprising:
the first acquisition module is used for respectively acquiring first frequency domain data of radio frequency signals received by the chips to be tested under the condition that the radio frequency test equipment does not transmit the test signals; the first frequency domain data are used for representing the background noise power;
the second acquisition module is used for controlling each radio frequency test device to transmit the test signal to the corresponding chip to be tested and respectively acquiring second frequency domain data of each chip to be tested for receiving the test signal; the radio frequency signal and the test signal have the same frequency point, and the second frequency domain data is used for representing the total power corresponding to the test signal comprising the background noise;
and the determining module is used for determining the difference value between the second frequency domain data and the first frequency domain data as the sensitivity of each chip to be detected.
12. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the chip sensitivity test method according to any one of claims 1 to 7 when executing the computer program.
13. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the chip sensitivity test method according to any one of claims 1 to 7.
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