CN116030859A

CN116030859A - Refreshing control circuit and memory

Info

Publication number: CN116030859A
Application number: CN202310103297.3A
Authority: CN
Inventors: 谷银川
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-02-13
Filing date: 2023-02-13
Publication date: 2023-04-28
Anticipated expiration: 2043-02-13
Also published as: CN116030859B

Abstract

The present disclosure relates to the field of integrated circuits, and discloses a refresh control circuit and a memory. Wherein the refresh control circuit includes: the device comprises a sign signal generating module, an address sampling module and an executing module. And the mark signal generating module is configured to receive the refresh command and generate n refresh mark signals according to the continuously received refresh command, wherein n is a positive integer. The address sampling module is connected with the mark signal generating module and is configured to receive n refresh mark signals and respond to the n refresh mark signals to sequentially select and output n hammering row addresses with the largest number of times of being started; and the execution module is connected with the address sampling module and is configured to sequentially receive the n hammering row addresses and sequentially execute refreshing operation on adjacent victim row addresses of the n hammering row addresses. According to the embodiment of the disclosure, the problem of the row hammer can be more pertinently protected, and the effect of protective refreshing is improved.

Description

Refreshing control circuit and memory

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a refresh control circuit and a memory.

Background

With the increasing level of semiconductor manufacturing technology, the density of memory is increasing, the physical size of memory cells is decreasing, word lines in memory cells are physically closer, capacitive coupling between adjacent word lines is increasing, and data stored on memory cells is also more and more susceptible to adjacent memory rows.

At the same time, as the working frequency of the memory is increased, the time for which the word line is turned on is shortened, and the problem of Row Hammer (Row Hammer) of the memory is more and more serious due to frequent or long-time turn-on of the word line, so that the problem of Row Hammer is effectively solved, which is a problem to be solved currently.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a refresh control circuit and a memory, which can more pointedly protect against the row hammer problem, and improve the effect of protective refresh.

The technical scheme of the embodiment of the disclosure is realized as follows:

embodiments of the present disclosure provide a refresh control circuit including: the mark signal generation module is configured to receive a refresh command and generate n refresh mark signals according to the refresh command which is continuously received, wherein n is a positive integer; the address sampling module is connected with the mark signal generating module and is configured to receive n refresh mark signals and sequentially select and output all or part of n hammering row addresses with the largest turn-on times in response to the n refresh mark signals; and the execution module is connected with the address sampling module and is configured to sequentially receive n hammering row addresses and sequentially execute refreshing operation on adjacent victim row addresses of the n hammering row addresses.

In the above aspect, the flag signal generating module is further configured to receive an activation command, and execute a reset operation on n refresh flag signals in response to the activation command.

In the above solution, the address sampling module is further configured to output a default row address when n refresh tag signals are reset; the default row address is the one of the hammer row addresses that is not output and has the largest number of times of being turned on.

In the above solution, the flag signal generating module is further configured to set the ith refresh flag signal to a first level value and set the remaining n-1 refresh flag signals to a second level value when the number of the refresh commands continuously received reaches the ith preset value; i is 1 or more and n or less; the address sampling module is further configured to output an ith hammering row address when only the ith i value is a first level value in the received n refresh flag signals.

In the above aspect, the flag signal generating module is further configured to set n refresh flag signals to the second level value in performing the reset operation.

In the above scheme, the flag signal generation module includes: a counting module and a coding module; the counting module is configured to receive the refresh command, count the refresh command and generate a count value; the encoding module is connected with the counting module and is configured to encode the count value, and generate and output n refreshing mark signals.

In the above scheme, the counting module includes: m cascaded D flip-flops; wherein 2 is ^m Greater than or equal to n; the clock input end of the D trigger of the 1 st level receives a refresh command; the inverting output end of the D trigger of each stage is connected with the data input end of the D trigger; the inverting output end of the D trigger of each stage is also connected with the clock input end of the D trigger of the next stage; and the reset end of the D trigger of each stage receives the activation command.

In the above scheme, the coding module includes: n AND gates; the m input ends of each AND gate are respectively connected with the in-phase output ends or the anti-phase output ends of the m D flip-flops; any two AND gates do not have identical inputs; and the output ends of the n AND gates output n refresh flag signals in one-to-one correspondence.

In the above scheme, the refresh control circuit further includes: a command decoding module; the command decoding module is connected with the sign signal generating module and is configured to decode a refresh command and an activation command and transmit the refresh command and the activation command to the sign signal generating module.

In the above scheme, the address sampling module includes: an address selecting unit configured to select n hammering row addresses with the largest number of times of being turned on from a hammering row address list; the address comparison unit is connected with the address selection unit and is configured to acquire n hammering row addresses, compare the opened times of the n hammering row addresses and sort the n hammering row addresses according to the opened times; and the address output unit is connected with the address comparison unit and is configured to receive the n refresh flag signals and the n hammering row addresses after sequencing, and respond to the n refresh flag signals to sequentially select all or part of the n hammering row addresses after sequencing and output the n hammering row addresses from the output end of the n hammering row addresses after sequencing.

In the above aspect, the address selecting unit is further configured to, when the n refresh flag signals are reset, reselect the n hammer row addresses that are turned on the largest number of times in response to the activation command.

In the above aspect, the address selecting unit is further configured to delete the hammering row address output by the address output unit from the hammering row address list.

In the above aspect, the address output unit includes: n cascaded data selectors; the first input end of each stage of the data selector is connected with the output end of the next stage of the data selector, the first input end of the last stage of the data selector receives the 1 st hammering row address, and the output end of the 1 st stage of the data selector is used as the output end of the address output unit; the second input end of the data selector of the ith stage receives the ith hammering row address, and the control end of the data selector of the ith stage receives the ith refresh flag signal, wherein i is greater than or equal to 1 and less than or equal to n.

In the above scheme, the number of times the 1 st to nth hammering row addresses are turned on is sequentially decreased.

In the above solution, the execution module is further configured to perform a refresh operation on an adjacent victim row address of the hammering row address during a current refresh command or during a next refresh command.

The embodiment of the disclosure also provides a memory, which comprises the refresh control circuit in the scheme.

In the above scheme, the memory is a DRAM.

It can be seen that the embodiments of the present disclosure provide a refresh control circuit and a memory. Wherein the refresh control circuit includes: the device comprises a sign signal generating module, an address sampling module and an executing module. And the mark signal generating module is configured to receive the refresh command and generate n refresh mark signals according to the continuously received refresh command, wherein n is a positive integer. The address sampling module is connected with the mark signal generating module and is configured to receive n refresh mark signals and respond to the n refresh mark signals to sequentially select and output n hammering row addresses with the largest number of times of being started; and the execution module is connected with the address sampling module and is configured to sequentially receive the n hammering row addresses and sequentially execute refreshing operation on adjacent victim row addresses of the n hammering row addresses. Since the larger the number of times of being turned on, the more easily the adjacent memory cells are affected. According to the embodiment of the disclosure, n addresses with the largest opening times are used as the hammering Row addresses, the ordered hammering Row addresses are sequentially selected and output by detecting the number of refreshing commands in burst refreshing, and protective refreshing is performed on the victim Row addresses adjacent to the hammering Row addresses, so that the Row Hammer problem can be more pertinently protected, and the effect of the protective refreshing is improved.

Drawings

FIG. 1 is a schematic diagram depicting burst refresh;

FIG. 2 is a schematic diagram depicting the row hammer problem;

fig. 3 is a schematic diagram of a refresh control circuit according to an embodiment of the present disclosure;

FIG. 4 is a first signal diagram of a refresh control circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a flag signal generating module in a refresh control circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a counting module in a refresh control circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a counting module in a refresh control circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a first structure of a coding module in a refresh control circuit according to an embodiment of the disclosure;

fig. 9 is a schematic diagram ii of a structure of a coding module in a refresh control circuit according to an embodiment of the present disclosure;

FIG. 10 is a second signal diagram of a refresh control circuit according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a second configuration of a refresh control circuit according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of an address sampling module in a refresh control circuit according to an embodiment of the present disclosure;

fig. 13 is a schematic diagram of a structure of an address output unit in a refresh control circuit according to an embodiment of the present disclosure;

Fig. 14 is a schematic diagram of a second structure of an address output unit in the refresh control circuit according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first/second" appears in the present document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first/second/third" may interchange a specific order or precedence, as allowed, to enable embodiments of the disclosure described herein to be implemented in an order other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

The following is an explanation of related art terms in the present disclosure:

row Hammer: is a vulnerability in memory, which is mainly represented by: when an attacker taps (punches) a specific line of memory for several times, the electromagnetic interference causes the memory cells of the other lines to flip (flip) accordingly.

Victim Row: the flipped memory cell Row occurs because of the Row Hammer problem.

Auto-Refresh: at regular intervals, spontaneously occurring refreshing in the memory; wherein the bank (bank) and Row addresses to be refreshed are determined by an internal refresh controller.

burst refresh: refresh by burst operation to compensate Auto-Refresh not performed during read/write operation; during burst refresh, the memory will suspend read/write operations and no activate command will be issued.

FIG. 1 illustrates auto-refresh and burst refresh in a memory. Referring to FIG. 1, during auto-refresh, every interval t _REFI A refresh command is issued; during read/write operations, auto-refresh is suspended and the issuance of refresh commands is suspended. Accordingly, after the read/write operation is completed, burst refresh is added to the memory to compensate for the lack of refresh in the read/write operation. During burst refresh, refresh commands are issued centrally. Taking fig. 1 as an example, the read/write operation duration is 9*t _REFI 8 refresh commands are missing; then, during the burst refresh,there are 8 refresh commands issued centrally, with a time interval t between two adjacent refresh commands _RFC 。

In a memory, for example, a DRAM (dynamic random access memory), there is a problem of Row Hammer. In this way, reading from and writing to a single region of memory can interfere with adjacent regions, causing current to flow into or out of adjacent memory cells. Further, if a large number of reads and writes are repeated, it is possible to change the contents of adjacent memory cells so that 0 becomes 1 or 1 becomes 0, a phenomenon called bit flipping (bit-flipping). Bit flipping may be used to gain higher authority, for example, to use bit flipping to make violent modifications to the data, thereby threatening the security of the data.

As shown in fig. 2, under the triggering of the activate command, the memory performs the read/write operation, and further, the memory rows repeatedly performing a large number of reads and writes become hammer rows, and accordingly, the memory rows adjacent to the hammer rows become victim rows, and there is a risk of bit flip in the victim rows. That is, consecutive read/write operations accumulate a large number of hammer row addresses.

In the related art, protection design for the Row Hammer problem is: target Row Refresh (target row refresh) is performed. Target Row Refresh is specifically made by the following steps: the potential Row address of the Row Hammer victim is grabbed and embedded into Auto-Refresh to perform a protective Refresh of the Row address victim to avoid bit flipping. For example, one can at t of each Auto-Refresh _RFC Taking out specific time, and performing protective refreshing specifically for the Row Hammer problem, namely performing protective refreshing on the victim Row address in the Row Hammer protection time; wherein t can be from two refresh commands _REFI Within the interval, the victim row address with the highest probability is selected from among the activated addresses.

However, the address is activated requiring triggering of an activate command, and no activate command is issued during burst refresh, that is, the activated address cannot be selected as the Victim Row address during burst refresh. Thus, it is usually a few The fixed address (i.e., reset address) is protectively refreshed within the Row Hammer guard time of the sub-burst refresh. However, in doing so, repeated refreshing of the reset address may, on the one hand, cause new Row Hammer problems, changing the contents of the memory cells adjacent to the reset address. On the other hand, before burst refresh is performed, there is typically a case of continuous reading/writing because: there is no refresh command for a period of time of continuous read/write, so that burst refresh is needed to compensate for the missing refresh command after the continuous read/write is completed. Meanwhile, since the memory activates operation at a large number of memory row addresses for a period of time of continuous reading/writing, a large number of row hammer row addresses and victim row addresses are accumulated; however, since there are no refresh commands during consecutive reads/writes, these victim row addresses may not be refreshed in time, e.g., for DDR5, the consecutive reads/writes may remain 9*t in fine refresh mode _REFI I.e. every 9*t _REFI A protective refresh is triggered and in normal refresh mode, continuous read/write operation may be maintained 5*t _REFI I.e. every 5*t _REFI The one-time protection refreshing can be triggered, so that the problem of Row Hammer is more difficult to solve, and the design difficulty is improved.

In summary, in the related art, it is difficult to effectively solve the Row Hammer problem during burst refresh of the memory.

Fig. 3 is a schematic diagram of an alternative configuration of a refresh control circuit provided in an embodiment of the present disclosure, as shown in fig. 3, the refresh control circuit includes: a flag signal generation module 101, an address sampling module 102, and an execution module 103. The Flag signal generation module 101 is configured to receive the refresh command REF and generate n refresh Flag signals burst_flag according to the refresh command REF received consecutively, n being a positive integer. The address sampling module 102 is connected with the Flag signal generating module 101, and is configured to receive n refresh Flag signals burst_flag, and respond to the n refresh Flag signals burst_flag, and sequentially select and output all or part of n hammering row addresses hammer_addr with the largest number of times of being started. The execution module 103 is connected to the address sampling module 102 and configured to sequentially receive the n hammering row addresses hammer_addr and sequentially perform a refresh operation on adjacent Victim row addresses victim_addr of the n hammering row addresses hammer_addr.

In the disclosed embodiment, referring to fig. 3, the refresh command REF is issued during burst refresh of the memory, and thus, the protective refresh of the victim Row address can be controlled during burst refresh to solve the Row Hammer problem. Each refresh command REF corresponds to one command pulse, and the refresh commands REF during Burst refresh are consecutive command pulses, and the Flag signal generation module 101 may count the number of refresh commands REF that are continuously received (i.e., the number of command pulses) to generate n refresh Flag signals burst_flag. Different count values of the refresh command REF correspond to different refresh Flag signals burst_flag, respectively, and therefore, the high level times of any two refresh Flag signals burst_flag are different.

It should be noted that, during each refresh command REF, multiple refreshes may be performed, where several protective refreshes to the Row Hammer problem may be reserved, and 2 refreshes are reserved as protective refresh operations in the present disclosure. The n Hammer row addresses Hammer Addr acquired in the embodiment of the present disclosure may be refreshed in 2 protective refresh operations reserved during each refresh command REF. Also, multiple rows may be opened simultaneously per refresh, e.g.,

rows

1, 2, and 4 simultaneously. Thus, the address sampling module 102 may output a plurality of hammering row addresses, for example, 1, 2 or 4 hammering rows to the execution module 103 at the same time, triggered by one refresh Flag signal burst_flag. Furthermore, the execution module 103 may perform protective refreshing on the victim row address on both sides of the received hammering row address by using 2 protective refreshing operations reserved during the present refresh command REF, that is, perform 1 protective refreshing on the victim row address on one side of the hammering row address, and perform another 1 protective refreshing on the victim row address on the other side of the hammering row address. In this way, the protective refresh of the neighboring rows of these hammer row addresses can be completed during the current refresh Flag signal burst_flag.

In another embodiment of the present disclosure, referring to fig. 3, the flag signal generation module 101 is further configured to receive an enable signal, and control activation of the flag signal generation module according to the enable signal. In still another embodiment of the present disclosure, the controller (not shown in fig. 3) may simultaneously transmit an identification signal of one burst refresh, which may be used as an enable signal of the flag signal generation module 101, when transmitting the refresh command REF. In this way, under the condition that no identification signal exists, the refresh control circuit does not need to be started, and the mark signal generation module 101 can control the refresh control circuit to stop acting, so that the power consumption of the refresh control circuit is saved.

Fig. 4 is a schematic waveform diagram of an alternative to the refresh command and refresh flag signals. In some embodiments of the present disclosure, as shown in fig. 4, the refresh Flag signals are 8 in total, and are Burst1_flag to Burst8_flag, respectively. In Burst refresh (Burst refresh) mode, the controller does not transmit the active command ACT (i.e., the active command ACT remains low), and when the controller continuously transmits 8 refresh commands REF, burst1_flag to Burst8_flag are sequentially set to high level as the number of refresh commands REF increases. Specifically, when the number of the refresh commands REF continuously received reaches 1, only the 1 st refresh Flag signal Burst1_flag is set to a high level, and the remaining 7 refresh Flag signals are set to low levels; when the number of the received refresh commands REF reaches 2, only the 2 nd refresh Flag signal Burst2_flag is set to high level, and the remaining 7 refresh Flag signals are set to low level; and so on until the last refresh Flag signal Burst8 Flag is set high.

In the embodiment of the present disclosure, with continued reference to fig. 3, the address sampling module 102 sequentially selects and outputs n hammering row addresses hammer_addr under the control of n refresh Flag signals burst_flag. The Hammer row address hammer_addr may be n addresses that are turned on the most times before the current burst refresh.

In some embodiments, the number of refresh commands that the controller continuously sends in burst refresh mode is variable. When the number of consecutively transmitted refresh commands is different, as described above, the number of refresh flag signals that can be set to high level is different (i.e., not necessarily n) as the number of burst refresh commands increases, and further, the number of addresses that can be sequentially selected and outputted from n hammer row addresses in response to the n refresh flag signals is also different. For example, the number of refresh commands sent consecutively is any of 4-9, and the maximum count for burst refresh commands is also 4-9; when the number of consecutively transmitted refresh commands is 4, n (n=9) refresh Flag signals, which can be set to high level as the number of Burst refresh commands increases, are Burst1_flag to Burst4_flag, and the address which can be selectively output from n hammer row addresses in response to the n refresh Flag signals is the 4 addresses with the largest number of times of being turned on; similarly, when the number of consecutively transmitted refresh commands is 9, the address outputted from the n hammer row addresses may be selected as the 9 addresses having the largest number of times of being turned on in response to the n refresh flag signals.

In the embodiment of the present disclosure, with continued reference to fig. 3, after receiving n hammering row addresses hammer_addr, the execution module 103 may determine a Victim row address victim_addr from addresses adjacent to each hammering row address hammer_addr, for example, determine addresses +1/-1, +2/-2, +3/-3 … on the basis of hammering row addresses hammer_addr as Victim row addresses victim_addr, where addresses adjacent to hammering row addresses +1/-1 are described as Victim row addresses in the present disclosure. In turn, the execution module 103 may perform a protective refresh on the Victim row address Victim_addr.

It will be appreciated that the greater the number of times that is turned on, the more likely it is to affect adjacent memory cells. According to the embodiment of the disclosure, n addresses with the largest opening times are used as the hammering Row addresses hammer_addr, the ordered hammering Row addresses are sequentially selected and output by detecting the number of refreshing commands in burst refreshing, and protective refreshing is performed on Victim Row addresses Victim_addr adjacent to the hammering Row addresses hammer_addr, so that the Row Hammer problem can be effectively protected more pertinently, and the effect of the protective refreshing is improved.

Meanwhile, because the times of setting the high level of any two refresh Flag signals burst_flag are different (respectively corresponding to different refresh commands in the Burst refresh mode), the output times of any two hammering row addresses hammer_addr are also different, so that n hammering row addresses hammer_addr can be sequentially output, and further, the operation of timely executing the operation on the Victim row addresses victim_addr adjacent to the hammering row addresses sequentially output by utilizing the reserved protective refresh operation during the current refresh command is ensured.

In addition, as previously described, in some embodiments, multiple memory rows (e.g., 2/4/8 rows) may be refreshed simultaneously per refresh operation, and multiple hammer row addresses (corresponding to the number of memory rows that can be refreshed by a single refresh operation) may be sent simultaneously by the address sampling module during one refresh command in one burst refresh mode, or the refresh operation may be performed simultaneously by the execution module on multiple adjacent row addresses (+ 1/-1, +2/-2, +3/-3 …) of one hammer row address output by the address sampling module.

In some embodiments of the present disclosure, referring to fig. 3, the Flag signal generation module 101 is further configured to receive an active command ACT, and in response to the active command ACT, perform a reset operation on n refresh Flag signals burst_flag; the activate command ACT characterizes the burst refresh end.

In some embodiments of the present disclosure, with continued reference to fig. 3, the address sampling module 102 is further configured to output a default row address when the n refresh Flag signals burst_flag are reset; the default row address is the one of the Hammer row addresses hammer_addr that is not output and is turned on the largest number of times. The refresh control circuit updates the hammering row address list in time according to the output condition of the hammering row addresses, n hammering row addresses selected from the hammering row address list during resetting are updated, and a default row address is selected after updating, wherein the default row address is the hammering row address which is not output currently and has the largest starting times.

In the embodiment of the disclosure, with continued reference to fig. 3, since the controller transmits a continuous refresh command REF to the memory during which no activate command is issued in the burst refresh mode, the memory can be considered to exit the burst refresh mode, i.e., characterize the end of the burst refresh, when the memory receives the activate command ACT after receiving the continuous refresh command. Further, the Flag signal generation module 101 performs a reset operation on n refresh Flag signals burst_flag in response to the active command ACT; the address sampling module 102 may output one of the Hammer row addresses hammer_addr that is not output and has the largest number of turned-on times as the default row address when the n refresh Flag signals burst_flag are reset.

In some embodiments, the outputted hammering row address is deleted in the hammering row address list. When the n refresh Flag signals burst_flag are reset, the address sampling module 102 updates the n hammering row addresses, and reselects n row addresses with the largest number of turned-on times, which are not output, as new n hammering row addresses. The outputted row address is typically not selected again by the address sampling module 102.

It can be understood that, after Burst refresh is finished, the Flag signal generating module 101 does not continue to output valid n refresh Flag signals burst_flag; furthermore, the address sampling module 102 may not continue to output n hammering row addresses hammer_addr, but may output 1 hammering row address with the largest number of turned-on times as a default row address, so as to continue to perform protective refresh on an adjacent victim row of the default row address; in other embodiments, an address may be selected from other address tables to be output as a default row address for output. In this way, even if no burst refresh is performed, the victim Row address can be subjected to protective refresh, so that the protective refresh can be performed in different conditions, and the Row Hammer problem can be effectively prevented.

In some embodiments of the present disclosure, referring to fig. 3, the Flag signal generating module 101 is further configured to set the i-th refresh Flag signal burst_flag to a first level value and the remaining n-1 refresh Flag signals burst_flag to a second level value when the number of consecutively received refresh commands REF reaches the i-th preset value; i is 1 or more and n or less. The address sampling module 102 is further configured to output an ith Hammer row address hammer_addr when only an ith of the n received refresh Flag signals burst_flag is a first level value.

In the embodiment of the disclosure, referring to fig. 3 and 4, in the case of n=8, if the number of refresh commands REF continuously received by the Flag signal generating module 101 reaches 1 (i.e. 1 st preset value), the 1 st refresh Flag signal Burst1_flag is set to a high level (i.e. a first level value), and the remaining refresh Flag signals (Burst 2_flag to Burst 8_flag) are set to a low level (i.e. a second level value); if the number of refresh commands REF continuously received by the Flag signal generating module 101 reaches 2 (i.e., the 2 nd preset value), the 2 nd refresh Flag signal Burst2_flag is set to a high level (i.e., the first level value), and the remaining refresh Flag signals (Burst 1_flag, and Burst3_flag to Burst 8_flag) are set to a low level (i.e., the second level value); by analogy, if the number of refresh commands REF continuously received by the Flag signal generating module 101 reaches 8 (i.e., the n-th preset value), the 8 th refresh Flag signal Burst8_flag is set to a high level (i.e., the first level value), and the remaining refresh Flag signals Burst1_flag to Burst7_flag are set to a low level (i.e., the second level value).

It can be understood that different count values of the refresh command REF correspond to different refresh Flag signals burst_flag respectively, so that the times when any two refresh Flag signals burst_flag are set to high level are different, thereby ensuring that n hammering row addresses hammer_addr can be sequentially output, and ensuring that protective refresh operations performed on the victim row address can be sequentially performed.

In some embodiments of the present disclosure, with continued reference to fig. 3, the Flag signal generation module 101 is further configured to set each of the n refresh Flag signals burst_flag to a second level value in performing a reset operation.

In the embodiment of the present disclosure, referring to fig. 3 and 4, the Flag signal generation module 101 may set the refresh Flag signals Burst1_flag to Burst8_flag to a low level (i.e., a second level value) when the active command ACT is received to perform the reset operation. In this way, the address sampling module 102 can not continue to output n hammering Row addresses hammer_addr, and the refresh control circuit changes to perform protective refresh in other ways (only 1 hammering Row address output with the maximum number of times of being turned on can be output, and address output can also be selected from other address tables to be output), so that the Row Hammer problem is more effectively protected.

In some embodiments of the present disclosure, as shown in fig. 5, the flag signal generation module 101 includes: a counting module 201 and an encoding module 202. The counting module 201 is configured to receive the refresh command REF, count the refresh command REF to generate a count value ref_cnt. The encoding module 202 is connected to the counting module 201, and is configured to encode the count value ref_cnt, and generate and output n refresh Flag signals burst_flag.

In the disclosed embodiment, referring to fig. 5, the count value ref_cnt characterizes the number of consecutively received refresh commands REF, that is, each time one refresh command REF is received, the count value ref_cnt changes accordingly. Further, n refresh Flag signals burst_flag encoded by the count value ref_cnt have a correspondence relationship with the number of refresh commands REF. In this way, n hammering row addresses are ensured to be sequentially output, and protective refresh operations performed on the victim row address are ensured to be sequentially performed.

In some embodiments of the present disclosure, referring to fig. 6, the counting module 201 includes: m cascaded D flip-flops 203; wherein 2 is ^m Greater than or equal to n. The clock input CLK of the stage 1D flip-flop 203 receives the refresh command REF. The inverting output terminal QB of each stage D flip-flop 203 is connected to the data input terminal D thereof, and the inverting output terminal QB of each stage D flip-flop 203 is also connected to the clock input terminal CLK of the next stage D flip-flop 203. The reset terminal RST of each stage D flip-flop 203 receives the activation command ACT.

It should be noted that, the number m of D flip-flops 203 may be determined according to the number n of refresh flag signals to be generated, i.e., 2, in order to satisfy the number of continuous refresh commands in burst refresh mode ^m Greater than or equal to n, for example, if n=5, then m needs to be greater than or equal to 3.

The number of D flip-flops 203 illustrated in fig. 7 is 4, that is, m=4. Referring to fig. 7, the clock input CLK of the 1 st stage D flip-flop 203 receives the refresh command REF. The inverting output terminal QB of each stage D flip-flop 203 is connected to its data input terminal D, and the inverting output terminal QB of each stage D flip-flop is also connected to the clock input terminal CLK of the next stage D flip-flop. The in-phase output terminal Q of each stage D flip-flop outputs corresponding count values ref_cnt0 to ref_cnt3, and the inverting output terminal QB of each stage D flip-flop outputs corresponding complementary count values ref_cntb0 to ref_cntb3, wherein the count values ref_cnt0 and ref_cntb0 are mutually inverted, and the other count values and the corresponding complementary count values are mutually inverted.

In the disclosed embodiment, with continued reference to fig. 7, the reset terminal RST of each stage D flip-flop 203 receives an activate command ACT. The active command ACT may control each stage D flip-flop 203 to reset the count value and the complementary count value output thereof, thereby resetting the n-stage refresh flag signal.

In some embodiments of the present disclosure, referring to fig. 8, the encoding module 202 includes: n and gates 204. Referring to fig. 6 and 8, m input terminals of each and gate 204 are respectively connected to the in-phase output terminal Q or the opposite-phase output terminal QB of the m D flip-flops 203, and neither of any two and gates has exactly the same input, and both input terminals of each and gate 204 are not connected to the same stage D flip-flop 203. The outputs of the n and gates 204 output n refresh Flag signals (i.e., burst1_flag to burst_flag) in one-to-one correspondence.

Fig. 9 shows 5 and gates 204, i.e., n=5. Meanwhile, the and gates 204 shown in fig. 9 correspond to the D flip-flops 203 shown in fig. 7, and the number of outputs of each and gate 204 is equal to the number m of the D flip-flops 203, that is, in the case where m=4, each and gate 204 has 4 inputs, respectively.

Taking m=4 and n=5 as an example in conjunction with fig. 7 and 9, the 4 input terminals of each and gate 204 are respectively connected to the non-inverting output terminal Q or the inverting output terminal QB of the 4-stage D flip-flop 203, and neither and gate 204 has exactly the same input, and at the same time, the two input terminals of each and gate 204 are not connected to the same-stage D flip-flop 203. The outputs of the 5 and gates 204 output 5 refresh Flag signals (i.e., burst1_flag to Burst 5_flag) in one-to-one correspondence.

Taking fig. 7 and 9 as an example, the 4 input terminals of the 1 st and gate 204 are connected to the non-inverting input terminal Q of the 1 st stage D flip-flop 203, the inverting input terminal QB of the 2 nd stage D flip-flop 203, the inverting input terminal QB of the 3 rd stage D flip-flop 203, and the inverting input terminal QB of the 4 th stage D flip-flop 203, respectively; the 1 st AND gate 204 receives the signals REF_CNT0, REF_CNTb1, REF_CNTb2, and REF_CNTb3.

The 4 inputs of the 2 nd and gate 204 are connected to the inverting input QB of the 1 st stage D flip-flop 203, the non-inverting input Q of the 2 nd stage D flip-flop 203, the inverting input QB of the 3 rd stage D flip-flop 203, and the inverting input QB of the 4 th stage D flip-flop 203, respectively; and

gate

204, 2 nd, receives signals ref_cntb0, ref_cnt1, ref_cntb2, and ref_cntb3.

The 4 inputs of the 3 rd AND gate 204 are connected to the non-inverting input terminal Q of the 1 st stage D flip-flop 203, the non-inverting input terminal Q of the 2 nd stage D flip-flop 203, the inverting input terminal QB of the 3 rd stage D flip-flop 203, and the inverting input terminal QB of the 4 th stage D flip-flop 203, respectively; the 3 rd AND gate 204 receives the signals REF_CNT0, REF_CNTb2, REF_CNTb3.

The 4 input terminals of the 4 th and gate 204 are connected to the inverting input terminal QB of the 1 st stage D flip-flop 203, the inverting input terminal QB of the 2 nd stage D flip-flop 203, the non-inverting input terminal Q of the 3 rd stage D flip-flop 203, and the inverting input terminal QB of the 4 th stage D flip-flop 203, respectively; the 4 th AND gate 204 receives the signals REF_CNTb0, REF_CNTb1, REF_CNT2, and REF_CNTb3.

The 4 inputs of the 5 th AND gate 204 are respectively connected to the non-inverting input terminal Q of the 1 st stage D flip-flop 203, the inverting input terminal QB of the 2 nd stage D flip-flop 203, the non-inverting input terminal Q of the 3 rd stage D flip-flop 203 and the inverting input terminal QB of the 4 th stage D flip-flop 203; the 5 th AND gate 204 receives the signals REF_CNT0, REF_CNTb1, REF_CNT2, and REF_CNTb3.

Note that fig. 10 is a schematic diagram of signals corresponding to fig. 7 and 9, and fig. 10 shows waveforms of partial signals in fig. 7 and 9. In addition, fig. 10 shows waveforms of count values ref_cnt0 to ref_cnt3 in fig. 7, and does not show waveforms of complementary count values ref_cntb0 to ref_cntb3 in fig. 7; the waveforms of the complementary count values ref_cntb0 to ref_cntb3 and the waveforms of the corresponding count values ref_cnt0 to ref_cnt3 are mutually inverted, and can be understood with reference to the waveforms of the count values ref_cnt0 to ref_cnt 3.

Referring to fig. 7, 9 and 10, in burst refresh (burst refresh) mode, the controller does not transmit the active command ACT (i.e., the active command ACT remains low), but continuously transmits 8 refresh commands REF. Further, in the Burst refresh mode, when the number of received refresh commands REF is 1, the count value ref_cnt0 is set to a high level and the count values ref_cnt1 to ref_cnt3 are set to a low level under the triggering of the 1 st refresh command REF, so that only the refresh Flag signal Burst1_flag output from the 1 st and gate 204 is set to a high level, and the other and gates 204 output low levels. When the number of the received refresh commands REF is 2, the count value ref_cnt0 is set to a low level, the count value ref_cnt1 is set to a high level, and the count values ref_cnt2 and ref_cnt3 are still set to a low level under the triggering of the 2 nd refresh command REF, so that only the refresh Flag signal Burst2_flag output by the 2 nd and gate 204 is set to a high level, and the other and gates 204 output low levels.

In the burst refresh mode, when the number of the received refresh commands REF changes from 1 to 5, the outputs of the 1 st and 5 th and gates 204 are sequentially triggered to generate high-level pulse signals, and when any and gate 204 outputs high level, the other and gates 204 output low level. In this way, n hammering row addresses are guaranteed to be sequentially output, and protective refreshing operation performed on the victim row address is guaranteed to be sequentially and timely performed.

With continued reference to fig. 7, 9 and 10, after the Burst refresh mode is completed, the controller transmits an active command ACT (i.e., the active command ACT generates a pulse), so that the count values (ref_cnt 0 to ref_cnt 3) output from the 4-stage D flip-flop 203 are all reset to a low level, and further, the refresh Flag signals (Burst 1_flag to Burst 5_flag) output from the 5 and gates 204 are all maintained to a low level. In this case, the row address that is turned on the most number of times among the row addresses that are not outputted may be outputted as the default hammer row address, so that the protective refresh is continued.

In some embodiments of the present disclosure, as shown in fig. 11, the refresh control circuit further includes: the command decoding module 104. The command decoding module 104 is connected to the flag signal generating module 101. The command decoding module 104 is configured to decode the refresh command REF and the activate command ACT, and transmit the refresh command REF and the activate command ACT to the flag signal generation module 101.

In some embodiments of the present disclosure, as shown in fig. 12, the address sampling module 102 includes: an address selection unit 301, an address comparison unit 302, and an address output unit 303. The address selecting unit 301 is configured to select n hammer row addresses (addr_ A, addr _ B, addr _ C, addr _d and addr_e, for example, n=5) having the largest number of times of being turned on from the hammer row address list. The address comparing unit 302 is connected to the address selecting unit 301, and is configured to obtain n hammering row addresses, compare the turned-on times of the n hammering row addresses, and sort the n hammering row addresses according to the turned-on times. An address output unit 303, connected to the address comparing unit 302, configured to receive the n refresh Flag signals burst_flag and the n hammer row addresses after sorting, and in response to the n refresh Flag signals burst_flag, sequentially select all or part of the n hammer row addresses after sorting and output from the output terminal thereof.

Note that, in fig. 12, n=5 is taken as an example, and 5 hammering row addresses are shown, n in the embodiment of the present disclosure may be set to other values, which is not limited herein.

In the embodiment of the present disclosure, referring to fig. 12, the address selecting unit 301 selects 5 hammer row addresses addr_ A, addr _ B, addr _ C, addr _d and addr_e, which are turned on the largest number of times, from the hammer row address list. The row address list records the row address (i.e. the hammering row address) whose number of times is turned on reaches a certain threshold value and the corresponding number of times of being turned on before the burst refresh.

With continued reference to fig. 12, the hammer row addresses addr_ A, addr _ B, addr _ C, addr _d and addr_e are not ordered when selected. The address comparing unit 302 may compare the turned-on times of the hammer row addresses addr_ A, addr _ B, addr _ C, addr _d and addr_e and sort them by the turned-on times.

In some embodiments of the present disclosure, referring to fig. 12, the address selecting unit 301 is further configured to, when the n refresh Flag signals burst_flag are reset, re-select the n hammer row addresses (addr_a to addr_e) that are turned on the most times in response to the activation command.

In some embodiments of the present disclosure, referring to fig. 12, the address selecting unit 301 is further configured to delete the Hammer row address hammer_addr output by the address output unit 303 from the Hammer row address list.

In the embodiment of the present disclosure, the address selecting unit 301 may delete the already output hammering row address from the hammering row address list, and further, when the refresh Flag signal burst_flag is reset, in response to the activation command, reselect n hammering row addresses with the largest number of times of being turned on, so as to continue to perform the protective refresh on the adjacent victim row addresses of other hammering row addresses that are not output. Thus, the repeated protective refreshing of the same row address is avoided; therefore, on one hand, the real-time performance and the coverage range of the protective refreshing are enlarged, and the effect of the protective refreshing is improved; on the other hand, the problem that the Row Hammer caused by other hammering rows cannot be solved because the repeated protective refreshing of the addresses of a plurality of hammering rows is avoided, and the effect of Row Hammer protection on the whole memory bank cannot be achieved by the protective refreshing.

In some embodiments of the present disclosure, the number of times the 1 st to nth hammer row addresses are turned on decreases in order. That is, referring to fig. 12, the address comparing unit 302 may sort the hammer row addresses addr_ A, addr _ B, addr _ C, addr _d and addr_e from more to less according to the number of times of being turned on, resulting in sorted hammer row addresses addr_1, addr_2, addr_3, addr_4, and addr_5, where addr_1 is one of the 5 hammer row addresses that is most turned on, addr_2 is one of the 5 hammer row addresses that is turned on more than one time, and so on.

In other embodiments of the present disclosure, the address comparing unit 302 may also sort the hammering row addresses addr_ A, addr _ B, addr _ C, addr _d and addr_e according to other sorting rules, for example, sorting from less to more times being turned on, which is not limited herein.

In the embodiment of the present disclosure, with continued reference to fig. 12, the address output unit 303 may sequentially output the ordered hammering row addresses in response to the refresh Flag signal burst_flag. The number of the refresh Flag signals burst_flag is the same as the number of the hammer row addresses selected and ordered, so that the address output unit 303 may output a corresponding hammer row address each time one refresh Flag signal burst_flag is received. For example, when the address output unit 303 receives the 1 st refresh Flag signal burst_flag, it correspondingly outputs the hammer row address addr_1; the address output unit 303 receives the 2 nd refresh Flag signal burst_flag, and correspondingly outputs the hammering row address addr_2; and so on until all the hammer row addresses are output.

It can be understood that n hammering row addresses with the largest number of times of being turned on are selected from the hammering row address list, and the n hammering row addresses are ordered according to the number of times of being turned on, so that the n hammering row addresses are sequentially output. On the one hand, the Row Hammer problem can be more pertinently protected, and the protective refreshing effect is improved; on the other hand, the protective refreshing operation performed on the victim row address is ensured to be performed sequentially and timely.

In some embodiments of the present disclosure, referring to fig. 13, the address output unit 303 includes: n concatenated data selectors 304. The first input (i.e., 0 input) of each stage of data selector 304 is connected to the output of the next stage of data selector 304, and the first input (i.e., 0 input) of the last stage of data selector 304 receives the 1 st hammer row address addr_1. The output end of the data selector of the 1 st stage is used as the output end of the address output unit, and the hammering row address Hammer_addr is output. The second input (i.e., 1 input) of the ith data selector 304 receives the ith hammer row address, and the control of the ith data selector 304 receives the ith refresh flag signal, where i is greater than or equal to 1 and less than or equal to n.

Fig. 14 illustrates a 5-stage data selector 304, taking n=5 as an example. As shown in fig. 14, the second input terminal (i.e., 1 input terminal) of the data 1 selector 304 receives the 1 st hammer row address addr_1, and the control terminal of the data 1 selector 304 receives the 1 st refresh Flag signal Burst1 Flag; a second input terminal (i.e., 1 input terminal) of the data-2 selector 304 receives the 2 nd hammer row address addr_2, and a control terminal of the data-2 selector 304 receives the 2 nd refresh Flag signal Burst2 Flag; similarly, the second input (i.e., 1 input) of the 5 th data selector 304 receives the 5 th hammer row address addr_5, and the control of the 5 th data selector 304 receives the 5 th refresh Flag signal Burst5 Flag.

In the embodiment of the disclosure, referring to fig. 10 and 14, when the refresh Flag signal Burst1_flag is at a high level and the other refresh Flag signals are all at a low level, the 1 st stage data selector 304 outputs the hammering row address addr_1 received by the second input terminal (i.e., the 1 input terminal) thereof as the hammering row address hammer_addr. When the refresh Flag signal Burst2_flag is at a high level and the other refresh Flag signals are all at a low level, the 2 nd data selector 304 transmits the hammering row address addr_2 received at the second input end (i.e., 1 input end) thereof to the first input end (i.e., 0 input end) of the 1 st data selector 304, and the 1 st data selector 304 further outputs the hammering row address addr_2 received at the first input end (i.e., 0 input end) thereof as the hammering row address hammer_addr. Similarly, when the refresh Flag signal Burst5_flag is high and the other refresh Flag signals are low, the hammering row address addr_5 received by the second input terminal (i.e., the 1 input terminal) of the 5 th stage data selector 304 is outputted as the hammering row address hammer_addr after passing through the respective stages of data selectors 304. That is, different refresh Flag signals Burst1_flag to Burst5_flag are sequentially set to high level (trigger one high level pulse), and different hammering row addresses addr_1 to addr_5 are respectively output correspondingly, thereby ensuring that the hammering row addresses addr_1 to addr_5 can be sequentially output and ensuring that the protective refresh operation performed on the victim row address can be sequentially performed.

In the embodiment of the disclosure, with continued reference to fig. 10 and 14, when the refresh Flag signals Burst1_flag to Burst5_flag are all at a low level, the hammering row address addr_1 received by the first input terminal (i.e., the 0 input terminal) of the data selector 304 at stage 5 is output as the hammering row address hammer_addr after passing through the data selector 304 at each stage. That is, when the refresh Flag signals Burst1_flag to Burst5_flag are all reset to the low level, the hammer row address addr_1 is output as the default row address. The refresh control circuit updates the hammering row address list in time according to the output condition of the hammering row addresses, n hammering row addresses selected from the hammering row address list during resetting are updated, and a default row address is selected after updating, wherein the default row address is the hammering row address which is not output currently and has the largest starting times. The row address addr_1 is obtained after sorting, that is, the row address addr_1 may be one of the n row addresses that is turned on most frequently. Therefore, even if no burst refresh is performed, the victim Row address can be subjected to protective refresh, so that the protective refresh can be performed in different conditions, and the Row Hammer problem can be effectively prevented.

In some embodiments of the present disclosure, referring to fig. 3 or 11, the execution module 103 is further configured to perform a refresh operation on an adjacent victim row address of the Hammer row address Hammer Addr during a current refresh command or during a next refresh command.

In the embodiment of the disclosure, referring to fig. 3 or 11, the execution module 103 may perform +1 or-1 on the basis of the Hammer row address hammer_addr to obtain a victim row address adjacent to the Hammer row address hammer_addr, and further perform a protective refresh on the victim row address by using 2 refresh operations reserved during the current refresh command; in other embodiments, a protective refresh may also be performed on the victim row address with 2 refresh operations reserved during the next refresh command; it should be noted that, the protection refresh is performed by taking 2 refresh operations reserved during each refresh command as an example, and in other embodiments, the number of operations reserved for the protection refresh by each refresh command device may be other values.

The disclosed embodiments also provide a memory, as shown in fig. 15, where the memory 90 includes a refresh control circuit 80. The refresh control circuit 80 includes the structure of any of the above embodiments.

In some embodiments of the present disclosure, referring to fig. 15, memory 90 is a DRAM. The DRAM may be any one of DDR4 (4 th generation double rate synchronous dynamic random access memory), DDR5 (5 th generation double rate synchronous dynamic random access memory), LPDDR4 (4 th generation low power consumption double rate synchronous dynamic random access memory), and LPDDR5 (5 th generation low power consumption double rate synchronous dynamic random access memory).

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A refresh control circuit, the refresh control circuit comprising:

the mark signal generation module is configured to receive a refresh command and generate n refresh mark signals according to the refresh command which is continuously received, wherein n is a positive integer;

the address sampling module is connected with the mark signal generating module and is configured to receive n refresh mark signals and sequentially select and output all or part of n hammering row addresses with the largest turn-on times in response to the n refresh mark signals;

and the execution module is connected with the address sampling module and is configured to sequentially receive n hammering row addresses and sequentially execute refreshing operation on adjacent victim row addresses of the n hammering row addresses.

2. The refresh control circuit of claim 1, wherein the refresh control circuit comprises a refresh circuit,

The flag signal generation module is further configured to receive an activation command, and in response to the activation command, perform a reset operation on the n refresh flag signals.

3. The refresh control circuit of claim 2, wherein the refresh control circuit comprises a refresh circuit,

the address sampling module is further configured to output a default row address when n refresh flag signals are reset; the default row address is the one of the hammer row addresses that is not output and has the largest number of times of being turned on.

4. The refresh control circuit of claim 2, wherein the refresh control circuit comprises a refresh circuit,

the mark signal generating module is further configured to set an ith refresh mark signal to a first level value and set the rest n-1 refresh mark signals to a second level value when the number of the refresh commands continuously received reaches the ith preset value; i is 1 or more and n or less;

the address sampling module is further configured to output an ith hammering row address when only the ith i value is a first level value in the received n refresh flag signals.

5. The refresh control circuit of claim 2, wherein the refresh control circuit comprises a refresh circuit,

the flag signal generation module is further configured to set each of the n refresh flag signals to a second level value in performing the reset operation.

6. The refresh control circuit of claim 4, wherein the flag signal generation module comprises: a counting module and a coding module;

the counting module is configured to receive the refresh command, count the refresh command and generate a count value;

the encoding module is connected with the counting module and is configured to encode the count value, and generate and output n refreshing mark signals.

7. The refresh control circuit of claim 6, wherein the counting module comprises: m cascaded D flip-flops; wherein 2 is ^m Greater than or equal to n;

the clock input end of the D trigger of the 1 st level receives a refresh command;

the inverting output end of the D trigger of each stage is connected with the data input end of the D trigger; the inverting output end of the D trigger of each stage is also connected with the clock input end of the D trigger of the next stage;

and the reset end of the D trigger of each stage receives the activation command.

8. The refresh control circuit of claim 7, wherein the encoding module comprises: n AND gates;

the m input ends of each AND gate are respectively connected with the in-phase output ends or the anti-phase output ends of the m D flip-flops; any two AND gates do not have identical inputs; and the output ends of the n AND gates output n refresh flag signals in one-to-one correspondence.

9. The refresh control circuit of claim 2, wherein the refresh control circuit further comprises: a command decoding module;

the command decoding module is connected with the sign signal generating module and is configured to decode a refresh command and an activation command and transmit the refresh command and the activation command to the sign signal generating module.

10. The refresh control circuit of claim 2, wherein the address sampling module comprises:

an address selecting unit configured to select n hammering row addresses with the largest number of times of being turned on from a hammering row address list;

the address comparison unit is connected with the address selection unit and is configured to acquire n hammering row addresses, compare the opened times of the n hammering row addresses and sort the n hammering row addresses according to the opened times;

and the address output unit is connected with the address comparison unit and is configured to receive the n refresh flag signals and the n hammering row addresses after sequencing, and respond to the n refresh flag signals to sequentially select all or part of the n hammering row addresses after sequencing and output the n hammering row addresses from the output end of the n hammering row addresses after sequencing.

11. The refresh control circuit of claim 10, wherein the refresh control circuit is configured to control the refresh rate of the memory device,

the address selecting unit is further configured to, when the n refresh flag signals are reset, re-select the n hammer row addresses that are turned on the largest number of times in response to the activation command.

12. The refresh control circuit of claim 10, wherein the refresh control circuit is configured to control the refresh rate of the memory device,

the address selecting unit is further configured to delete the hammering row address output by the address output unit from the hammering row address list.

13. The refresh control circuit of claim 10, wherein the address output unit comprises: n cascaded data selectors;

the first input end of each stage of the data selector is connected with the output end of the next stage of the data selector, the first input end of the last stage of the data selector receives the 1 st hammering row address, and the output end of the 1 st stage of the data selector is used as the output end of the address output unit;

the second input end of the data selector of the ith stage receives the ith hammering row address, and the control end of the data selector of the ith stage receives the ith refresh flag signal, wherein i is greater than or equal to 1 and less than or equal to n.

14. The refresh control circuit according to any one of claims 1 to 13, wherein the number of times the hammer row address is turned on decreases in order from 1 st to nth.

15. The refresh control circuit of claim 1, wherein the refresh control circuit comprises a refresh circuit,

the execution module is further configured to perform a refresh operation on an adjacent victim row address of the hammered row address during a current refresh command or during a next refresh command.

16. A memory comprising a refresh control circuit as recited in any one of claims 1 to 15.

17. The memory of claim 16, wherein the memory is a DRAM.