CN116030853A

CN116030853A - Column control circuit and memory device

Info

Publication number: CN116030853A
Application number: CN202310311823.5A
Authority: CN
Inventors: 王子健
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-04-28
Anticipated expiration: 2043-03-28
Also published as: CN116030853B

Abstract

The embodiment of the disclosure provides a column control circuit and a storage device. The column control circuit includes a delay control circuit and a control signal generation circuit. The delay control circuit receives the column selection start signal and performs delay processing to output a column selection end signal and a reset signal. The control signal generating circuit receives a column selection start signal, a reset signal, a column selection end signal, and a target bank group selection signal, and outputs a target column selection start signal, a target column selection end signal, and a target column selection window signal. The method comprises the steps of starting a target column selection starting signal to be in an effective state, and enabling the target column selection window signal to be in an effective state from the starting moment when the target column selection starting signal is in the effective state until a reset signal is effective, wherein the effective time length of the target column selection window signal is longer than or equal to the effective time length of a target memory bank group selection signal.

Description

Column control circuit and memory device

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a column control circuit and a storage device.

Background

Semiconductor memories are used in many electronic systems to store data that can be retrieved at a later time. Semiconductor memories are typically controlled by providing commands, addresses, and clocks to the semiconductor memory. The semiconductor memory may perform various memory operations in response to commands. For example, a read command causes the semiconductor memory to perform a read operation to retrieve data from the semiconductor memory, and a write command causes the semiconductor memory to perform a write operation to store data to the semiconductor memory. The address identifies the semiconductor memory location for the access operation, and the clock provides the timing of the various operations and data provision.

In order to improve the throughput of internal data, more data can be conveniently read at the same time, the semiconductor memory can be divided into a plurality of memory Bank groups (BG, bank groups), and each memory Bank Group can independently read and write data.

Disclosure of Invention

The embodiment of the disclosure provides a column control circuit and a memory device, which is at least beneficial to providing a column control circuit applicable to a plurality of memory bank groups, and ensures that a column selection termination signal can be always sampled by a target column selection window signal to obtain the target column selection termination signal.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a column control circuit, including: a delay control circuit configured to receive a column selection start signal, perform delay processing on the column selection start signal, and generate and output a column selection end signal and a reset signal; wherein the column selection termination signal has a first delay amount with respect to the column selection start signal, and the reset signal has a second delay amount with respect to the column selection start signal, the second delay amount being greater than the first delay amount; a control signal generating circuit connected to the delay control circuit and configured to receive the column selection start signal, the reset signal, the column selection end signal, and a target bank group selection signal, perform a first and operation on the column selection start signal and the target bank group selection signal to generate and output a target column selection start signal, generate and output a target column selection window signal based on the target column selection start signal, the target bank group selection signal, and the reset signal, and perform a second and operation on the target column selection window signal and the column selection end signal to generate and output a target column selection end signal; the target column selection window signals are in an effective state from the starting time when the target column selection starting signals are in an effective state until the reset signals are effective, and the effective time length of the target column selection window signals is greater than or equal to the effective time length of the target memory bank group selection signals.

In some embodiments, the control signal generation circuit includes: a plurality of target signal generating circuits, each corresponding to a bank group, each corresponding to a target bank group selection signal; each of the target signal generating circuits corresponding to each of the bank groups is configured to receive the column selection start signal, the reset signal, the column selection end signal, and the target bank group selection signal corresponding to the bank group, and output the target column selection start signal, the target column selection window signal, and the target column selection end signal corresponding to the bank group.

In some embodiments, the target signal generation circuit includes: a start signal generating circuit configured to receive the column selection start signal and the target bank group selection signal and perform the first and operation, generate and output the target column selection start signal; a reset signal generating circuit configured to receive the reset signal and the target bank group selection signal and perform a logic operation to generate and output a target reset signal; a window signal generating circuit configured to output the target column selection window signal based on the target reset signal, the target bank group selection signal, and the target column selection start signal, wherein the target column selection window signal is in an active state during which the target column selection window signal is in an inactive state from when the target column selection start signal is active until when the target reset signal is active; and a termination signal generating circuit configured to receive the target column selection window signal and the column selection termination signal and perform the second AND operation, and generate and output the target column selection termination signal.

In some embodiments, the start signal generation circuit includes: a first NAND gate, two input terminals respectively receiving the target bank group selection signal and the column selection start signal; and the input end of the first inverter is connected with the output end of the first NAND gate, and the output end of the first inverter outputs the target column selection starting signal.

In some embodiments, the reset signal generation circuit includes: the second inverter, the input end receives the said goal memory bank group selection signal, the output end outputs the inverted signal of the said goal memory bank group selection signal; and one input end of the first AND gate is connected with the output end of the second inverter, one input end of the first AND gate receives the reset signal, and the output end of the first AND gate outputs the target reset signal.

In some embodiments, the window signal generation circuit includes: the data input end of the first D trigger receives the target memory bank group selection signal, the clock end of the first D trigger receives the target column selection starting signal or the column selection starting signal, the reset end of the first D trigger receives the target reset signal, and the non-inverting output end of the first D trigger outputs the target column selection window signal.

In some embodiments, the first D flip-flop also has an inverted clock trigger that receives the target column select start signal or an inverted signal of the column select start signal.

In some embodiments, the termination signal generation circuit includes: a second NAND gate, one input end of which receives the target column selection window signal and the other input end of which receives the column selection termination signal; and the input end of the third inverter is connected with the output end of the second NAND gate, and the output end outputs the target column selection termination signal.

In some embodiments, the second delay amount and the first delay amount satisfy: and 2T is less than or equal to T2-T1, wherein T2 is the second delay amount, T1 is the first delay amount, 2T is the effective duration of the column selection start signal, and T is 1 clock cycle.

In some embodiments, the delay control circuit is further configured to receive a delay selection signal and adjust the first delay amount and the second delay amount based on the delay selection signal.

In some embodiments, the delay select signal comprises a first delay select signal and a second delay select signal; the delay control circuit includes: a delay circuit having an input node and N output nodes configured to receive the column selection start signal via the input node and output N delay signals via the N output nodes, wherein the N output nodes include 1 st to N th output nodes arranged in a natural number increasing order, and delay amounts of the N delay signals output from the 1 st to N th output nodes with respect to the column selection start signal sequentially increase, N being a natural number of 2 or more; a first gating circuit connected to the m output nodes, having a first output terminal configured to gate a transmission path between one of the m output nodes and the first output terminal in response to the first delay selection signal to output the column selection termination signal via the first output terminal, m being a natural number of N or less; and a second gate circuit connected to the N output nodes and having a second output terminal configured to gate a transmission path between one of the N output nodes and the second output terminal in response to the second delay selection signal to output the reset signal via the second output terminal, N being a natural number of N or less.

In some embodiments, the delay circuit includes: the data input ends of the second D flip-flops in the first stage serve as the input nodes, and the inverting output ends of the second D flip-flops in the previous stage are connected with the data input ends of the second D flip-flops in the subsequent stage; the clock ends of the second D flip-flops at the odd positions all receive clock signals, the clock ends of the second D flip-flops at the even positions all receive inverted clock signals, and the inverted clock signals and the clock signals are mutually inverted signals; and the inverting output ends of the N second D flip-flops serve as N output nodes.

In some embodiments, the delay circuit is further configured to generate the column selection start signal in response to a read operation command and provide the column selection start signal to the input node.

In some embodiments, the delay circuit includes: the data input end of the third D flip-flop at the first stage receives the read operation command, and the inverting output end of the third D flip-flop at the previous stage is connected with the data input end of the third D flip-flop at the subsequent stage; the clock ends of the third D flip-flops at the odd positions all receive clock signals, the clock ends of the third D flip-flops at the even positions all receive inverted clock signals, and the inverted clock signals and the clock signals are mutually inverted signals; the inverting output end of the third D flip-flop of the last stage is connected with the input node and outputs the column selection starting signal.

In some embodiments, the first gating circuit includes: each first gating unit is provided with a first node, and each first gating unit is connected with two corresponding and adjacent output nodes in m output nodes; each of the first gating units is configured to gate a transmission path between one of the two output nodes and the first node in response to the first delay selection signal.

In some embodiments, the first delay selection signal includes p-bit first control codes, each of the first gating units receives the corresponding three first control codes, p is a natural number greater than or equal to 3, and the effective levels of the delay signals output by the two adjacent output nodes are opposite; the first gating unit includes: the two input ends of the third NAND gate respectively receive the inverted signals of corresponding one of the three first control codes; the input end of the fourth inverter is connected with the output node; the two input ends of the second AND gate are respectively connected with the output end of the third NAND gate and the output end of the fourth inverter; the third AND gate, one input end receives the rest of three first control codes, another input end is connected with another output node; and the input end of the fourth NAND gate is respectively connected with the output end of the second AND gate and the output end of the third AND gate, and the output end of the fourth NAND gate is used as the first node.

In some embodiments, the first gating circuit comprises at least two first gating cells, and each first gating cell is connected to a different one of the output nodes; the first gating circuit further includes: and the input end of the first OR gate is connected with each first node, and the output end of the first OR gate is connected with the first output end.

In some embodiments, the second gating circuit includes: at least one second gating unit, each second gating unit has a second node and is connected with two corresponding and adjacent output nodes in the n output nodes; each of the second gating units is configured to gate a transmission path between one of the two output nodes and the second node in response to the second delay selection signal.

In some embodiments, the second delay selection signal includes q-bit second control codes, each of the second gating units receives the corresponding three second control codes, q is a natural number greater than or equal to 3, and the effective levels of the delay signals output by the two adjacent output nodes are opposite; the second gating unit includes: a fifth NAND gate, wherein two input ends respectively receive the inverted signals of corresponding one of the three second control codes; the input end of the fifth inverter is connected with the output node; the two input ends of the fourth AND gate are respectively connected with the output end of the fifth NAND gate and the output end of the fifth inverter; a fifth AND gate, one input end of which receives the rest of the three second control codes, and the other input end of which is connected with the other output node; and the input end of the sixth NAND gate is respectively connected with the output end of the fourth AND gate and the output end of the fifth AND gate, and the output end of the sixth NAND gate is used as the second node.

In some embodiments, the second gating circuit comprises at least two second gating cells, and each second gating cell is connected to a different one of the output nodes; the second gating circuit further includes: and the input end of the second OR gate is connected with each second node, and the output end of the second OR gate is connected with the second output end.

According to other embodiments of the present disclosure, there is also provided, in another aspect, a storage device including: the memory bank comprises a plurality of memory bank groups, wherein each memory bank group comprises a plurality of memory cell arrays, each memory cell array comprises a plurality of memory cells, and each memory cell array is connected with a plurality of column selection switch tubes; the column control circuit according to any of the above embodiments, wherein the column selection switch tube is turned on in response to the corresponding target column selection start signal and turned off in response to the target column selection end signal.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the technical scheme of the column control circuit provided by the embodiment of the disclosure, the reset signal has a second delay amount compared with the column selection start signal, and the column selection end signal has a first delay amount compared with the column selection start signal, and the second delay amount is greater than or equal to the first delay amount. A first AND operation is performed on the column selection start signal and the target bank group selection signal to generate and output a target column selection start signal. A target column selection window signal is generated and output based on the target column selection start signal, the target bank group selection signal, and the reset signal. Performing a second AND operation on the target column selection window signal and the column selection termination signal to generate and output the target column selection termination signal. In this way, the valid start time of the target column selection window signal is earlier than the valid start time of the column selection end signal, so that the valid start time of the column selection end signal can be sampled by the target column selection window signal. And because the target column selection starting signal is in the starting time of the effective state until the reset signal is effective, the target column selection window signal is in the effective state, and the effective time length of the target column selection window signal is longer than or equal to the effective time length of the target memory bank group selection signal, the effective ending time of the column selection ending signal with relatively large delay amount can still be earlier than the effective ending time of the target column selection window signal, and the effective ending time of the column selection ending signal can also be sampled by the target column selection window signal. Thus, in embodiments of the present disclosure, the column selection termination signal may always be sampled by the target column selection window signal.

For example, even if the operating frequency of the memory device changes, the column selection end signal can always be sampled by the target column selection window signal. Or, the first delay amount or the second delay amount is changed, so that a time interval between the target column selection termination signal and the target column selection start signal is changed.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings do not depict a proportional limitation unless expressly stated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a functional block diagram of a column control circuit provided by an embodiment of the present disclosure;

FIG. 2 is another functional block diagram of a column control circuit provided by an embodiment of the present disclosure;

FIG. 3 is a functional block diagram of a target signal generating circuit provided by an embodiment of the present disclosure;

fig. 4 is a schematic circuit diagram of a start signal generating circuit according to an embodiment of the disclosure;

fig. 5 is a schematic circuit diagram of a reset signal generating circuit according to an embodiment of the disclosure;

fig. 6 is a schematic circuit diagram of a window signal generating circuit according to an embodiment of the disclosure;

fig. 7 is a schematic circuit diagram of a termination signal generating circuit according to an embodiment of the disclosure;

fig. 8 is a schematic circuit diagram of a control signal generating circuit according to an embodiment of the disclosure;

FIG. 9 is a timing diagram of signals in a column control circuit according to an embodiment of the present disclosure;

FIG. 10 is another timing diagram of signals in a column control circuit according to an embodiment of the present disclosure;

FIG. 11 is a timing diagram of signals in a column control circuit according to an embodiment of the present disclosure;

FIG. 12 is a timing diagram of signals in a column control circuit according to an embodiment of the present disclosure;

FIG. 13 is yet another functional block diagram of a column control circuit provided by an embodiment of the present disclosure;

FIG. 14 is a timing diagram of signals in a column control circuit according to an embodiment of the present disclosure;

FIG. 15 is another timing diagram of signals in the column control circuit according to an embodiment of the present disclosure;

FIG. 16 is a functional block diagram of a delay control circuit provided by an embodiment of the present disclosure;

fig. 17 is a schematic circuit diagram of a delay circuit according to an embodiment of the disclosure;

fig. 18 is a schematic circuit diagram of a delay circuit according to an embodiment of the disclosure;

FIG. 19 is a functional block diagram of a first gating circuit provided by an embodiment of the present disclosure;

FIG. 20 is another functional block diagram of a first gating circuit provided by an embodiment of the present disclosure;

fig. 21 is a schematic circuit diagram of any one of the first gating units according to the embodiment of the disclosure;

fig. 22 is a schematic circuit diagram of a first gating circuit according to an embodiment of the present disclosure;

FIG. 23 is a functional block diagram of a second gating circuit provided by an embodiment of the present disclosure;

FIG. 24 is another functional block diagram of a second gating circuit provided by an embodiment of the present disclosure;

fig. 25 is a schematic circuit diagram of any one of the second gating units according to the embodiment of the disclosure;

Fig. 26 is a schematic circuit diagram of a second gating circuit according to an embodiment of the present disclosure;

FIG. 27 is a schematic diagram of a memory device according to an embodiment of the disclosure;

fig. 28 is a schematic diagram of a memory cell array in the bank group BankGroupA of fig. 27.

Detailed Description

The embodiment of the disclosure provides a column control circuit which can be applied to a storage device. The column control circuit provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

The memory device may include a plurality of bank groups. When the same bank group is continuously accessed, there is a first delay time tccd_l between access commands of the same bank group, in other words, the same bank group may be accessed again at the first delay time tccd_l after the same bank group is accessed. The first delay time tccd_l may represent the minimum time interval required to access the same bank group.

When different bank groups are consecutively accessed, any bank group may be accessed again at a second delay time tccd_s after other bank groups are accessed, in other words, with a second delay time tccd_s between access commands of different bank groups. The second delay time tccd_s may be expressed as a minimum time interval required to access different bank groups. In general, the first delay time tccd_l is greater than the second delay time tccd_s.

Taking a reading operation as an example, a column selection start signal is generated based on a reading command, and a column selection window signal is generated after the reading command is circularly turned over according to the cycle number corresponding to the first delay time. The memory device will operate at different frequencies, and at each operating frequency it is desirable that the delay between the column select start signal and the column select window signal remain relatively constant without variation with operating frequency, since the first delay time is different at different operating frequencies, it is believed that the first delay time is characteristic of being able to characterize the operating frequency, and therefore has the following formula:

tCK×Shift_Cycle=CSLM-S（1）

tCK is the time of one clock Cycle corresponding to the working frequency, shift_cycle is a cyclic inversion multiple, CSLM-S is the delay between the column selection start signal and the column selection window signal, and the delay between the column selection start signal and the column selection window signal is the pulse width of CSLM-S. The pulse width of the CSLM-S is also the active duration of the column strobe signal, in other words, the pulse width of the CSLM-S is the duration that the column strobe signal is enabled. The column selection communication is connected with the column selection switch tube, and the column selection switch tube is enabled, so that the corresponding column selection switch tube is opened.

In one example, to ensure the on-time of the column select switch connected to the bit line, the time to ensure complete transfer of data on the bit line to the local data line (i.e., LIO) is sufficient, and the time of CSLM-S should be greater than or equal to 2.5ns. With the increase of the operating frequency, for the point where the minimum pulse width (pulse width: pulse width) is the limit (i.e., margin) of the second delay time tccd_s=8tck, the valid time that should be satisfied by the CSLM-S cannot be satisfied even if the pulse width of the CSLM-S is greater than 8tCK, i.e., the pulse width of the CSLM-S is less than 2.5ns, so that the column selection window signal cannot cover the corresponding bank group address information, and the valid duration of the column strobe signal of the bank group corresponding to the corresponding bank group address information cannot be ensured to satisfy the requirement.

Further, it is understood that in a specific example, the pulse width of CSLM-S is 2.5ns in order to keep the column strobe enabled. Second, to ensure that the local data line is sufficiently precharged or to ensure that the column strobe signal does not affect the precharge process, the column strobe signal needs to be deactivated before precharge begins. While the time from the start of the column select communication to the end of the precharge is fixed (5 ns is taken as an example), the precharge time of the local data line is 1.25ns as an example, and in order to achieve the precharge time of the local data line, CSLM-S may be set to a section of more than 3ns and less than 3.75ns, which would still be required if it were still achieved by the CSLM-S with a pulse width of 8tCK, 1 tCK. Gtoreq.0.375 ns. However, for high frequency memory devices operating at 6000MHz and above, 1tCK is much less than 0.375ns, i.e., the pulse width of CSLM-S is 8tCK, which is not satisfactory.

In the technical scheme of the column control circuit provided by the embodiment of the disclosure, the target column selection window signal of the corresponding memory bank group is generated by performing logic operation on the memory bank group selection signal and one column selection start signal, so that the target column selection window signal generated based on the first column selection start signal is always kept at an active level until the reset signal comes, and the target column selection window signal is not changed into an inactive state no matter whether two continuous column selection start signals access the same memory bank group or different memory bank groups. Wherein, because the delay (second delay amount) of the reset signal relative to the column selection start signal is larger than the delay (first delay amount) of the column selection end signal relative to the column selection start signal, the valid period of the target column selection window signal can be covered to the valid period of the column selection end signal, thereby ensuring that the target column selection end signal corresponding to the corresponding target memory bank group can be generated under all working frequencies.

In addition, the delay of the target column selection termination signal relative to the column selection start signal is determined by the first delay amount, and by reasonably setting the first delay amount, the effective duration of the column strobe signal can be ensured to be greater than 3ns under different working frequencies, namely, the effective duration is not influenced by the limit point of the 8 tCK.

Fig. 1 is a functional block diagram of a column control circuit provided in an embodiment of the present disclosure.

Referring to fig. 1, the column control circuit includes a delay control circuit 101 and a control signal generation circuit 102 connected to the delay control circuit 101.

The delay control circuit 101 is configured to receive the column selection start signal CSLEN0T, perform a delay process on the column selection start signal CSLEN0T, and generate and output a column selection end signal CSLDIS and a reset signal RSTB.

The column selection end signal CSLDIS has a first delay amount with respect to the column selection start signal CSLEN0T, and the reset signal RSTB has a second delay amount with respect to the column selection start signal CSLEN0T, the second delay amount being larger than the first delay amount.

In some examples, the clock period of the column selection start signal CSLEN0T is 2T, and the difference between the second delay amount and the first delay amount may be greater than or equal to 2T.

Taking the column selection start signal CSLEN0T as the active high level as an example, the difference between the second delay amount and the first delay amount is 2T, the clock falling edge of the column selection start signal CSLEN0T is aligned with the clock rising edge of the reset signal RSTB. It will be appreciated that the "alignment" referred to in the embodiments of the present disclosure is in an ideal state, in which the different signals pass through different logic circuits or different transmission paths, so that there may be some delay between the different signals that cannot be aligned completely, but if the delay between the different signals is negligible, the different signals may be considered to be aligned.

Taking the column selection start signal CSLEN0T as the active low level as an example, the difference between the second delay amount and the first delay amount is 2T, the clock rising edge of the column selection start signal CSLEN0T is aligned with the clock falling edge of the reset signal.

The control signal generating circuit 102 is configured to receive the column selection start signal CSLEN0T, the reset signal RSTB, the column selection end signal CSLDIS, and the target bank group selection signal BG, and perform a first and operation on the column selection start signal CSLEN0T and the target bank group selection signal BG to generate and output a target column selection start signal bg_cslen.

Each target bank group selection signal BG corresponds to a bank group. And if the target memory bank group selection signal BG is valid, the memory bank group corresponding to the target memory bank group selection signal BG is selected for reading or writing. The target bank group selection signal BG is not valid, and the corresponding bank group is not selected.

The control signal generating circuit 102 also generates and outputs a target column selection window signal CSLSLV based on the target column selection start signal bg_cslen, the target bank group selection signal BG, and the reset signal RSTB.

The control signal generating circuit 102 further performs a second AND operation on the target column selection window signal CSLSLV and the column selection termination signal CSLDIS to generate and output a target column selection termination signal BG_CSLDIS.

The target column selection window signal CSLSLV is in an active state from a starting time when the target column selection start signal bg_cslen is in an active state until the reset signal RSTB is active, and the active time of the target column selection window signal CSLSLV is greater than or equal to the active time of the target bank group selection signal BG.

Taking the effective duration of the target bank group selection signal BG as an example, where the effective duration is 8T, and T is one clock period corresponding to one frequency, the effective duration of the target column selection window signal CSLSLV may be greater than or equal to 8T. In this way, at all frequencies, the effective duration of the target column selection window signal CSLSLV is guaranteed to have a delay greater than or equal to 8T compared to the effective start time of the target column selection start signal bg_cslen. In this way, under all operating frequencies, before each time the column selection termination signal CSLDIS is changed from valid to invalid, the corresponding target column selection window signal CSLDIS is already kept in a valid state, so that the valid column selection termination signal CSLDIS can be sampled by the valid target column selection window signal cslsiv, in other words, the valid period of the target column selection window signal cslsiv can completely cover the valid period of the column selection termination signal CSLIDS, so that the target column selection termination signal bg_csldis with the valid period meeting the requirement can be generated, the valid period of column selection communication of the corresponding memory bank group is ensured, and the correct transmission of data in the reading operation or the writing operation is ensured.

For example, taking the period of the active period (i.e., the active period) of the column selection termination signal CSLDIS as an example of 2T, the reset signal RSTB may have a delay amount greater than or equal to 2T compared to the target column selection window signal CSLSLV. The invalid starting time of the target column selection window signal CSLSLV is determined by the valid starting time of the reset signal RSTB, so that the valid period of the target column selection window signal CSLSLV can be ensured to completely cover the valid period of the column selection termination signal CSLDIS, so that the valid period of the target column selection termination signal bg_csldis is 2T, i.e., the valid period of the target column selection termination signal bg_csldis meets the requirement.

Fig. 2 is another functional block diagram of a column control circuit provided by an embodiment of the present disclosure.

Referring to fig. 2, the control signal generating circuit 102 includes a plurality of target signal generating circuits 112. Each of the target signal generating circuits 112 corresponds to a bank group, and each of the bank groups corresponds to a target bank group selection signal.

The different target bank group select signals are identified as bg_a … bg_h. Each of the target signal generating circuits 112 receives a corresponding one of the target bank group selection signals, in other words, each of the target bank group selection signals is transmitted to the corresponding target signal generating circuit 112.

Each of the target signal generating circuits 112 corresponding to each of the bank groups is configured to receive a column selection start signal CSLEN0T, a reset signal RSTB, a column selection end signal CSDIS, and a target bank group selection signal BG corresponding to the bank group, and output a target column selection start signal, a target column selection window signal, and a target column selection end signal corresponding to the bank group.

The valid start timing of the column selection start signal CSLEN0T may have a small delay compared to the valid start timing of the target bank group selection signal, and the valid start timing of the column selection start signal CSLEN0T may be synchronized with the valid start timing of the target bank group selection signal.

The target column selection start signal, the target column selection window signal, and the target column selection end signal generated by the target signal generating circuit 112 receiving the target bank group selection signal bg_a are sequentially identified as bga_cslen, cslslv_a, and bga_csldis. The target column selection start signal, the target column selection window signal, and the target column selection end signal generated by the target signal generation circuit 112 receiving the target bank group selection signal bg_h are sequentially identified as bgh_cslen, cslslv_h, and bgh_csldis.

Fig. 3 is a functional block diagram of a target signal generating circuit according to an embodiment of the disclosure, and fig. 3 is an example of a target signal generating circuit for receiving a target bank group selection signal bg_a. Referring to fig. 3, the target signal generating circuit 112 includes a start signal generating circuit 12, a reset signal generating circuit 42, a window signal generating circuit 22, and a stop signal generating circuit 32.

The start signal generating circuit 12 is configured to receive the column selection start signal CSLEN0T and the target bank group selection signal bg_a and perform a first and operation, and generate and output a target column selection start signal bga_cslen.

Fig. 4 is a schematic circuit diagram of a start signal generating circuit according to an embodiment of the disclosure. Referring to fig. 4, the start signal generating circuit 12 may include a first nand gate ANN1 and a first inverter Inv1.

The two input terminals of the first nand gate ANN1 respectively receive the target bank group selection signal bg_a and the column selection start signal CSLEN0T. The input terminal of the first inverter Inv1 is connected to the output terminal of the first nand gate ANN1, and the output terminal outputs the target column selection start signal bga_cslen.

With continued reference to fig. 3, the reset signal generation circuit 42 is configured to receive the reset signal RSTB and the target bank group selection signal and perform a logical operation, generate and output a target reset signal. Taking the target bank group selection signal as bg_a as an example, the corresponding target reset signal is bga_rstb.

In some examples, there are two consecutive cases where the same target bank group is selected for operation, e.g., the two consecutive target bank group selection signals are bg_a. In this case, if there is a temporal overlap between the reset signal generated based on the previous target bank group selection signal bg_a and the next target bank group selection signal bg_a, it may result in that the target column selection window signal cslslv_a corresponding to the next target bank group selection signal bg_a cannot be generated.

To avoid the problem caused by the above situation, the reset signal generating circuit 42 may mask the reset signal RSTB with the target bank group selection signal bg_a to generate the target reset signal bga_rstb, so as to ensure that the target reset signal bga_rstb is always disabled during the period when any one of the target bank group selection signals bg_a is active regardless of the first delay amount, the second delay amount, and the time interval between the adjacent two target bank group selection signals bg_a. Thus, the window signal generating circuit 22 outputs the target column selection window signal cslslv_a in an active state during the period when any one of the target bank group selection signals bg_a is received.

The function of the reset signal generating circuit 42 will be described in more detail later with reference to the timing diagrams.

Fig. 5 is a schematic circuit diagram of a reset signal generating circuit. Referring to fig. 5, the reset signal generation circuit 42 may include a second inverter Inv2 AND a first AND gate AND1.

The second inverter Inv2 has an input terminal receiving the target bank group selection signal bg_a and an output terminal outputting an inverted signal of the target bank group selection signal bg_a. One input end of the first AND gate AND1 is connected to the output end of the second inverter Inv2, the other input end receives the reset signal RSTB, AND the output end outputs the target reset signal bga_rstb.

The active period of the target bank group selection signal bg_a, i.e., the period when the target bank group selection signal bg_a is 1, is the inactive state when the target reset signal bgga_rstb is 0, no matter whether the reset signal RSTB is active or not.

Referring to fig. 3, the window signal generating circuit 22 is configured to output a target column selection window signal cslslv_a based on a target reset signal bga_rstb, a target bank group selection signal bg_a, and a target column selection start signal bga_cslen.

The target column selection window signal cslslv_a is in an active state from the time when the target column selection start signal bga_cslen is active until the target reset signal bga_rstb is active, and the target column selection window signal cslslv_a is in an inactive state during the time when the target reset signal bga_rstb is active.

It will be appreciated that for the same target signal generating circuit, after the reset signal RSTB is in an active state, the target column selection window signal cslslv_a changes from active to inactive and remains inactive until the next target bank group selection signal bg_a is received, and the active target column selection window signal cslslv_a is generated again based on the next target column selection start signal bga_cslen.

It will be appreciated that, when the masking effect of the target bank group selection signal on the reset signal is considered, for the same target signal generating circuit, after the target reset signal is in an active state, the target column selection window signal cslslv_a changes from active to inactive and remains inactive until the next target bank group selection signal is received, and the active target column selection window signal is generated again based on the target column selection start signal corresponding to the next target bank group selection signal.

Note that, in some examples, if there is no time overlap between the reset signal generated based on the previous target bank group selection signal bg_a and the next target bank group selection signal bg_a, the target signal generating circuit 112 may not include the reset signal generating circuit 42, and the window signal generating circuit 22 may output the target column selection window signal cslslv_a based on the reset signal RSTB, the target bank group selection signal bg_a, and the target column selection start signal bga_cslen. In other words, according to whether or not there is a time interval between the reset signal corresponding to the previous bank group selection signal and the next bank group selection signal among the adjacent two bank group selection signals for the same target bank group, whether or not the reset signal generating circuit 42 is provided can be reasonably selected as long as it is ensured that each target bank group selection signal bg_a can generate the corresponding target column selection window signal cslslv_a.

Fig. 6 is a schematic circuit diagram of a window signal generating circuit according to an embodiment of the disclosure. Referring to fig. 6, the window signal generating circuit 22 may include a first D flip-flop F/L1.

The data input terminal D of the first D flip-flop F/L1 receives the target bank group selection signal bg_a, the clock terminal CK of the first D flip-flop F/L1 receives the target column selection start signal bga_cslen or the column selection start signal CSLEN0T, the reset terminal of the first D flip-flop F/L1 receives the target reset signal bga_rstb, and the non-inverting output terminal Q of the first D flip-flop F/L1 outputs the target column selection window signal cslslv_a.

As shown in fig. 6, the clock terminal CK of the first D flip-flop F/L1 may receive the target column selection start signal bga_cslen, and the target column selection start signal bga_cslen is used as the clock signal of the first D flip-flop F/L1, which helps to reduce power consumption. This is because the column selection start signal CSLEN0T is sent to each of the target signal generating circuits 112, and the target column selection start signal bga_cslen is generated only when the corresponding target bank group selection signal bg_a is received, so that the clock terminal CK of the first D flip-flop F/L1 does not receive the valid target column selection start signal bga_cslen, and the first D flip-flop F/L1 does not sample and output the corresponding target bank group selection signal bg_a, thereby contributing to reducing power consumption.

Specifically, taking the clock terminal CK of the first D flip-flop F/L1 receiving the target column selection start signal bga_cslen as an example, the positive phase output terminal Q outputs a high level signal from the start of the target column selection start signal bga_cslen. When the target reset signal bga_rstb is in an active state, the non-inverting output terminal Q outputs a low level signal, i.e., the target column selection window signal cslslv_a changes from active to inactive.

It should be noted that, in the embodiments of the present disclosure, reference is made to the concept of "high level" and "low level", which are both relative concepts, and a signal higher than a preset level is a high level signal, and a signal lower than a preset voltage is a low level signal, where the high level signal may be represented by "1", and the low level signal may be represented by "0".

With continued reference to fig. 6, the first D flip-flop F/L1 may further have an inverted clock trigger terminal CKB receiving an inverted signal of the target column selection start signal bga_cslen or the column selection start signal CSLEN 0T. In other words, the clock signal received by the inverted clock trigger terminal CKB is in opposite phase to the clock signal received by the clock terminal CK.

Referring to fig. 3, the termination signal generating circuit 32 is configured to receive the target column selection window signal cslslv_a and the column selection termination signal CSLDIS and perform a second and operation, generate and output a target column selection termination signal bga_csldis.

Fig. 7 is a schematic circuit diagram of a termination signal generating circuit according to an embodiment of the disclosure. Referring to fig. 7, the termination signal generating circuit 32 may include a second nand gate ANN2 and a third inverter Inv3.

One input end of the second nand gate ANN2 receives the target column selection window signal cslslv_a, and the other input end receives the column selection termination signal CSLDIS.

The input terminal of the third inverter Inv3 is connected to the output terminal of the second nand gate ANN2, and the output terminal outputs the target column selection termination signal bga_csldis.

Fig. 8 is a schematic circuit diagram of a control signal generating circuit according to an embodiment of the disclosure. Referring to fig. 8, an output terminal of the first nand gate ANN1 may be connected to an inverted clock trigger terminal CKB of the first D flip-flop F/L1.

Fig. 9 to 12 are several different timing diagrams of signals in the column control circuit according to the embodiments of the present disclosure.

Referring to fig. 9 to 12, ck represents a clock signal, and the clock period of ck is 1T. The target bank group selection signals bg_a and bg_h are sequentially valid, and the valid duration of each of the target bank group selection signals bg_a and bg_h is the second delay time tccd_s, which may be 8T, and the pulse width of the column selection start signal CSLEN0T may be 2T.

In fig. 9, two target bank group selection signals sequentially appearing are respectively directed to different target bank groups, and the corresponding target reset signals bga_rstb and bgh_rstb are the same as the reset signal RSTB.

In fig. 10 to 12, two target bank group selection signals that occur consecutively are respectively for the same target bank group, taking bg_a as an example of the target bank group selection signal corresponding to the target bank group.

As shown in fig. 11, the reset signal RSTB corresponding to the previous target bank group selection signal bg_a is completely overlapped with the next target bank group selection signal bg_a in time, and the target reset signal bga_rstb has the mask period RA1 corresponding to the overlapped period, so that the mask period RA1 of the target reset signal bga_rstb is disabled. Accordingly, the target column selection window signal cslslv_a generated based on the next target bank group selection signal bg_a has a validity period RA2 temporally corresponding to the mask area RA1, and the validity period RA2 of the target column selection window signal cslslv_a is valid. Thus, the target column selection window signal cslslv_a corresponding to the two target bank group selection signals bg_a remains active all the time.

As shown in fig. 12, the reset signal RSTB corresponding to the previous target bank group selection signal bg_a is partially overlapped with the next target bank group selection signal bg_a in time, and the target reset signal bga_rstb has the mask period RA1 corresponding to the overlapped period, so that the mask period RA1 of the target reset signal bga_rstb is disabled. Accordingly, the target column selection window signal cslslv_a generated based on the next target bank group selection signal bg_a has a validity period RA2 corresponding in time to the mask period RA1, and the validity period RA2 of the target column selection window signal cslslv_a is valid. In this way, even if the reset signal RSTB is active during the period when the next target bank group selection signal bg_a is active, the target column selection window signal cslslv_a corresponding to the next target bank group selection signal bg_a is generated. The time interval between the two target column selection window signals cslslv_a corresponding to the two target bank group selection signals bg_a is smaller than the pulse width of the reset signal RSTB.

The first column selection start signal CSLEN0T may have a delay with respect to the target bank group selection signal bg_a, and the second column selection start signal CSLEN0T may have a delay with respect to the target bank group selection signal bg_h. The column selection end signal CSLDIS has a first delay T1 compared to the column selection start signal CSLEN0T, the reset signal RSTB has a second delay T2 compared to the column selection start signal CSLEN0T, and the pulse width of the target column selection window signal cslslv_a is T3, T3 being equal to T2.

It is understood that the second delay amount satisfies with the first delay amount: 2T is less than or equal to T2-T1, wherein T2 is a second delay amount, T1 is a first delay amount, 2T is the effective duration of the column selection start signal CSLEN0T, and T is 1 clock cycle. It should be noted that, although T2-t1=2t in fig. 9, in practice, the clock rising edge of the reset signal RSTB may also occur later than the clock falling edge of the column selection termination signal CSLDIS, i.e., T2-T1 > 2T, so that the clock falling edge of the target column selection window signal may be aligned with the clock rising edge of the reset signal.

In addition, in some examples, t2-t1 < tccd_s, where the difference between the second delay amount and the first delay amount is smaller than tccd_s, which is advantageous for avoiding signal interference between the reset signal RSTB corresponding to one bank group and the column selection termination signal CSLDIS corresponding to another bank group, and tccd_s is the effective duration of the selection signal of the target bank group.

In summary, each signal generated by the column control circuit may satisfy the following conditions: in one aspect, during each target bank group selection signal active period, the corresponding target column selection window signal is active; on the other hand, it is ensured that the target column selection window signal may overlap the column selection termination signal, i.e. that the pulse width of the target column selection window signal overlaps in time with the pulse width of the column selection termination signal.

In addition, in order to ensure the effective duration of the target column selection termination signal, the foregoing target column selection window signal may cover the column selection termination signal, which may specifically mean that a portion where the pulse width of the target column selection window signal overlaps with the pulse width of the column selection termination signal in time is the same as the pulse width of the column selection termination signal, so that the effective duration of the target column selection termination signal may be the same as the effective duration of the column selection termination signal.

In other examples, if the active duration of the target column selection termination signal is less than the active duration of the column selection termination signal, the target column selection window signal may overlap the column selection termination signal, or specifically, a portion of the pulse width of the target column selection window signal overlapping the pulse width of the column selection termination signal in time is less than the pulse width of the column selection termination signal.

Fig. 13 is a further functional block diagram of a column control circuit according to an embodiment of the present disclosure, and fig. 14 and 15 are two other timing diagrams of signals in the column control circuit according to an embodiment of the present disclosure. Referring to fig. 9 and 13 in combination, the delay control circuit 101 may receive the delay selection signal tccll and adjust the first delay amount t1 and the second delay amount t2 based on the delay selection signal tccll.

As shown in fig. 9, T1 may be 6T, and the corresponding T2 may be greater than or equal to 8T. T1 may be 7T and the corresponding T2 may be greater than or equal to 9T. T1 may be 8T and the corresponding T2 may be greater than or equal to 10T. T1 may be 9T and the corresponding T2 may be greater than or equal to 11T. T1 may be 11T and the corresponding T2 may be greater than or equal to 13T.

Referring to fig. 9, T1 in fig. 9 is actually 6T, T2 is 8T, and T3 is 8T; referring to fig. 14, taking T1 as 8T as an example in fig. 14, T2 as 10T, and T3 as 10T; referring to fig. 15, in fig. 15, taking T1 as 11T as an example, T2 as 13T, and T3 as 13T.

Fig. 16 is a functional block diagram of a delay control circuit. Referring to fig. 16, the delay selection signal includes a first delay selection signal tccdl_1 and a second delay selection signal tccdl_2; the delay control circuit 101 may include a delay circuit 11, a first gate circuit 21, and a second gate circuit 31.

Delay circuit 11 has an input node Din and N output nodes Dout1-DoutN, identified as Dout1, dout2 … … DoutN-1 and DoutN, respectively. The delay circuit 11 is configured to receive the column selection start signal CSLEN0T via the input node Din and output N delay signals DL1 via N output nodes Dout1-DoutN, wherein the N output nodes Dout1-DoutN include 1 st to N th output nodes arranged in a natural number increasing order, and the delay amounts of the N delay signals DL1 output by the 1 st to N th output nodes with respect to the column selection start signal CSLEN0T are sequentially increased, N being a natural number of 2 or more.

The delay amount of each delay signal DL1 compared to the column selection start signal CSLEN0T may be sequentially 1T, 2T, 3T, 4T, 5T, 6T, 7T, 8T, 9T, 10T, 11T, 12T, 13T. The N delay signals DL1 may be CSLEN1T, CSLEN2T, CSLEN T … CSLENnT … CSLENNT, CSLENnT, respectively, which refers to a delay amount nT with respect to the column selection start signal CSLEN0T, where N is a positive integer equal to or less than N. The delay amount of the delay signal DL1 outputted by the output node Doutn is nT compared with the column selection start signal CSLEN 0T.

Fig. 17 is a schematic circuit configuration diagram of the delay circuit. Referring to fig. 16 and 17 in combination, the delay circuit 11 may include N cascaded second D flip-flops H/L2, the data input terminal of the second D flip-flop H/L2 at the first stage is taken as the input node Din, and the inverting output terminal of the second D flip-flop H/L2 at the previous stage is connected to the data input terminal of the second D flip-flop H/L2 at the subsequent stage.

The clock ends of the second D flip-flops H/L2 at the odd positions all receive the clock signal PCLKB, and the clock ends of the second D flip-flops H/L2 at the even positions all receive the inverted clock signal PCLKD, and the inverted clock signal PCLKD and the clock signal PCLKB are mutually inverted signals. The inverting output ends of the N second D flip-flops H/L2 serve as N output nodes Dout1-DoutN.

Specifically, the inverting output terminal of the second D flip-flop H/L2 of the first stage is taken as the output node Dout1, the inverting output terminal of the second D flip-flop H/L2 of the second stage is taken as the output node Dout2, and so on, and the inverting output terminal of the second D flip-flop H/L2 of the nth stage is taken as the output node DoutN.

Correspondingly, the delay signal output by the inverting output terminal of the second D flip-flop H/L2 in the odd position is opposite to the active level of the column selection start signal CSLEN0T, and the delay signal output by the inverting output terminal of the second D flip-flop H/L2 in the even position is identical to the active level of the column selection start signal CSLEN 0T.

Wherein the active level of the delay signal CSLEN1T, CSLEN3T, CSLEN T … is opposite to the active level of the column select Start signal CSLEN 0T; the active level of the delay signal CSLEN2T, CSLEN4T, CSLEN6T … is the same as the active level of the column select start signal CSLEN0T.

In some embodiments, the delay circuit 11 may be further configured to generate a column selection start signal CSLEN0T in response to a read operation command, and to supply the column selection start signal CSLEN0T to the input node Din.

It will be appreciated that the delay circuit 11 may also be configured to generate the column selection start signal CSLEN0T in response to a write operation command and to supply the column selection start signal CSLEN0T to the input node Din.

If the operation performed on the bank group is a read operation, a column selection start signal CSLEN0T is generated based on the read operation command. If the operation performed on the bank group is a write operation, a column selection start signal CSLEN0T is generated based on the write operation command.

Fig. 18 is a schematic circuit diagram of a delay circuit. Referring to fig. 18, the delay circuit 11 may include an even number of cascaded third D flip-flops H/L3. The data input end of the third D trigger H/L3 positioned at the first stage receives a READ operation command READ or a write operation command, and the reverse phase output end of the third D trigger H/L3 positioned at the previous stage is connected with the data input end of the third D trigger H/L3 positioned at the next stage.

The clock ends of the third D flip-flops H/L3 at the odd positions all receive the clock signal PCLKB, and the clock ends of the third D flip-flops H/L3 at the even positions all receive the inverted clock signal PCLKD, and the inverted clock signal PCLKD and the clock signal PCLKB are mutually inverted signals.

The inverting output terminal of the third D flip-flop H/L3 of the last stage is connected with the input node Din and outputs a column selection start signal CSLEN0T.

In fig. 18, 2 third D flip-flops H/L3 are schematically shown, and in practice, the delay circuit 11 may have any even number of third D flip-flops H/L3, such as 4 or 6.

With continued reference to fig. 16, the first gating circuit 21 is connected to m output nodes, has a first output terminal O1, and is configured to gate a transmission path between one of the m output nodes and the first output terminal O1 in response to the first delay selection signal tccll_1 to output a column selection termination signal CSLDIS via the first output terminal O1, m being a natural number of N or less.

Fig. 19 and 20 are two different functional block diagrams of a first gating circuit provided by an embodiment of the present disclosure.

Referring to fig. 19, the first gating circuit 21 may include one first gating unit 201. The first gating units 201 have first nodes n1, and each first gating unit 201 is connected to two corresponding and adjacent output nodes of the m output nodes. Each first gating unit 201 is configured to gate a transmission path between one of the two output nodes and the first node n1 in response to the first delay selection signal tccldl_1. Wherein, two adjacent output nodes are respectively marked as Doutx and Doutx+1, wherein, 2 is less than x+1 and less than or equal to N, and x is a positive integer.

The first node n1 and the first output terminal O1 may be directly connected. In addition, it will be understood that in some examples, the active levels of the delay signals output from two adjacent output nodes are opposite, the two output nodes are respectively defined as a first output node and a second output node, the active level of the delay signal output from the first output node is the same as the active level of the column selection start signal CSLEN0T, the active level of the delay signal output from the second output node is opposite to the active level of the column selection start signal CSLEN0T, the first output node is directly connected to the first output terminal O1, and the second output node is connected to the first output terminal O1 via an inverter, which can invert the active level of the delay signal output from the second output node.

Referring to fig. 20, the first gating circuit 21 may include two or more first gating units 201, each first gating unit 201 having a first node n1, and each first gating unit 201 being connected to a different output node. The first gating circuit 21 may further include a first or gate 202, an input terminal of the first or gate 202 is connected to each first node n1, and an output terminal of the first or gate 202 is connected to the first output terminal O1. Wherein two adjacent output nodes connected by the other first gating unit 201 are respectively identified as Douty and douty+1.2 < y+1.ltoreq.N, x, x+1, y and y+1 being different from each other.

For a detailed description of the first gating unit 201, reference may be made to the foregoing description.

Fig. 21 is a schematic circuit diagram of any first gating unit. Referring to fig. 21, the first delay selection signal may include p-bit first control codes, each of the first gating units 201 receives the corresponding three first control codes, p is a natural number greater than or equal to 3, and the effective levels of the delay signals output from the adjacent two output nodes are opposite. The first control code per bit may be 0 or 1. The first delay select signal may be a binary signal, the number of bits in the p bits referring to the number of bits in binary. The value of the first control code is 0 or 1.

Referring to fig. 21, the first gating unit 201 may include a third nand gate ANN3, a fourth inverter Inv4, a second AND gate AND2, a third AND gate AND3, AND a fourth nand gate ANN4.

The two input ends of the third nand gate ANN3 respectively receive the inverted signal of a corresponding one of the three first control codes. The inverted signals of the first control code received by the third nand gate ANN3 are identified as tcdl 11B and tcdl 21B, respectively, tcdl 11B being the inverted signal of the first control code tcdl 11 and tcdl 21B being the inverted signal of the first control code tcdl 21. Fig. 21 also illustrates the relationship among tcdl 11, tcdl 11B, tCCDL, tcdl 21B, and the first control code is inverted by the zeroth inverter Inv0 and then outputs the corresponding inverted signal.

The input of the fourth inverter Inv4 is connected to an output node.

The two input terminals of the second AND gate AND2 are connected to the output terminal of the third nand gate ANN3 AND the output terminal of the fourth inverter Inv4, respectively. The second AND gate AND2 may include a first sub-nand gate 41 AND a first sub-inverter 402, two input terminals of the first sub-nand gate 41 being two input terminals of the second AND gate AND2, an output terminal of the first sub-nand gate 41 being connected to an input terminal of the first sub-inverter 402, AND an output terminal of the first sub-inverter 402 being an output terminal of the second AND gate AND 2.

One input terminal of the third AND gate AND3 receives the remaining one of the three first control codes, the other input terminal is connected to the other output node, AND the first control code received by the third AND gate AND3 is identified as tccll 31. The third AND gate AND3 may include a second sub-nand gate 43 AND a second sub-inverter 44, two input terminals of the second sub-nand gate 43 being two input terminals of the third AND gate AND3, an output terminal of the second sub-nand gate 43 being connected to an input terminal of the second sub-inverter 44, AND an output terminal of the second sub-inverter 44 being an output terminal of the third AND gate AND 3.

The input end of the fourth nand gate ANN4 is connected to the output end of the second AND gate AND2 AND the output end of the third AND gate AND3, respectively, AND the output end of the fourth nand gate ANN4 is used as the first node n1.

It should be noted that, in the specific circuit related to the first gating unit 201, the following logic requirements may be satisfied: for an output node provided with the same active level of the delay signal as the column selection start signal CSLEN0T, this output node is connected via an inverter to a respective AND gate, which may be one of the second AND gate AND2 or the third AND gate AND 3. For an output node provided with an active level of the delay signal opposite to the active level of the column selection start signal CSLEN0T, this output node is then directly connected to the corresponding AND gate, which may be one of the second AND gate AND2 or the third AND gate AND 3.

Fig. 22 is a schematic circuit diagram of a first gating circuit. Referring to fig. 22, the first gating circuit 21 includes three first gating units 201. It should be noted that fig. 22 is only one specific implementation of the first gating circuit with a delay range of 6T-11T compared to the column selection start signal CSLEN0T, and the embodiment of the disclosure is not limited to the specific circuit structure of the first gating circuit, and other specific circuit structures with a delay of 6T-11T compared to the column selection start signal CSLEN0T may be used as the first gating circuit. Furthermore, the specific circuit configuration of the corresponding first gate circuit may also be different for different delay ranges.

The delayed signals received by the first gating unit 201 are CSLEN6T AND CSLEN7T, the inverted signals of the two first control codes received by the third nand gate ANN3 are respectively identified as tcdl 8B AND tcdl 9B, the first control code received by the third AND gate AND3 is identified as tcdl 10, where, taking tcdl 8B AND tcdl 8 as an example, tcdl 8B corresponds to the inverted signal of the first control code tcdl 8, one of the first control code AND the corresponding inverted signal is 0 AND the other is 1, AND for avoiding redundancy, the description of tcdl 9B, tCCDL12B, tCCDL 5713B, tCCDL B AND tcdl 16B with reference to tcdl_8b will not be described in detail later. As can be seen from the analysis described above, the output node Dout6 of the receiving CSLEN6T is connected to the second AND gate AND2 via the fourth inverter Inv4, AND the output node Dout7 of the receiving CSLEN7T is directly connected to the third AND gate AND3.

The delay signals received by the other first gating unit 201 are CSLEN8T AND CSLEN9T, the inverted signals of the two first control codes received by the third nand gate ANN3 are respectively identified as tcdl 12B AND tcdl 13B, AND the first control code received by the third AND gate AND3 is identified as tcdl 11. tcdl 12B corresponds to an inverted signal of tcdl 12 and tcdl 13B corresponds to an inverted signal of tcdl 13. As can be seen from the analysis described above, the output node Dout8 of the receiving CSLEN8T is connected to the third AND gate AND3 via the fourth inverter Inv4, AND the output node Dout9 of the receiving CSLEN9T is directly connected to the second AND gate AND2.

The delay signals received by the first gating unit 201 are CSLEN10T AND CSLEN11T, the inverted signals of the two first control codes received by the third nand gate ANN3 are respectively identified as tcdl 15B AND tcdl 16B, AND the first control code received by the third AND gate AND3 is identified as tcdl 14. tcdl 15B corresponds to an inverted signal of tcdl 15 and tcdl 16B corresponds to an inverted signal of tcdl 16. As can be seen from the above analysis, the output node Dout10 of the receiving CSLEN10T is connected to the third AND gate AND3 via the fourth inverter Inv4, AND the output node Dout11 of the receiving CSLEN11T is directly connected to the second AND gate AND2. It is understood that the first control code outputs a corresponding inverted signal after being inverted via the inverter.

With continued reference to fig. 16, the second gating circuit 31 connects N output nodes, has a second output terminal O2, and is configured to gate a transmission path between one of the N output nodes and the second output terminal O2 in response to the second delay selection signal tccll_2 to output the reset signal RSTB via the second output terminal O2, N being a natural number of N or less. In some examples, the first delay amount t1 may be determined using the correspondence shown in table 1 on the premise that the time for which the column select communication is enabled is 3ns or more.

TABLE 1

Referring to table 1, the greater the operating frequency, the smaller tCK. The number of clock cycles, the operating frequency, the first delay amount t1 of the first delay time tccd_l, the multiple of tCK, and the first delay amount t1 have the correspondence relationship as shown in table 1. The number of clock cycles of the first delay time tccd_l having a fixed time (for example, 5 ns) may vary with the variation of the operating frequency according to the relationship of table 1 (since the first delay time tccd_l is equal to the number of clock cycles multiplied by tCK, and tCK decreases with the increase of the operating frequency), i.e., the operating frequency may be indicated by the number of clock cycles of the first delay time tccd_l to determine the value of the first delay selection signal tccdl_1 (only 1 bit of the first control codes tCCDL8-tCCDL16 is 1 and the remaining first control codes are 0), and the specific value of the first delay amount t1 at different operating frequencies is selected according to the value of the first delay selection signal tccdl_1. In table 1, the number of clock cycles of the first delay time tccd_l is any natural number between 8 and 16, the value of the number of clock cycles of the first delay time tccd_l is determined, and the value of the first delay selection signal tccdl_1 is also determined accordingly, and the corresponding selected first delay amount is also determined.

The correspondence between the number of clock cycles of the first delay time tccd_l and the value of the first delay selection signal tccdl_1 in table 1 may be implemented by a decoder, i.e. the number of clock cycles of the first delay time tccd_l is taken as the input of the decoder and the value of the first delay selection signal tccdl_1 is taken as the output of the decoder. The value of the first delay selection signal tccldl_1 in table 1 is related to the value of the p-bit first control code, and when the value of the first delay selection signal tccldl_1 is determined, the value of each of the p-bit first control codes is also determined. The value of the first delay selection signal tccldl_1 may be related to a binary value formed by q-bit second control codes, and when the value of the first delay selection signal tccldl_1 is determined, the value of each of the q-bit second control codes is also determined.

Fig. 23 and 24 are two different functional block diagrams of a second gating circuit provided by an embodiment of the present disclosure.

Referring to fig. 23, the second gating circuit 31 may include one second gating unit 301, each second gating unit 301 having a second node n2 and connecting corresponding and adjacent two output nodes of the n output nodes; each of the second gating units 301 is configured to gate a transmission path between one of the two output nodes and the second node n1 in response to the second delay selection signal tccldl_2. Wherein, two adjacent output nodes are respectively identified as Douta and douta+1.

The second delay selection signal tccldl_2 and the first delay selection signal tccldl_1 may be the same signal.

The second node n2 and the second output O2 may be directly connected. In addition, it will be understood that in some examples, the active levels of the delay signals output by two adjacent output nodes are opposite, the two output nodes are respectively defined as a first output node and a second output node, the active level of the delay signal output by the first output node is the same as the active level of the column selection start signal CSLEN0T, the active level of the delay signal output by the second output node is opposite to the active level of the column selection start signal CSLEN0T, the first output node is directly connected to the second output terminal O2, and the second output node is connected to the second output terminal O2 via an inverter, and the inverter can invert the active level of the delay signal output by the second output node.

It will be appreciated that the relation between the output nodes to which the second gate circuit 31 and the first gate circuit 21 are respectively connected may be determined based on the delay difference between the column selection termination signal CSLDIS and the reset signal RSTB.

Referring to fig. 24, the second gating circuit 31 includes at least two second gating units 301, and each second gating unit 301 is connected to a different output node. The second gating circuit 31 further includes a second or gate 302, an input terminal of the second or gate 302 is connected to each second node n2, and an output terminal of the second or gate 302 is connected to the second output terminal O2. The output nodes connected to a second strobe unit 301 are respectively identified as Doutb and doutb+1.

Fig. 25 is a schematic circuit diagram of any second gating unit. Referring to fig. 25, the second delay selection signal includes q-bit second control codes, each second gating unit 301 receives the corresponding three second control codes, q is a natural number greater than or equal to 3, and the effective levels of the delay signals output from the adjacent two output nodes are opposite. The second control code per bit may be 0 or 1. The second delay select signal may be a binary signal, the number of bits in the q bits referring to the number of bits in binary. The value of the second control code is 0 or 1.

Referring to fig. 25, the second gating unit 301 includes a fifth nand gate ANN5, a fifth inverter Inv5, a fourth AND gate AND4, a fifth AND gate AND5, AND a sixth nand gate ANN6.

The two input ends of the fifth nand gate ANN5 respectively receive the inverted signal of a corresponding one of the three second control codes. The inverted signals of the second control code received by the fifth nand gate ANN5 are identified as tcdl 12B and tcdl 22B, respectively. tcdl 12B is an inverted signal of the second control code tcdl 12, and tcdl 22B is an inverted signal of the second control code tcdl 22. Fig. 25 also illustrates the relationship among tcdl 12, tcdl 12B, tCCDL, tcdl 22B, and the second control code is inverted via the zeroth inverter Inv0 and then outputs the corresponding inverted signal.

The input of the fifth inverter Inv5 is connected to an output node.

The two input terminals of the fourth AND gate AND4 are connected to the output terminal of the fifth nand gate ANN5 AND the output terminal of the fifth inverter Inv5, respectively.

The fourth AND gate AND4 may include a third sub-nand gate 51 AND a third sub-inverter 52, AND an output terminal of the third sub-nand gate 51 is connected to an input terminal of the third sub-inverter 52.

One input end of the fifth AND gate AND5 receives the rest of the three second control codes, AND the other input end is connected with the other output node. The second control code received by the fifth AND gate AND5 is identified as tcdl 32.

The third AND gate AND3 may include a fourth sub-nand gate 53 AND a fourth sub-inverter 54, AND an output terminal of the fourth sub-nand gate 53 is connected to an input terminal of the fourth sub-inverter 54.

AND the input end of the sixth NAND gate ANN6 is respectively connected with the output end of the fourth AND gate AND4 AND the output end of the fifth AND gate AND5, AND the output end of the sixth NAND gate ANN6 is used as a second node n2.

It should be noted that, in the specific circuit related to the second gating unit 301, the following logic requirements may be satisfied: for an output node provided with the same active level of the delay signal as the column selection start signal CSLEN0T, this output node is connected via an inverter to a respective AND gate, which may be one of the fourth AND gate AND4 or the fifth AND gate AND 5. For an output node provided with an active level of the delay signal opposite to the active level of the column selection start signal CSLEN0T, this output node is then directly connected to the corresponding AND gate, which may be one of the fourth AND gate AND4 or the fifth AND gate AND 5.

Fig. 26 is a schematic circuit diagram of a second gating circuit. Referring to fig. 26, the second gating circuit 31 includes three second gating units 301. It should be noted that fig. 26 is only one specific implementation of the second gating circuit with a delay range of 8T-13T compared to the column selection start signal CSLEN0T, and the embodiment of the disclosure is not limited to the specific circuit structure of the second gating circuit, and other specific circuit structures capable of implementing the delay signal with a delay of 8T-13T compared to the column selection start signal CSLEN0T may be used as the second gating circuit. Furthermore, the specific circuit configuration of the corresponding second gate circuit may also be different for different delay ranges.

The delay signals received by one second gating unit 301 are CSLEN8T AND CSLEN9T, the inverted signals of the two second control codes received by the fifth nand gate ANN5 are respectively identified as tcdl 8B AND tcdl 9B, AND the second control code received by the fifth AND gate AND5 is identified as tcdl 10.

The delay signals received by the other second gating unit 301 are CSLEN10T AND CSLEN11T, the inverted signals of the two second control codes received by the fifth nand gate ANN5 are respectively identified as tcdl 12B AND tcdl 13B, AND the second control code received by the fifth AND gate AND5 is identified as tcdl 11.

The delayed signals received by the further second gating unit 301 are CSLEN12T and CSLEN12T, and the inverted signals of the two second control codes received by the fifth nand gate ANN5 are identified as tcdl 15B and tcdl 16B, respectively. The second control code received by the fifth AND gate AND5 is identified as tcdl 14.

In fig. 22 and 26, the same portion of the first control code as the second control code indicates that the corresponding first control code has the same value as the second control code. For example, the values of the first control codes identified as tcdl 8, tcdl 9 and tcdl 10 are the same as the corresponding values of the second control codes identified as tcdl 8, tcdl 9 and tcdl 10, respectively. More specifically, the value of the first control code identified as tcdl 8 is the same as the value of the second control code identified as tcdl 8. In other words, in some examples, the first delayed selection signal may be the same as the second delayed selection signal.

Referring to fig. 22 and 26 in combination, the delay control circuit 101 may generate several sets of column selection termination signals CSLDIS and reset signals RSTB as shown in table 2, where t2-t1 is the difference between the second delay amount and the first delay amount:

TABLE 2

It is clear that table 2 corresponds to table 1. For example, when CSLDIS is CSLEN6T, that is, the first delay amount T1 is a multiple of 6 compared to tCK, as shown in tables 1 and 2, tcdl 8 may be 1 or tcdl 9 may be 1, and the first delay time tccd_l may be 1 compared to a multiple of tCK/number of clock cycles 8, and tcdl 9 may be 1 compared to a multiple of tCK/number of clock cycles 9. When CSLDIS is CSLEN7T, the first delay amount T1 is 7 as compared to tCK, and tcdl 10 is 1 as shown in tables 1 and 2.

It is to be understood that the circuit of the delay control circuit is not particularly limited, and the delay control circuit may be applied to the embodiment of the present disclosure as long as it can select one output from a plurality of delay signals as a column selection end signal, and select one output from a plurality of delay signals as a reset signal, where the delay amount of the reset signal (i.e., the second delay amount) compared to the column selection start signal is greater than the delay amount of the column selection end signal (i.e., the first delay amount) compared to the column selection start signal.

Further, in some specific examples, in order to ensure that the pulse width of the target column selection end signal is sufficient, the pulse width of the target column selection end signal is defined as mT being a sufficient pulse width, and the difference between the second delay amount and the first delay amount may be greater than or equal to mT. Taking the pulse width of the target column selection termination signal as 2T as a sufficient example, the difference between the second delay amount and the first delay amount is greater than or equal to 2T.

Accordingly, the embodiments of the present disclosure also provide a memory device, which may include the column control circuit provided in the above embodiments. The following description will be given of a storage device provided by an embodiment of the present disclosure, and the content of the foregoing embodiment is equally applicable to an embodiment of a storage device.

Fig. 27 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure, and fig. 28 is a schematic structural diagram of a memory cell array in a bank group BankGroupA.

Referring to fig. 27 and 28, the memory device includes a column control circuit 300 and a plurality of bank groups, each of which includes a plurality of memory cell arrays, each of which includes a plurality of memory cells, each of which is connected to a plurality of column selection switching transistors 221.

The memory device may be a random access memory device (RAM), a read only memory device (ROM), a crystalline random access memory device (SRAM), a dynamic random access memory Device (DRAM), a synchronous dynamic random access memory device (SDRAM), a resistive random access memory device (RRAM), a double rate memory device (DDR), a low power double data rate memory device (LPDDR), a phase change memory device (PCM), or a flash memory device.

The different bank groups are identified as BankGroupA, bankGroupB … … BankGroupH, respectively. The column control circuit 300 receives the column selection start signal CSLEN0T and the target bank group selection signal BG, generates a target column selection start signal and a target column selection end signal, and also generates a target column selection window signal.

In fig. 27, for bank group BankGroupA, the target column selection start signal and the target column selection end signal are bga_cslen and bga_csldis, respectively. The target column selection start signal and the target column selection end signal are bgb_cslen and bgb_csldis, respectively, for the bank group BankGroupB. For bank group BankGroupH, the target column select start signal and the target column select end signal are BGH_CSLEN and BGH_CSLDIS, respectively.

In fig. 27, although the target column selection start signal and the target column selection end signal corresponding to different bank groups are identified, in practice, only one bank group may be selected as the target bank group at the same time, that is, only the target column selection start signal and the target column selection end signal for one bank group may be generated, and the target column selection start signal and the target column selection end signal corresponding to the remaining bank groups other than the target bank group may not be generated, or, the target column selection start signal and the target column selection end signal corresponding to the remaining bank groups other than the target bank group may be invalid.

Each BANK group may include a plurality of BANKs (BANKs), each including at least one memory cell array.

Referring to fig. 28, a memory cell array in a bank of the bank group BankGroupA is identified as A0. The partial number of column selection switch tubes 221 are controlled by the same column selection signal, i.e., the gates of the partial number of column selection switch tubes 221 are connected to the same column selection line CSL for transmitting the column selection signal to the partial number of column selection switch tubes 221. That is, the plurality of column selection switching tubes 221 receive the same column selection signal via the same column selection line CSL, and when one column selection signal is active, the column selection line CSL receiving the column selection signal is selected such that the column selection switching tube 221 connected to the column selection line CSL is turned on.

The memory cell array A0 has a plurality of bit lines BL, each of which is connected to the sense amplifier 211, and each of which is further connected to the local data line LIO via a column selection switch 221, and a column selection line CSL is connected to a gate of each of the column selection switch 221. If the column selection switch 221 is turned on, the transmission path between the bit line BL and the local data line LIO is turned on to realize the transmission between the bit line BL and the local data line LIO, and the local data line LIO is connected to the read/write circuit to realize the data transmission between the local data line LIO and the global data line through the read/write circuit.

In some examples, according to the arrangement positions of all bit lines BL of the memory cell array A0, the bit line BL in the odd bit may be connected to one local data line LIO via the column selection switch 221, and the bit line in the even bit may be connected to another local data line LIO via the column selection switch 221, where each sense amplifier array includes a plurality of sense amplifiers 211. In this way, when the column selection line CSL is selected, that is, when the column selection signal received by the column selection line CSL is valid, the column selection switching transistors 221 connected to the two local data lines LIO are turned on, thereby turning on the transmission paths between the bit lines BL of the memory cell array A0 and the corresponding local data lines LIO.

In one example, the column selection switch 221 may be an NMOS transistor, and if the column selection signal transmitted by the column selection line CSL is valid, i.e. 1, the column selection switch 221 of the corresponding column is turned on.

Taking the operation performed on the bank group as a read operation, the read command includes a bank group selection signal (or called BG address), a bank selection signal (or called BA address), and a column address signal, where the column address signal is sent to each bank, and the bank selection signal is used to define the location of the target bank. Taking the target BANK group as BankGroupA and the target BANK as BANK1 as an example, the column control circuit 300 generates a target column selection start signal bga_clsen and a target column selection end signal bga_csldis corresponding to the target BANK group selection signal bg_a, while the target column selection start signal and the target column selection end signal corresponding to the remaining BANK groups are inactive.

The memory device may also include a column decode circuit 400. The column decoding circuit 400 generates an internal target column selection start signal and an internal target column selection end signal corresponding to the target bank based on the target column selection start signal bga_clsen, the target column selection end signal bga_csldis, and the bank selection signal BA 1. Wherein, the BANK select signal BA1 characterizes BANK1 as the target BANK. The column decoding circuit 400 also generates and outputs a column selection signal based on the received column address signal ADDR, the internal target column selection start signal, and the internal target column selection end signal, which is supplied to the column selection line CSL by the column decoding circuit 400.

The column selection switching tube 221 is turned on in response to a corresponding internal target column selection start signal and turned off in response to a corresponding internal target column selection end signal. Specifically, when the internal target column selection start signal is active, the column selection switch tube 221 is turned on, and when the internal target column selection end signal is active, the column selection signal is changed from active to inactive, and the column selection switch tube 221 is turned off.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A column control circuit, comprising:

a delay control circuit configured to receive a column selection start signal, perform delay processing on the column selection start signal, and generate and output a column selection end signal and a reset signal; wherein the column selection termination signal has a first delay amount with respect to the column selection start signal, and the reset signal has a second delay amount with respect to the column selection start signal, the second delay amount being greater than the first delay amount;

a control signal generating circuit connected to the delay control circuit and configured to receive the column selection start signal, the reset signal, the column selection end signal, and a target bank group selection signal, perform a first and operation on the column selection start signal and the target bank group selection signal to generate and output a target column selection start signal, generate and output a target column selection window signal based on the target column selection start signal, the target bank group selection signal, and the reset signal, and perform a second and operation on the target column selection window signal and the column selection end signal to generate and output a target column selection end signal;

The target column selection window signals are in an effective state from the starting time when the target column selection starting signals are in an effective state until the reset signals are effective, and the effective time length of the target column selection window signals is greater than or equal to the effective time length of the target memory bank group selection signals.

2. The column control circuit according to claim 1, wherein the control signal generation circuit includes:

a plurality of target signal generating circuits, each corresponding to a bank group, each corresponding to a target bank group selection signal; each of the target signal generating circuits corresponding to each of the bank groups is configured to,

the column selection start signal, the reset signal, the column selection end signal, and the target bank group selection signal corresponding to the bank group are received, and the target column selection start signal, the target column selection window signal, and the target column selection end signal corresponding to the bank group are output.

3. The column control circuit according to claim 2, wherein the target signal generation circuit includes:

A start signal generating circuit configured to receive the column selection start signal and the target bank group selection signal and perform the first and operation, generate and output the target column selection start signal;

a reset signal generating circuit configured to receive the reset signal and the target bank group selection signal and perform a logic operation to generate and output a target reset signal;

a window signal generating circuit configured to output the target column selection window signal based on the target reset signal, the target bank group selection signal, and the target column selection start signal, wherein the target column selection window signal is in an active state during which the target column selection window signal is in an inactive state from when the target column selection start signal is active until when the target reset signal is active;

and a termination signal generating circuit configured to receive the target column selection window signal and the column selection termination signal and perform the second AND operation, and generate and output the target column selection termination signal.

4. The column control circuit of claim 3, wherein the start signal generation circuit comprises:

a first NAND gate, two input terminals respectively receiving the target bank group selection signal and the column selection start signal;

and the input end of the first inverter is connected with the output end of the first NAND gate, and the output end of the first inverter outputs the target column selection starting signal.

5. The column control circuit of claim 3, wherein the reset signal generation circuit comprises:

the second inverter, the input end receives the said goal memory bank group selection signal, the output end outputs the inverted signal of the said goal memory bank group selection signal;

and one input end of the first AND gate is connected with the output end of the second inverter, one input end of the first AND gate receives the reset signal, and the output end of the first AND gate outputs the target reset signal.

6. The column control circuit of claim 3, wherein the window signal generation circuit comprises:

the data input end of the first D trigger receives the target memory bank group selection signal, the clock end of the first D trigger receives the target column selection starting signal or the column selection starting signal, the reset end of the first D trigger receives the target reset signal, and the non-inverting output end of the first D trigger outputs the target column selection window signal.

7. The column control circuit of claim 6, wherein the first D flip-flop further has an inverted clock trigger that receives the target column select start signal or an inverted signal of the column select start signal.

8. The column control circuit of claim 3, wherein the termination signal generation circuit comprises:

a second NAND gate, one input end of which receives the target column selection window signal and the other input end of which receives the column selection termination signal;

and the input end of the third inverter is connected with the output end of the second NAND gate, and the output end outputs the target column selection termination signal.

9. The column control circuit of claim 1, wherein the second delay amount and the first delay amount satisfy: and 2T is less than or equal to T2-T1, wherein T2 is the second delay amount, T1 is the first delay amount, 2T is the effective duration of the column selection start signal, and T is 1 clock cycle.

10. The column control circuit of claim 1, wherein the delay control circuit is further configured to receive a delay select signal and adjust the first delay amount and the second delay amount based on the delay select signal.

11. The column control circuit of claim 10, wherein the delay select signal comprises a first delay select signal and a second delay select signal; the delay control circuit includes:

a delay circuit having an input node and N output nodes configured to receive the column selection start signal via the input node and output N delay signals via the N output nodes, wherein the N output nodes include 1 st to N th output nodes arranged in a natural number increasing order, and delay amounts of the N delay signals output from the 1 st to N th output nodes with respect to the column selection start signal sequentially increase, N being a natural number of 2 or more;

a first gating circuit connected to the m output nodes, having a first output terminal configured to gate a transmission path between one of the m output nodes and the first output terminal in response to the first delay selection signal to output the column selection termination signal via the first output terminal, m being a natural number of N or less;

and a second gate circuit connected to the N output nodes and having a second output terminal configured to gate a transmission path between one of the N output nodes and the second output terminal in response to the second delay selection signal to output the reset signal via the second output terminal, N being a natural number of N or less.

12. The column control circuit of claim 11, wherein the delay circuit comprises:

the data input ends of the second D flip-flops in the first stage serve as the input nodes, and the inverting output ends of the second D flip-flops in the previous stage are connected with the data input ends of the second D flip-flops in the subsequent stage;

the clock ends of the second D flip-flops at the odd positions all receive clock signals, the clock ends of the second D flip-flops at the even positions all receive inverted clock signals, and the inverted clock signals and the clock signals are mutually inverted signals;

and the inverting output ends of the N second D flip-flops serve as N output nodes.

13. The column control circuit of claim 11, wherein the delay circuit is further configured to generate the column selection start signal in response to a read operation command and provide the column selection start signal to the input node.

14. The column control circuit of claim 13, wherein the delay circuit comprises:

the data input end of the third D flip-flop at the first stage receives the read operation command, and the inverting output end of the third D flip-flop at the previous stage is connected with the data input end of the third D flip-flop at the subsequent stage;

The clock ends of the third D flip-flops at the odd positions all receive clock signals, the clock ends of the third D flip-flops at the even positions all receive inverted clock signals, and the inverted clock signals and the clock signals are mutually inverted signals;

the inverting output end of the third D flip-flop of the last stage is connected with the input node and outputs the column selection starting signal.

15. The column control circuit of claim 11, wherein the first gating circuit comprises:

each first gating unit is provided with a first node, and each first gating unit is connected with two corresponding and adjacent output nodes in m output nodes; each of the first gating units is configured to gate a transmission path between one of the two output nodes and the first node in response to the first delay selection signal.

16. The column control circuit of claim 15, wherein said first delay selection signal comprises p-bit first control codes, each of said first strobe units receiving a corresponding three of said first control codes, p being a natural number greater than or equal to 3, the effective levels of said delay signals output by adjacent two of said output nodes being opposite; the first gating unit includes:

The two input ends of the third NAND gate respectively receive the inverted signals of corresponding one of the three first control codes;

the input end of the fourth inverter is connected with the output node;

the two input ends of the second AND gate are respectively connected with the output end of the third NAND gate and the output end of the fourth inverter;

the third AND gate, one input end receives the rest of three first control codes, another input end is connected with another output node;

and the input end of the fourth NAND gate is respectively connected with the output end of the second AND gate and the output end of the third AND gate, and the output end of the fourth NAND gate is used as the first node.

17. The column control circuit of claim 15, wherein said first gating circuit includes at least two of said first gating cells, and wherein each of said first gating cells is connected to a different one of said output nodes; the first gating circuit further includes:

and the input end of the first OR gate is connected with each first node, and the output end of the first OR gate is connected with the first output end.

18. The column control circuit of claim 11, wherein the second gating circuit comprises:

At least one second gating unit, each second gating unit has a second node and is connected with two corresponding and adjacent output nodes in the n output nodes; each of the second gating units is configured to gate a transmission path between one of the two output nodes and the second node in response to the second delay selection signal.

19. The column control circuit of claim 18, wherein said second delay selection signal includes q-bit second control codes, each of said second strobe units receiving a corresponding three of said second control codes, q being a natural number greater than or equal to 3, the effective levels of said delay signals output by adjacent two of said output nodes being opposite; the second gating unit includes:

a fifth NAND gate, wherein two input ends respectively receive the inverted signals of corresponding one of the three second control codes;

the input end of the fifth inverter is connected with the output node;

the two input ends of the fourth AND gate are respectively connected with the output end of the fifth NAND gate and the output end of the fifth inverter;

a fifth AND gate, one input end of which receives the rest of the three second control codes, and the other input end of which is connected with the other output node;

And the input end of the sixth NAND gate is respectively connected with the output end of the fourth AND gate and the output end of the fifth AND gate, and the output end of the sixth NAND gate is used as the second node.

20. The column control circuit of claim 18, wherein said second gating circuit includes at least two of said second gating cells, and each of said second gating cells is connected to a different one of said output nodes; the second gating circuit further includes:

and the input end of the second OR gate is connected with each second node, and the output end of the second OR gate is connected with the second output end.

21. A memory device, comprising:

the memory bank comprises a plurality of memory bank groups, wherein each memory bank group comprises a plurality of memory cell arrays, each memory cell array comprises a plurality of memory cells, and each memory cell array is connected with a plurality of column selection switch tubes;

the column control circuit of any one of claims 1-20, the column select switch being turned on in response to the corresponding target column select start signal and turned off in response to the target column select end signal.