CN116028992B - SoC chip and method for realizing data security detection thereof - Google Patents
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Abstract
The application discloses a SoC chip and a method for realizing data security detection, wherein the hardware initial value generated by the SoC chip is random and indefinite when the SoC chip is electrified and initialized each time, that is, the SoC chip provided by the embodiment of the application generates a specific security identifier by utilizing the hardware characteristic, and the hardware characteristic is a hardware basis for realizing a PUF, so that the SoC chip provided by the embodiment of the application becomes a security chip with the PUF, and the security of the SoC chip is ensured by checking the hardware initial value and the stored security identifier generated when the SoC chip is electrified and initialized each time after the SoC chip is electrified and initialized, and the security of the SoC chip is ensured safely, stably and reliably.
Description
Technical Field
The present application relates to, but not limited to, hardware security technologies, and in particular, to a SoC chip and a method for implementing data security detection.
Background
With the rapid development of integrated circuit technology, the functions of circuits in a chip are more and more complex, and the functions integrated in a single chip are more and more, so as to adapt to the requirements of the complexity of a chip system, the chip design has been developed from a single large-scale integrated circuit to the systemization of multifunctional IP integration. Among them, a System on Chip (SoC) is a major solution to replace a conventional integrated circuit, and has become a necessary trend in the current microelectronic Chip technology development.
The SoC chip contains the complete system and has the entire contents of the embedded software. In the working process of the SoC chip, starting safety is the guarantee of all subsequent safety mechanisms, and if the safety of the SoC chip has loopholes, serious safety problems can be generated. In the related art, the security of SoC chips is based on a cryptographic algorithm to perform data security detection, including a symmetric algorithm, a hash algorithm, a public key algorithm, and the like. However, these algorithms have a common problem that they cannot cope with the risk of leakage of the corresponding key.
Therefore, a more secure, stable and reliable data security detection method is needed to ensure the security of the SoC chip.
Disclosure of Invention
The application provides an SoC chip and a method for realizing data security detection thereof, which can safely, stably and reliably ensure the security of the SoC chip.
The embodiment of the invention provides an SoC chip, which comprises: the control unit is embedded with a logic processing unit of the RAM unit and the Flash unit; wherein,
The logic processing unit is used for generating a second hardware initial value by the RAM unit when the RAM unit is powered on for initialization; the Flash unit stores a first numerical value serving as a security identifier of a system-on-chip (SoC) system so that the SoC chip becomes a security chip with a Physical Unclonable Function (PUF);
The control unit is used for reading the first numerical value from the Flash unit and reading the second hardware initial value from the RAM unit every time the SoC system is started; and carrying out security verification according to the read first numerical value and the second hardware initial value, if the verification is passed, the SoC chip is safe and usable, and if the verification is not passed, the SoC chip is unsafe.
In an exemplary example, the logic processing unit is further to:
At power-on initialization, the RAM unit generates a first hardware initial value; storing the first numerical value from the control unit in the Flash unit; in response to this, the control unit,
The control unit is further configured to:
And reading a first hardware initial value from the RAM unit, converting the read first hardware initial value into the first numerical value, and writing the first numerical value into the Flash unit as a security identifier of the SoC system.
In an exemplary embodiment, converting the read first hardware initial value into the first numerical value in the control unit includes:
and converting the first hardware initial value into the first numerical value of 1KB through a preset calculation mode.
In an exemplary embodiment, the security verification in the control unit according to the read first value and the second hardware initial value includes:
converting the second hardware initial value into a second numerical value according to a preset calculation mode;
Comparing the first value with the second value, and if the first value and the second value are consistent, indicating that the verification is passed, enabling the SoC chip to be safe and usable; if the two are inconsistent, the verification is not passed, and the SoC chip is not safe.
In one illustrative example, the control unit includes a micro control unit MCU.
In one illustrative example, the logic processing unit includes a field programmable gate array FPGA unit.
The embodiment of the application also provides a method for realizing data security detection, which comprises the following steps:
in the starting of the SoC system, the SoC chip reads a first numerical value serving as a security identifier of the SoC system from a Flash unit embedded in a logic processing unit of the SoC chip, and reads a second hardware initial value from a RAM unit embedded in the logic processing unit of the SoC chip; when the second hardware initial value is generated by a RAM unit embedded in the logic processing unit during power-on initialization;
and the SoC chip performs security verification according to the read first numerical value and the second hardware initial value, if the verification is passed, the SoC chip is safe and usable, and if the verification is not passed, the SoC chip is unsafe.
In an exemplary embodiment, the method further comprises:
The RAM unit generates a first hardware initial value when the SoC chip is powered on and initialized; the SoC chip reads a first hardware initial value from the RAM unit and converts the read first hardware initial value into the first numerical value;
And taking the first numerical value as a security identifier of the SoC system and writing the first numerical value into the Flash unit so that the SoC chip becomes a security chip with a PUF.
In one illustrative example, the converting the read first hardware initial value to a first numerical value includes:
and converting the first hardware initial value into the first numerical value of 1KB through a preset calculation mode.
In an exemplary embodiment, the security verification according to the read first value and the second hardware initial value includes:
converting the second hardware initial value into a second numerical value according to a preset calculation mode;
Comparing the first value with the second value, and if the first value and the second value are consistent, indicating that the verification is passed, enabling the SoC chip to be safe and usable; if the two are inconsistent, the verification is not passed, and the SoC chip is not safe.
Embodiments of the present application further provide a computer-readable storage medium storing computer-executable instructions for performing the method for implementing data security detection described in any one of the above.
The embodiment of the application further provides a device for realizing data security detection, which comprises a memory and a processor, wherein the memory stores the following instructions executable by the processor: a step for performing the method of implementing data security detection of any of the above.
The SoC chip provided by the embodiment of the application comprises the control unit, and the logic processing unit embedded with the RAM unit and the Flash unit, wherein the hardware initial value generated by the RAM unit embedded with the logic processing unit is random and indefinite when the SoC chip is initialized during power-on every time, that is, the SoC chip provided by the embodiment of the application utilizes the hardware characteristics of the control unit and the logic processing unit to generate a specific security identifier, the security identifier is placed in the Flash unit embedded with the logic processing unit, the hardware characteristic of the hardware initial value in the embodiment of the application is a hardware basis for realizing PUF, so that the SoC chip provided by the embodiment of the application becomes a security chip with PUF, and the security of the SoC chip is ensured by checking the hardware initial value generated during power-on initialization of the SoC and the security identifier stored in the Flash unit after each power-on initialization of the SoC chip.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
Fig. 1 is a schematic diagram of a composition structure of an SoC chip in an embodiment of the present application;
fig. 2 is a flow chart of a method for implementing data security detection in an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be arbitrarily combined with each other.
In one typical configuration of the application, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer readable media, as defined herein, does not include non-transitory computer readable media (transmission media), such as modulated data signals and carrier waves.
The steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.
The physical unclonable function (PUF, PHYSICALLY UNCLONABLE FUNCTIONS) is a hardware security technology that can provide all functions from improved cryptography to IC counterfeiting. PUFs use inherent device variations to produce unclonable unique device responses for a given input. Based on the PUF, the inventor provides an SoC chip with the PUF, which can safely, stably and reliably guarantee the safety of the SoC chip.
Fig. 1 is a schematic diagram of a composition structure of an SoC chip in an embodiment of the present application, where, as shown in fig. 1, the SoC chip at least includes: a control unit, a logic processing unit embedded with a Random Access Memory (RAM) unit and a Flash memory (Flash) unit; wherein,
The logic processing unit is used for generating a second hardware initial value by the RAM unit embedded in the logic processing unit when the power-on initialization is performed; the Flash unit embedded in the logic processing unit stores a first numerical value serving as a security identifier of the SoC system, so that the SoC chip to which the logic processing belongs becomes a security chip with a PUF.
The control unit is used for reading a first numerical value serving as a security identifier of the SoC system from a Flash unit embedded in the logic processing unit every time the SoC system is started, reading a second hardware initial value from a RAM unit embedded in the logic processing unit, performing security verification according to the read first numerical value serving as the security identifier of the SoC system and the second hardware initial value, if the verification is passed, the SoC chip which the control unit belongs to is safe and available, and if the verification is not passed, the SoC chip which the control unit belongs to is unsafe.
In one illustrative example, the logic processing unit is further to:
When power-on initialization is performed, a RAM unit embedded in a logic processing unit generates a first hardware initial value; storing a first value which is taken as a security identifier of the SoC system from the control unit into an embedded Flash unit so that the SoC chip to which the logic processing belongs becomes a security chip with a PUF;
Correspondingly, the control unit is further configured to:
and reading the first hardware initial value from the RAM unit embedded in the logic processing unit, converting the read first hardware initial value into a first numerical value, taking the first numerical value as a security identifier of the SoC system, and writing the first numerical value into the Flash unit embedded in the logic processing unit.
In one illustrative example, the control unit may include, but is not limited to, a micro control unit (MCU, microcontroller Unit), for example. The MCU is essentially a single chip microcomputer, which means a chip-level computer formed by integrating CPU, RAM, ROM, a timing counter and various I/O interfaces of the computer on a chip.
In one illustrative example, the logic processing unit may include, but is not limited to, a Field-Programmable gate array (FPGA) unit. FPGAs are a further development product based on PAL, GAL, CPLD and other programmable devices. FPGA is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuit number of the original programmable device.
In one illustrative example, a first value that is a security identification of the SoC system may be stored at a preset address location in a Flash unit embedded in the FPGA unit.
In an exemplary embodiment, the control unit may read the hardware initial value from a preset address in a RAM unit embedded in the logic processing unit.
In an exemplary embodiment, converting the read first hardware initial value into the first numerical value in the control unit may include: and converting the read first hardware initial value into a first value of 1KB by a preset calculation mode, wherein the first value is used as a security identifier of the SoC system.
In an exemplary embodiment, the security verification performed by the control unit according to the read first value and the second hardware initial value as the security identifier of the SoC system may include:
According to a preset calculation mode, the read second hardware initial value is converted into a second numerical value, for example: converting the second hardware initial value into a second numerical value of 1KB according to a calculation mode in the power-on initialization;
comparing the first value and the second value which are used as the security identification of the SoC system, and if the first value and the second value are consistent, indicating that the verification is passed, then the control unit belongs to the SoC chip and is safe and available; if the two are inconsistent, the verification is not passed, the SoC chip to which the control unit belongs is not safe, for example, the SoC chip to which the control unit belongs may be modified or destroyed.
In one embodiment, comparing the first value and the second value as the security identification of the SoC system may include: and performing exclusive OR operation on each bit of the first value and the second value, and then performing OR operation sequentially, wherein if the operation result is 0, the first value and the second value which are used as the safety identification of the SoC system are consistent, and if the operation result is 1, the first value and the second value which are used as the safety identification of the SoC system are inconsistent. Such as: the first value is: 111000, the second value is: 111000, then, the following operation (1^1) | (1^1) | (1^1) | (0^0) | (0^0) | (0^0) =0, and the result is 0, which indicates that the first value and the second value are consistent, and the SoC chip is safe.
For example, when the SoC chip is powered up initially, the RAM unit will generate an initial value randomly, and special attention should be paid here to the fact that if the RAM unit is the same RAM unit, the initial value is constant every time the RAM unit is powered up, but the initial value is random for different RAM units after the RAM unit is powered up, for example: the initial value of the RAM of the chip 1 is 011100000111100, and the value is obtained after each power-on; the initial value of the RAM of chip 2 is 111100000111100, which is also this value each time after power-up. The randomness of the RAM initial values means that the RAM of the chip 1 and the RAM of the chip 2 are different, and the different RAM initial values are random, so that the chip 1 and the chip 2 are random and different. That is, for the same SoC chip, the value written into the Flash unit is compared with the initial value of the RAM after each power-up, and if the values are consistent, it is indicated that the PUF value in the Flash unit is of the SoC chip, the SoC chip is safely usable, and the PUF value is also safely usable.
The hardware initial value generated by the RAM unit embedded in the logic processing unit is random when the SoC chip is initialized during power-on every time, that is, the SoC chip provided by the embodiment of the application generates a specific safety mark by utilizing the hardware characteristics of the control unit and the logic processing unit, the safety mark is placed in the Flash unit embedded in the logic processing unit, the hardware characteristic reflected by the hardware initial value in the embodiment of the application is a hardware basis for realizing the PUF, so that the SoC chip provided by the embodiment of the application becomes a safety chip with the PUF, and the safety of the SoC chip is ensured by checking the hardware initial value generated during the power-on initialization of the SoC chip and the safety mark stored in the Flash unit after the power-on every time.
Fig. 2 is a flow chart of a method for implementing data security detection in an embodiment of the present application, including:
Step 200: in the starting of the SoC system, the SoC chip reads a first numerical value serving as a security identifier of the SoC system from a Flash unit embedded in a logic processing unit of the SoC chip, and reads a second hardware initial value from a RAM unit embedded in the logic processing unit of the SoC chip. Wherein, when the second hardware initial value is power-on initialization, the RAM unit embedded in the logic processing unit generates.
In an illustrative example, this step may further include:
When the SoC chip is electrified and initialized, a RAM unit embedded in a logic processing unit of the SoC chip generates a first hardware initial value; and reading a first hardware initial value from the RAM unit embedded in the logic processing unit, converting the read hardware initial value into a first numerical value, and writing the first numerical value serving as a security identifier of the SoC system into the Flash unit embedded in the logic processing unit so as to enable the SoC chip to which the logic processing belongs to become a security chip with a PUF.
In one illustrative example, a first value that is a security identification of the SoC system may be stored at a preset address location in a Flash unit embedded in the FPGA unit.
In an exemplary embodiment, the SoC chip may read the hardware initial value from a preset address in a RAM unit embedded in the logic processing unit.
In one embodiment, converting the read first hardware initial value to a first numerical value may include, for example: and converting the read first hardware initial value into a first value of 1KB by a preset calculation mode, wherein the first value is used as a security identifier of the SoC system.
Step 201: and the SoC chip performs security verification according to the read first numerical value and the second hardware initial value, if the verification is passed, the SoC chip is safe and usable, and if the verification is not passed, the SoC chip is unsafe.
In one illustrative example, step 201 may include:
According to a preset calculation mode, converting the read second hardware initial value into a second numerical value, and in one embodiment, for example, converting the second hardware initial value into a second numerical value of 1 KB;
Comparing the first value and the second value which are used as the security identification of the SoC system, and if the first value and the second value are consistent, indicating that the verification is passed, the SoC chip is safe and usable; if the two are inconsistent, the verification is not passed, the SoC chip is not safe, for example, the SoC chip to which the control unit belongs may be modified or destroyed.
According to the method for realizing data security detection, the hardware initial value generated by the RAM unit embedded in the logic processing unit is random and indefinite when the SoC chip is initialized during power-on every time, namely, the SoC chip provided by the embodiment of the application utilizes the hardware characteristics of the control unit and the logic processing unit to generate a specific security identifier, the security identifier is placed in the Flash unit embedded in the logic processing unit, the hardware characteristic reflected by the hardware initial value in the embodiment of the application is a hardware basis for realizing PUF, so that the SoC chip provided by the embodiment of the application becomes a security chip with a PUF, and therefore, the security of the SoC chip is ensured by checking the hardware initial value generated during power-on initialization of the SoC chip and the security identifier stored in the Flash unit after each power-on initialization of the SoC chip.
The present application also provides a computer readable storage medium storing computer executable instructions for performing the method of implementing data security detection as described in any one of fig. 2.
The application further provides a device for realizing data security detection, which comprises a memory and a processor, wherein the memory stores the following instructions executable by the processor: for performing the steps of the method of implementing data security detection described in any of fig. 2.
Although the embodiments of the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.
Claims (8)
1. A SoC chip, comprising: the control unit is embedded with a logic processing unit of the RAM unit and the Flash unit; wherein,
The logic processing unit is used for: at power-on initialization, the RAM unit generates a first hardware initial value; storing a first numerical value from the control unit in the Flash unit; accordingly, the control unit is configured to: reading a first hardware initial value from the RAM unit, converting the read first hardware initial value into the first numerical value, and writing the first numerical value into the Flash unit as a security identifier of the SoC system;
The logic processing unit is further configured to generate a second hardware initial value by the RAM unit when the SOC system is started and initialized every time; the Flash unit stores a first numerical value serving as a security identifier of a system-on-chip (SoC) system so that the SoC chip becomes a security chip with a Physical Unclonable Function (PUF);
The control unit is further configured to read the first value from the Flash unit and read the second hardware initial value from the RAM unit every time the SoC system is started; converting the second hardware initial value into a second numerical value according to a preset calculation mode; comparing the first value with the second value, and if the first value and the second value are consistent, indicating that the verification is passed, enabling the SoC chip to be safe and usable; if the two are inconsistent, indicating that the verification is not passed, the SoC chip is unsafe;
the initial values of the same RAM unit after power-on are fixed, and the initial values of the different RAM units after power-on are random.
2. The SoC chip of claim 1, wherein converting the read first hardware initial value to the first value in the control unit comprises:
and converting the first hardware initial value into the first numerical value of 1KB through a preset calculation mode.
3. The SoC chip of claim 1, wherein the control unit comprises a micro control unit MCU.
4. The SoC chip of claim 1, wherein the logic processing unit comprises a field programmable gate array FPGA unit.
5. A method of implementing data security detection, comprising:
When the SoC chip is powered on and initialized, a first hardware initial value is generated from a RAM unit embedded in a logic processing unit of the SoC chip; the SoC chip reads a first hardware initial value from the RAM unit and converts the read first hardware initial value into a first numerical value; the first numerical value is used as a security identifier of the SoC system and is written into a Flash unit embedded in a logic processing unit of the SoC chip, so that the SoC chip becomes a security chip with a PUF;
The SoC chip reads the first numerical value serving as a security identifier of the SoC system from the Flash unit and reads a second hardware initial value from the RAM unit in the starting process of the SoC system; wherein, when the second hardware initial value is initialized when the SOC system is started and electrified, the RAM unit generates the second hardware initial value;
The SoC chip converts the second hardware initial value into a second numerical value according to a preset calculation mode; comparing the first value with the second value, and if the first value and the second value are consistent, indicating that the verification is passed, enabling the SoC chip to be safe and usable; if the two are inconsistent, indicating that the verification is not passed, the SoC chip is unsafe;
the initial values of the same RAM unit after power-on are fixed, and the initial values of the different RAM units after power-on are random.
6. The method of claim 5, wherein the converting the read first hardware initial value to a first numerical value comprises:
and converting the first hardware initial value into the first numerical value of 1KB through a preset calculation mode.
7. A computer-readable storage medium storing computer-executable instructions for performing the method of implementing data security detection of any one of claims 5-6.
8. An apparatus for implementing data security detection, comprising a memory and a processor, wherein the memory has stored therein instructions executable by the processor to: a method for performing the method for implementing data security detection of any one of claims 5 to 6.
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