CN116028422A - Heterogeneous multi-core system, inter-core communication method thereof, chip and storage medium - Google Patents
Heterogeneous multi-core system, inter-core communication method thereof, chip and storage medium Download PDFInfo
- Publication number
- CN116028422A CN116028422A CN202310107157.3A CN202310107157A CN116028422A CN 116028422 A CN116028422 A CN 116028422A CN 202310107157 A CN202310107157 A CN 202310107157A CN 116028422 A CN116028422 A CN 116028422A
- Authority
- CN
- China
- Prior art keywords
- core
- real
- time message
- time
- message area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Multi Processors (AREA)
Abstract
The embodiment of the invention provides a heterogeneous multi-core system, an inter-core communication method, a chip and a storage medium thereof, belonging to the technical field of embedding. The heterogeneous multi-core system includes a sending core, a receiving core, and at least one memory block associated between the sending core and the receiving core, wherein the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and the inter-core communication method includes, for the sending core: generating and sending an interrupt notification to the receiving core in real-time in response to the real-time message being stored in the real-time message area; and generating and sending an interrupt notification to the receiving core based on the storage status of the non-real-time message area in response to the non-real-time message being stored in the non-real-time message area. The inter-core communication method can carry out classification processing according to the real-time property of the messages, can respond to the messages with high real-time property in real time, and can avoid frequent processing operation and reduce the burden of a CPU (central processing unit) for the delayed processing of the messages with low real-time property.
Description
Technical Field
The invention relates to the technical field of embedded technology, in particular to a heterogeneous multi-core system, an inter-core communication method, a chip and a storage medium thereof.
Background
The heterogeneous multi-core system comprises a main core and a secondary core, wherein the main core runs a Linux system, the secondary core runs a bare metal program or a real-time operating system (Real Time Operating System, RTOS) so as to realize synchronous collaboration and efficient communication among different systems and exert the performance of the multi-core processor. The inter-core communication mode in the existing Asymmetric Multiprocessing (AMP) mode is often implemented based on a shared memory. By opening up a section of shared memory in the memory, a plurality of core systems can perform read-write access on data of the shared memory based on direct memory access (Direct Memory Access, DMA). For example, the master core system writes data into the shared memory and generates an interrupt re-notification so that the slave core system can read the written data based on the interrupt notification, thereby realizing inter-core communication. Therefore, when the inter-core communication technology based on the shared memory is used for communication at present, because the transmission strategy for data is single, when a large amount of data communication occurs, particularly when data with low real-time requirements is transmitted, interruption is continuously carried out to inform a receiver to process the data, and the frequent interruption and frequent data communication can generate a larger burden on the system, so that the performance of the whole system is greatly influenced.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a heterogeneous multi-core system, and an inter-core communication method, a chip and a storage medium thereof, for at least partially solving the above-mentioned existing technical problems.
To achieve the above object, in a first aspect, an embodiment of the present invention provides an inter-core communication method of a heterogeneous multi-core system, the heterogeneous multi-core system including a transmitting core, a receiving core, and at least one memory block associated between the transmitting core and the receiving core, wherein the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and the inter-core communication method includes for the transmitting core: generating and sending an interrupt notification to the receiving core in real-time in response to the real-time message being stored in the real-time message area; and generating and sending an interrupt notification to the receiving core based on a storage state of the non-real-time message area in response to the non-real-time message being stored in the non-real-time message area.
Optionally, the inter-core communication method further includes, for the receiving core: and responding to the interrupt notification sent by the sending core, and reading the corresponding message from the real-time message area or the non-real-time message area.
Optionally, for the sending core, the real-time message is written to the real-time message area based on a direct memory access DMA.
Optionally, the generating and sending an interrupt notification to the receiving core based on the storage status of the non-real-time message area includes: and if the storage state of the non-real-time message area is a full state, generating and sending the interrupt notification to the receiving core in real time.
Optionally, the generating and sending an interrupt notification to the receiving core based on the storage status of the non-real-time message area includes: and if the storage state of the non-real-time message area is an underfull state, generating in a delayed manner based on the expiration state of a preset timer and sending the interrupt notification to the receiving core.
Optionally, the inter-core communication method further includes: and for the memory block, the capacity sizes of the real-time message area and the non-real-time message area are configured differently according to whether the sending core is a master core or a slave core.
Optionally, if the sending core is the main core, the memory block is configured such that the capacity of the real-time message area is greater than the capacity of the non-real-time message area.
Optionally, if the sending core is a slave core, the memory block is configured to have a capacity of the real-time message area smaller than a capacity of the non-real-time message area.
Optionally, when the at least one memory block includes a first memory block and a second memory block, and the sending core and the receiving core are configured in a master-slave relationship, the inter-core communication method further includes: configuring main cores in the sending core and the receiving core to have read-write permission for the first memory block and read permission for the second memory block; and configuring the slave cores in the sending core and the receiving core to have read-write permission for the second memory block and read permission for the first memory block.
In a second aspect, an embodiment of the present invention provides a heterogeneous multi-core system including a sending core, a receiving core, and at least one memory block associated with storage between the sending core and the receiving core, wherein the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and the sending core is configured to: generating and sending an interrupt notification to the receiving core in real-time in response to the real-time message being stored in the real-time message area; and generating and sending an interrupt notification to the receiving core based on a storage state of the non-real-time message area in response to the non-real-time message being stored in the non-real-time message area.
Optionally, the receiving core is configured to: and responding to the interrupt notification sent by the sending core to read the corresponding message from the real-time message area or the non-real-time message area.
In a third aspect, an embodiment of the present invention provides a processor chip, where the processor chip includes the heterogeneous multi-core system described in the second aspect.
In a fourth aspect, an embodiment of the present invention provides a machine-readable storage medium having stored thereon instructions for causing a machine to perform the inter-core communication method according to any one of the first aspects.
Through the technical scheme, the inter-core communication method provided by the embodiment of the invention can be used for carrying out classification processing according to the real-time property of the messages, so that the instant response to the messages with high real-time property is improved, meanwhile, the messages with low real-time property are processed based on the storage state, frequent processing operation is avoided, the burden of a multi-core chip is reduced, and the overall transmission performance of inter-core communication is improved.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating an internuclear communication mechanism of a heterogeneous multi-core system, according to an example embodiment;
FIG. 2 is a schematic diagram illustrating an internuclear communication mechanism of a heterogeneous multi-core system, according to an example embodiment;
FIG. 3 is a flow diagram illustrating an inter-core communication method of a heterogeneous multi-core system, according to an example embodiment;
FIG. 4 is a diagram illustrating an internuclear communication mechanism of another heterogeneous multi-core system, according to an example embodiment.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Before describing the present invention, first, an explanation is given of an inter-core communication mechanism in an AMP mode according to an embodiment of the present invention.
AMP refers to the fact that a plurality of CPU cores of a multi-core chip run different tasks, and each CPU core is independent and isolated and can run different systems or bare computer programs. Of course, if different systems are operated, the use or access of the relative system resources must be mutually exclusive, so that the systems can operate in parallel without interference. Although the systems in AMP mode operate independently without interference, in an actual application scenario, a plurality of CPU cores are often required to communicate with each other to achieve the purpose of mutually coordinated operation, so that an inter-core communication technology is very important. Fig. 1 is a schematic diagram of an internuclear communication mechanism in AMP mode. As shown in fig. 1, the master core system and the slave core system implement data transmission communication based on the shared memory. When the master core system transmits data to the slave core system, the master core system writes the transmitted data into the shared memory and notifies the slave core system so that the slave core system can read the written data from the shared memory. Similarly, when the slave core system transmits data to the master core system, the slave core system writes the transmitted data into the shared memory and notifies the master core system so that the master core system reads the written data from the shared memory. However, when communication is performed by the current inter-core communication technology based on the shared memory, for example, when the master core system needs to transmit a large amount of data to the slave core system, the slave core needs to be continuously notified to process the data, and such frequent communication greatly affects the performance of the entire system, and thus, a load is imposed on the CPU.
In view of this, an embodiment of the present invention provides an inter-core communication method, which classifies transmitted messages and adopts different message transmission modes according to different real-time properties of the messages. Specifically, fig. 2 is a schematic diagram of a heterogeneous multi-core system, as shown in fig. 2, where the heterogeneous multi-core system includes a sending core, a receiving core, and at least one memory block associated between the sending core and the receiving core, where the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and for the sending core, as shown in fig. 3, the inter-core communication method includes:
step S110, generating and sending an interrupt notification to the receiving core in response to the real-time message being stored in the real-time message area.
Step S120, in response to the non-real-time message being stored in the non-real-time message area, generating and transmitting an interrupt notification to the receiving core based on the storage status of the non-real-time message area.
For example, the embodiment of the invention divides the messages into real-time messages and non-real-time messages based on the real-time nature of the messages. The real-time message refers to data that needs to be transmitted and responded quickly and immediately. Such as video data, audio data, data collected by sensors, the open and closed state of the switch, etc. Non-real-time messages refer to data that does not require immediate fast transmission and response. Such as log-like data information generated during operation of some systems, etc. Furthermore, the memory blocks are divided into different message areas in advance according to different instantaneity of the messages. Wherein the real-time message area may store real-time messages and the non-real-time message area may store non-real-time messages.
Further, based on the pre-divided message area, the sending core firstly judges the real-time property of the message when sending the message, namely, the message is a real-time message or a non-real-time message, and then writes the message into the corresponding message area based on the judging result. Since the real-time message needs to respond quickly and immediately, the sending core needs to notify the receiving core of the real-time message immediately, so that the receiving core can respond quickly and immediately to execute corresponding operation processing on the real-time message.
According to the embodiment of the invention, the messages are classified according to the instantaneity, the instant response of the system to the messages with high instantaneity requirements is improved, and meanwhile, the messages with low instantaneity requirements are processed based on the storage state, so that the load of a CPU (central processing unit) can be reduced, and the transmission performance of the system is improved.
In a preferred embodiment, the inter-core communication method further comprises, for the receiving core: and responding to the interrupt notification sent by the sending core, and reading the corresponding message from the real-time message area or the non-real-time message area.
For example, the notification sent by the sending core to the receiving core may include the location where the message was stored, i.e., the address where the message was stored in the real-time message area or the non-real-time message area. Further, when the receiving core receives the notification, the message can be read from the real-time message area or the non-real-time message area according to the address of the message storage contained therein, so that a corresponding operation can be performed based on the content of the message.
In a preferred embodiment, the real-time message is written to the real-time message area or the non-real-time message is written to the non-real-time message area based on direct memory access (Direct Memory Access, DMA) for the sending core.
For example, DMA technology refers to a high-speed data transfer operation that allows data to be read and written directly between an external device and a memory, neither by a CPU nor without requiring CPU intervention. Generally, the data of the peripheral is read into the memory or transferred to the peripheral through the control of the CPU, such as the inquiry or interrupt of the CPU program, and the DMA technology is used for data transfer, so that the occupation of CPU resources can be greatly reduced. Thus, embodiments of the present invention write a message to a corresponding message area based on DMA technology and read the message from the corresponding message area based on DMA technology.
In a preferred embodiment, the generating and sending an interrupt notification to the receiving core based on the storage status of the non-real time message area comprises: and if the storage state of the non-real-time message area is a full state, generating and sending the interrupt notification to the receiving core in real time.
For example, an interrupt refers to any unusual or unexpected urgent processing event occurring in the system during the running of the program by the CPU, so that the CPU temporarily interrupts the currently executing program and goes to execute the corresponding time processing program, and returns to the original interrupted position after the processing is completed, and continues to execute or schedule the new process to execute. The utilization rate of the CPU can be greatly improved by utilizing the interrupt technology. Therefore, when the real-time information is stored in the real-time information area, an interrupt notification which needs to be processed by the receiving core is generated, and the sending core immediately sends the generated interrupt notification to the receiving core.
For the non-real-time information, when the non-real-time information area is in a full state, the non-real-time information area indicates that the sending core cannot write when the sending core needs to write the non-real-time information again. Therefore, for the non-real-time message area to be in a full state, in the embodiment of the invention, the sending core needs to immediately send an interrupt notification to the receiving core, so that the receiving core can immediately read the stored batch of non-real-time messages from the non-real-time message area to release the storage space of the non-real-time message area, and further, the sending core can conveniently write the non-real-time message into the non-real-time message area when the sending core needs to send the non-real-time message subsequently.
In another preferred embodiment, the generating and transmitting an interrupt notification to the receiving core based on the storage status of the non-real-time message area includes: and if the storage state of the non-real-time message area is an underfull state, generating in a delayed manner based on the expiration state of a preset timer and sending the interrupt notification to the receiving core.
For example, when the non-real-time message area is in an unfilled state, the embodiment of the invention adopts a timer timing mode to determine whether there is newly added non-real-time message writing in the preset time counted by the timer. The preset time can be flexibly set, for example, 30 seconds. If no new message is written, the sending core sends an interrupt notification generated by the timer to the receiving core, so that the receiving core can conveniently read the batch of non-real-time messages stored in the non-real-time message area, and the problem that message data cannot be effectively processed due to overlong delay processing time of the non-real-time messages is avoided. When the newly added non-real-time information is written in the preset time, the timer restarts to count, and the operation is repeated.
Therefore, for the non-real-time message, the sending core sends the corresponding interrupt notification to the receiving core only if no newly added non-real-time message is written in within the preset time counted by the timer or when the non-real-time message area is full.
According to the embodiment, for the non-real-time information, the non-real-time information is delayed by judging the storage state of the non-real-time information area, and the non-real-time information of the non-real-time information area is processed in one batch, so that on one hand, the storage space of the non-real-time information area is released, on the other hand, the interruption times are reduced, the frequency of processing the information is reduced, and the burden of a CPU and a system caused by excessive interruption operations is avoided.
In a preferred embodiment, since the memory blocks in the present invention are preconfigured with different message areas, in order to further improve the storage and communication performance, the inter-core communication method further includes: and for the memory block, the capacity sizes of the real-time message area and the non-real-time message area are configured differently according to whether the sending core is a master core or a slave core.
For example, in the embodiment of the present invention, the capacity sizes of the real-time message area and the non-real-time message area are configured according to the respective functional attributes of the master core or the slave core.
Preferably, if the sending core is the main core, the memory block is configured such that the capacity of the real-time message area is greater than the capacity of the non-real-time message area.
Preferably, if the sending core is a slave core, the memory block is configured such that the capacity of the real-time message area is smaller than the capacity of the non-real-time message area.
For example, in a heterogeneous multi-core system, there are many more real-time messages transmitted by a master core to a slave core, and many non-real-time messages transmitted by a slave core to the master core in response to the real-time messages of the master core. Thus, embodiments of the present invention configure the capacity of the message area in the memory block based on the attributes of the sending core. For example, if the sending core is the main core, the real-time message area and the non-real-time message area in the memory block may be divided into 2MB and 1MB, respectively. The above configuration is only an example, and those skilled in the art can flexibly configure the capacity of the message area in the memory block according to the actual use situation of the system.
In a preferred embodiment, when the at least one memory block includes a first memory block and a second memory block, and the sending core and the receiving core are configured in a master-slave relationship, the inter-core communication method further includes: configuring main cores in the sending core and the receiving core to have read-write permission for the first memory block and read permission for the second memory block; and configuring the slave cores in the sending core and the receiving core to have read-write permission for the second memory block and read permission for the first memory block.
For example, as shown in fig. 4, the heterogeneous multi-core system includes a master core system and a slave core system, and sets a first memory block and a second memory block based on the master core system and the slave core system. The master core system sends a message to the slave core system based on the first memory block, so that the master core system has write and read rights to the first memory block and the slave core system has only read rights to the first memory block. The slave core system sends a message to the master core system based on the second memory block, so that the slave core system has write and read rights to the second memory block and the master core system has only read rights to the second memory block.
In the embodiment of the invention, corresponding memory blocks are configured for different cores in the heterogeneous multi-core system, and write-in and read-out authorities of the memory blocks are configured for different cores, so that the inter-core communication efficiency of the heterogeneous multi-core system is effectively improved.
It should be noted that, in the above embodiments, the heterogeneous multi-core system is taken as a dual-core example, but the number of cores in the heterogeneous multi-core system in the present application is not limited to dual-core, and any heterogeneous multi-core system with the number of cores may use the inter-core communication method, which is not described herein in detail.
The transmission of the above-described real-time and non-real-time messages is described in further detail below in more specific embodiments.
(1) For the transmission process of the real-time information, the display of the control graphical interface of the master core system is taken as an example to display real-time data, and the application scenario that the slave core system monitors partial sensor data and switch data is illustrated. When a certain sensor data or switch state is suddenly changed, the slave core system is required to transmit data to the master core in real time at the moment so as to synchronize the graphical interface display of the master core system. That is, the slave is regarded as a transmitting core, the master is regarded as a receiving core, and the slave determines that the sensor data or the switch state is a real-time message and writes the message into the real-time message area. After writing the message into the real-time message area, the slave core transmits an interrupt notification to the master core, and the master core reads the message written by the slave core from the real-time message area according to the interrupt notification. Thus, the data or the on-off state of a certain sensor is obtained, and the obtained data is updated on the graphical interface.
(2) For the transmission process of the non-real-time message, the transmitted message is taken as log data as an example. In heterogeneous multi-core systems, it is also extremely important to monitor the state of the slave core system during operation. However, the slave core system is often not provided with a file system, and the log file cannot be recorded directly, and the log file can be recorded only by the master core system. Because the log information has larger data and low real-time requirement, the embodiment of the invention can utilize the processing flow of the non-real-time information. The slave core is taken as a sending core, the master core is taken as a receiving core, when the slave core needs to transmit the data representing the running state to the master core, the storage state of the non-real-time message area is judged first, and if the storage state is full, the master core is informed to read the log data in the non-real-time message area. If the storage state is not full, starting a timer, further judging whether newly added log data is stored in a non-real-time message area in a preset time, and further realizing delay notification of a master check log for reading. Furthermore, the master core reads the log data of the non-real-time message area at one time according to the notification sent by the slave core, records the read log data into the file system, and independently stores the read log data as the running log of the slave core, so that the running condition of the slave core system is convenient to inquire and manage.
Accordingly, an embodiment of the present invention provides a heterogeneous multi-core system, the heterogeneous multi-core system including a sending core, a receiving core, and at least one memory block associated between the sending core and the receiving core, wherein the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and the sending core is configured to: generating and sending an interrupt notification to the receiving core in real-time in response to the real-time message being stored in the real-time message area; and generating and sending an interrupt notification to the receiving core based on a storage state of the non-real-time message area in response to the non-real-time message being stored in the non-real-time message area.
In a preferred embodiment, the receiving core is configured to: and responding to the interrupt notification sent by the sending core to read the corresponding message from the real-time message area or the non-real-time message area.
For advantages and descriptions of inter-core communication in heterogeneous multi-core systems, reference may be made to the above embodiments, and redundant descriptions are omitted herein.
Correspondingly, the embodiment of the invention provides a processor chip, which comprises the heterogeneous multi-core system.
Accordingly, an embodiment of the present invention provides a machine-readable storage medium having stored thereon instructions for causing a machine to perform the inter-core communication method of any of the above embodiments.
In summary, the heterogeneous multi-core inter-core communication method provided by the invention has the following advantages:
1) The sent messages are classified according to real-time performance, messages with different real-time performance are processed differently, and a message processing mode is more flexible; 2) Real-time information is processed in real time, so that the real-time response of the system to the information with high real-time performance is improved; the non-real-time messages are processed in one batch, so that frequent operation is reduced, and the burden of a CPU and a system is reduced; 3) And the DMA mode is adopted to carry out inter-core data transmission, so that the resource utilization rate of a CPU is reduced, and the real-time performance of the system is improved.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (13)
1. An inter-core communication method of a heterogeneous multi-core system, the heterogeneous multi-core system comprising a sending core, a receiving core, and at least one memory block associated between the sending core and the receiving core, wherein the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and the inter-core communication method comprises for the sending core:
generating and sending an interrupt notification to the receiving core in real-time in response to the real-time message being stored in the real-time message area; and
in response to the non-real-time message being stored in the non-real-time message area, an interrupt notification is generated and sent to the receiving core based on the storage status of the non-real-time message area.
2. The inter-core communication method of claim 1, further comprising, for the receiving core:
and responding to the interrupt notification sent by the sending core, and reading the corresponding message from the real-time message area or the non-real-time message area.
3. The method of inter-core communication according to claim 1, wherein,
for the sending core, writing the real-time message to the real-time message area or writing the non-real-time message to the non-real-time message area based on Direct Memory Access (DMA).
4. The inter-core communication method according to claim 1, wherein the generating and transmitting an interrupt notification to the receiving core based on the storage state of the non-real-time message area comprises:
and if the storage state of the non-real-time message area is a full state, generating and sending the interrupt notification to the receiving core in real time.
5. The inter-core communication method according to claim 1, wherein the generating and transmitting an interrupt notification to the receiving core based on the storage state of the non-real-time message area comprises:
and if the storage state of the non-real-time message area is an underfull state, generating in a delayed manner based on the expiration state of a preset timer and sending the interrupt notification to the receiving core.
6. The inter-core communication method according to claim 1, further comprising:
and for the memory block, the capacity sizes of the real-time message area and the non-real-time message area are configured differently according to whether the sending core is a master core or a slave core.
7. The method of inter-core communication according to claim 6, wherein if the sending core is a master core, the memory block is configured such that the capacity of the real-time message area is greater than the capacity of the non-real-time message area.
8. The method of inter-core communication according to claim 6, wherein if the sending core is a slave core, the memory block is configured such that the capacity of the real-time message area is smaller than the capacity of the non-real-time message area.
9. The inter-core communication method of claim 1, wherein when the at least one memory block includes a first memory block and a second memory block, and the sending core and the receiving core are configured in a master-slave relationship, the inter-core communication method further comprises:
configuring main cores in the sending core and the receiving core to have read-write permission for the first memory block and read permission for the second memory block;
and configuring the slave cores in the sending core and the receiving core to have read-write permission for the second memory block and read permission for the first memory block.
10. A heterogeneous multi-core system comprising a sending core, a receiving core, and at least one memory block associated between the sending core and the receiving core, wherein the memory block is configured with a real-time message area for storing real-time messages and a non-real-time message area for storing non-real-time messages, and:
the sending core is configured to: generating and sending an interrupt notification to the receiving core in real-time in response to the real-time message being stored in the real-time message area; and generating and sending an interrupt notification to the receiving core based on a storage state of the non-real-time message area in response to the non-real-time message being stored in the non-real-time message area.
11. The heterogeneous multi-core system of claim 10, wherein the receiving core is configured to: and responding to the interrupt notification sent by the sending core to read the corresponding message from the real-time message area or the non-real-time message area.
12. A processor chip, characterized in that it comprises a heterogeneous multi-core system according to any of the preceding claims 10 or 11.
13. A machine-readable storage medium having stored thereon instructions for causing a machine to perform the inter-core communication method of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310107157.3A CN116028422A (en) | 2023-02-14 | 2023-02-14 | Heterogeneous multi-core system, inter-core communication method thereof, chip and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310107157.3A CN116028422A (en) | 2023-02-14 | 2023-02-14 | Heterogeneous multi-core system, inter-core communication method thereof, chip and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116028422A true CN116028422A (en) | 2023-04-28 |
Family
ID=86091387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310107157.3A Pending CN116028422A (en) | 2023-02-14 | 2023-02-14 | Heterogeneous multi-core system, inter-core communication method thereof, chip and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116028422A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103942178A (en) * | 2014-03-03 | 2014-07-23 | 浙江大学 | Communication method between real-time operating system and non-real-time operating system on multi-core processor |
| CN107357666A (en) * | 2017-06-26 | 2017-11-17 | 西安微电子技术研究所 | A kind of multi-core parallel concurrent system processing method based on hardware protection |
| DE102017117912A1 (en) * | 2016-08-18 | 2018-02-22 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Send messages to an unavailable device |
| CN115481072A (en) * | 2022-08-01 | 2022-12-16 | 北京智芯微电子科技有限公司 | Inter-core data transmission method, multi-core chip and machine-readable storage medium |
-
2023
- 2023-02-14 CN CN202310107157.3A patent/CN116028422A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103942178A (en) * | 2014-03-03 | 2014-07-23 | 浙江大学 | Communication method between real-time operating system and non-real-time operating system on multi-core processor |
| DE102017117912A1 (en) * | 2016-08-18 | 2018-02-22 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Send messages to an unavailable device |
| CN107357666A (en) * | 2017-06-26 | 2017-11-17 | 西安微电子技术研究所 | A kind of multi-core parallel concurrent system processing method based on hardware protection |
| CN115481072A (en) * | 2022-08-01 | 2022-12-16 | 北京智芯微电子科技有限公司 | Inter-core data transmission method, multi-core chip and machine-readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10649953B2 (en) | Blockchain-based data migration method and apparatus | |
| CN110019514B (en) | Data synchronization method and device and electronic equipment | |
| US20220283953A1 (en) | Method and system for low latency data management | |
| EP3489815B1 (en) | Method and system for low latency data management | |
| CN107783842B (en) | Distributed lock implementation method, device and storage device | |
| CN107818012B (en) | Data processing method and device and electronic equipment | |
| CN110971430A (en) | Automatic capacity expansion and reduction control method and device, storage medium and processor | |
| CN113760559A (en) | Dual-core communication method and electronic equipment | |
| CN114327930A (en) | System architecture for communication between heterogeneous multi-core and operation method of system architecture | |
| WO2024088268A1 (en) | Rdma event management methods, and device and storage medium | |
| CN113535425A (en) | Data sending method and device, electronic equipment and storage medium | |
| CN111338769B (en) | Data processing method, device and computer readable storage medium | |
| CN113296931A (en) | Resource control method, system, computing device and storage medium | |
| CN116028422A (en) | Heterogeneous multi-core system, inter-core communication method thereof, chip and storage medium | |
| CN110895517B (en) | Method, equipment and system for transmitting data based on FPGA | |
| CN109684051B (en) | Method and system for asynchronously submitting hybrid big data task | |
| JPH08221372A (en) | Free resource management device in distributed processing system | |
| CN116302605A (en) | Message engine-based message transmission method | |
| CN100576175C (en) | The parallel executing method and the system that are used for a plurality of kernels | |
| CN106997304B (en) | Input and output event processing method and device | |
| CN114296891A (en) | Task scheduling method, system, computing device, storage medium and program product | |
| CN111435320B (en) | Data processing method and device | |
| CN110928944B (en) | Data processing method and device | |
| CN113971085A (en) | Method, device, system and storage medium for distinguishing processing tasks by master core and slave core | |
| CN111404709B (en) | Method and device for operating policy rules under network function virtualization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |