CN114327930A - System architecture for communication between heterogeneous multi-core and operation method of system architecture - Google Patents
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Abstract
The embodiment of the invention provides a system architecture for communication among heterogeneous multi-core cores and an operation method of the system architecture, belonging to the technical field of chips. The system architecture for communication among heterogeneous multi-core processors is designed based on a remote processor Remoteproc framework, and comprises: the first processor system comprises a first control device and a first operating system module; a second processor system comprising a second control device, a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component, the second processor system being configured to control the first processor system to run through the Remoteproc and the AMP communication software component. The Linux Remoteproc framework is expanded by configuring an asymmetric multiprocessor AMP communication software component on the second processor system, so that the high-efficiency work of communication among heterogeneous multi-core cores is achieved, and the cooperative processing among the heterogeneous cores is completed.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a system architecture for communication among heterogeneous multi-core cores and an operation method of the system architecture.
Background
With the development of advanced semiconductor technology and Microprocessor technology, a plurality of Chip heterogeneous multicore (Soc) chips have appeared, in which a high-performance Microprocessor (MPU) and a Microcontroller (MCU) with high real-time performance are integrated, which are heterogeneous multicore socs. On a heterogeneous multi-core Soc, an MPU can run embedded operating system software to support various communication modes, graphics and image display; the MCU runs an embedded real-time operating system or bare computer program software to realize real-time system control and signal processing, realizes parallel running of various operating systems and various applications on different processor cores, and can realize partition isolation and synchronous cooperation among the operating systems. In order to realize synchronous cooperative work among heterogeneous multi-cores, software support realization of communication among the heterogeneous multi-cores is required to achieve efficient work among the heterogeneous multi-cores and complete cooperative processing among the heterogeneous cores.
Remote Processor Messaging (Rpmsg) is a mechanism that provides Inter-Process Communication (IPC) functionality between a kernel driver of a host operating system (e.g., Linux) and a Remote Processor. A remote processor (Remoteproc) framework allows different platforms/architectures to control while abstracting hardware differences and therefore does not require duplication of operations. In addition, the framework adds the virtio device of Rpmsg to a remote processor that supports such communications. It is only necessary to provide some low-level remote processor operating method to the Remoteproc driver and then all Rpmsg drivers can function. However, the existing Remoteproc framework provides an infrastructure with some limitations to influence communication between heterogeneous multi-core cores.
Disclosure of Invention
The embodiment of the invention aims to provide a method for communication among heterogeneous multi-core cores, which can realize high-efficiency communication among the heterogeneous multi-core cores.
In order to achieve the above object, an embodiment of the present invention provides a system architecture for communication between heterogeneous multi-core cores, where the system architecture for communication between heterogeneous multi-core cores is designed based on a remote processor Remoteproc framework, and the system architecture for communication between heterogeneous multi-core cores includes: the first processor system comprises a first control device and a first operating system module; a second processor system comprising a second control device, a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component, the second processor system being configured to control the first processor system to run the first processor system through the Remoteproc and the AMP communication software component.
Optionally, the first processor system further includes a first upper module, and the second processor system further includes a second upper module.
Optionally, the second upper layer module communicates with the first upper layer module through a remote processor messaging Rpmsg mechanism.
Optionally, the second operating system module includes a Bare Metal and/or an embedded real-time operating system RTOS.
Optionally, the physical layer of the AMP communication software component is configured to: taking charge of data receiving and sending and an inter-core interrupt mechanism through a hardware mechanism Mailbox and a device driver thereof; setting a small memory block without occupying the main memory of the second processor system; and allowing access by different processors through the protection of a synchronous mutual exclusion mechanism.
Optionally, the medium access layer of the AMP communication software component is configured to: analyzing a message format, wherein the message format comprises a message header and a message body, and the message header information comprises the length of the message and the check of data in the message; and performing buffering management on the message through the transceiving buffer area.
Optionally, the transport layer of the AMP communication software component is configured to: and setting an API (application program interface) of the Rpmsg standard protocol, and shielding interfaces of the physical layer and the media access layer.
An embodiment of the present invention further provides an operation method of a system architecture for communication between heterogeneous multi-core devices, where in any of the above system architectures for communication between heterogeneous multi-core devices, the operation method of the system architecture for communication between heterogeneous multi-core devices includes: the second control device starts a second operating system module, wherein the second operating system module is also configured with an asymmetric multiprocessor AMP communication software component; and the second control device controls the first control device through the Remoteproc and the AMP communication software component.
Optionally, the method for operating the system architecture for communication between heterogeneous multi-core devices further includes: the first control device operates according to the control of the Remoteproc and the AMP communication software component;
the first control device controls the first operating system module to operate.
Optionally, the first processor system further includes a first upper module, the second processor system further includes a second upper module, and the operating method of the system architecture for communication among heterogeneous multi-core further includes: the second upper module communicates with the first upper module via a remote processor messaging (Rpmsg) mechanism.
Through the technical scheme, the Linux Remoteproc framework is expanded by configuring the asymmetric multiprocessor AMP communication software component on the second processor system, so that the high-efficiency work of communication among heterogeneous multi-core cores is achieved, and the cooperative processing among the heterogeneous cores is completed.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic diagram of an exemplary structure of heterogeneous multi-core software;
FIG. 2 is a schematic diagram of an example remote processor messaging;
FIG. 3 is a schematic diagram of a system architecture for communication between heterogeneous multi-core devices according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an example architecture of a system architecture for communication between heterogeneous multi-core devices, according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating an operation method of a system architecture for communication between heterogeneous multi-core devices according to an embodiment of the present invention.
Description of the reference numerals
10 first processor system 20 second processor system
11 first control device 21 second control device
12 first operating system module 22 second operating system module
13 first upper module 23 second upper module
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Before explaining the embodiments of the present invention in detail, the prior art, the drawbacks of the prior art, and the design idea of the embodiments of the present application will be briefly described.
On a System On Chip (Soc), a Microprocessor (MPU) may run embedded operating System (e.g., Linux) software to support various communication technologies and graphic and image display; a Microcontroller (MCU) runs an embedded Real-Time Operating System (Real Time Operating System) or Bare Metal program (barrel Metal) software to realize Real-Time System control and signal processing, realize parallel running of various Operating systems and various applications on different processor cores, and realize partition isolation and synchronous cooperation among the Operating systems. In order to realize synchronous cooperative work among heterogeneous multi-core cores, software support realization of communication among the heterogeneous multi-core cores is required to achieve efficient work among the heterogeneous multi-core cores and complete cooperative processing among the heterogeneous cores. An exemplary structural schematic diagram of heterogeneous multi-core software is shown in fig. 1.
Remote Processor Messaging (Rpmsg) is a mechanism that provides Inter-Process Communication (IPC) functionality between a kernel driver of a host operating system (e.g., Linux) and a Remote Processor. A remote processor (Remoteproc) framework allows different platforms/architectures to control while abstracting hardware differences and therefore does not require duplication of operations. In addition, the framework adds the virtio device of Rpmsg to a remote processor that supports such communications. It is only necessary to provide some low-level remote processor operating method to the Remoteproc driver and then all Rpmsg drivers can function. A schematic diagram of an example of the Rpmsg is shown in fig. 2.
However, the existing Remoteproc framework provides an infrastructure with some limitations. Taking the Linux Remoteproc framework as an example, Linux is always implicitly assumed to be the primary operating system and is not supported as a remote operating system configured in an Asymmetric Multi-Processing (AMP) system. Furthermore, Linux kernel space is only available from Rpmsg, and there are no equivalent APIs or libraries for other operating systems and runtimes.
Fig. 3 is a schematic structural diagram of a system architecture for communication between heterogeneous multi-core devices according to an embodiment of the present invention, and fig. 4 is an exemplary structural diagram. Referring to fig. 3 and 4, the system architecture for communication between heterogeneous multi-core processors is designed based on a remote processor Remoteproc framework, and includes: a first processor system (e.g., Master)10 including a first control device (e.g., Core1 MPU)11, a first operating system module (e.g., Linux) 12; a second processor system (e.g. Remote)20 comprising a second control means (e.g. Core2 MCU)21, a second operating system module 22, wherein said second operating system module 22 is further configured with an asymmetric multiprocessor AMP communication software component, said second processor system 20 being configured to control said first processor system to run the first processor system via said Remote and said AMP communication software components.
Wherein, the first control device 11 may include: a memory, a processor, and a computer program stored on the memory and executable on the processor.
The second control device 21 may include: a memory, a processor, and a computer program stored on the memory and executable on the processor.
Preferably, the second operating system module comprises a Bare Metal and/or an embedded real-time operating system RTOS.
As shown in fig. 4, the system architecture for communication between heterogeneous multi-core cores according to the embodiment of the present invention may extend the Linux Remoteproc framework by configuring an asymmetric multiprocessor AMP communication software component on a Remote, so as to control a second processor system without using a first processor system (e.g., a Master) as a main system. For example, the first control device can be controlled by the second control device to realize Linux which can open, load firmware and close Master by a Bare Metal of Remote and/or an embedded real-time operating system RTOS.
Furthermore, the Remoteproc base framework provides a way of controlling a second control device (e.g. the Core2 MCU) via a first control device (e.g. the Core1 MPU), in fact bi-directional control between the Master and the Remote processor may be achieved by embodiments of the present invention.
The embodiment of the invention preferably provides a set of application program service architecture on the basis of the AMP communication software group, and the AMP communication software group is used for carrying out functional design on the three-layer communication service of the bottom layer.
Preferably, the physical layer of the AMP communication software component may be configured to: taking charge of data receiving and sending and an inter-core interrupt mechanism through a hardware mechanism Mailbox and a device driver thereof; setting a small memory block without occupying the main memory of the second processor system; and allowing access by different processors through the protection of a synchronous mutual exclusion mechanism.
Mailbox is used as a hardware mechanism for process synchronization and data exchange among processors in a multiprocessor system, and has the advantages of wide application and high speed. The Mailbox mode is mainly used for multiprocessor communication through a mode of transmitting control information.
By way of example, the Mailbox hardware and the device driver thereof are responsible for the most basic data transceiving and inter-Core interrupt mechanism, and the Mailbox device has a small memory and can realize a data transmission function without occupying a system main memory, and the Mailbox device can allow different processors (cores) to access under the protection of a synchronous mutual exclusion mechanism, write or read a message to the Mailbox unit, and then send interrupt information to the Core using the message, and the corresponding Core uses the Core under the protection of the synchronous mutual exclusion mechanism to read the message.
Preferably, the medium access layer of the AMP communication software component may be configured to: analyzing a message format, wherein the message format comprises a message header and a message body, and the message header information comprises the length of the message and the check of data in the message; and performing buffering management on the message through the transceiving buffer area.
By way of illustration, the media access layer primary functions include: message format analysis, transmit-receive buffer management and the like. The message format is composed of two parts of message header information and message body, and the message header information contains the length of the message and the check of the data in the message body so as to ensure that no error occurs when the message is output. The receiving and sending buffer zone realizes the buffer management of the message, ensures the reliable transmission of the message, and realizes the retransmission of the message when the transmission error is found. The maximum transmission capacity of the medium access layer is to deduct a plurality of bytes of the message header on the basis of the physical layer.
Preferably, the transport layer of the AMP communication software component may be configured to: and setting an API (application program interface) of the Rpmsg standard protocol, and shielding interfaces of the physical layer and the media access layer.
By way of example, the transport layer mainly provides an API standard interface of an Rpmsg standard protocol, and shields interfaces of a media access layer and a physical layer, so that the framework is easy to use.
Preferably, the first processor system 10 further comprises a first upper module 13, and the second processor system 20 further comprises a second upper module 23.
Further preferably, the second upper layer module 23 communicates with the first upper layer module 13 through a remote processor messaging Rpmsg mechanism.
Fig. 5 is a flowchart illustrating an operation method of a system architecture for communication between heterogeneous multi-core devices according to an embodiment of the present invention, referring to fig. 4 and fig. 5, in the above system architecture for communication between heterogeneous multi-core devices, the operation method of the system architecture for communication between heterogeneous multi-core devices may include the following steps:
step S110: the second control means launches a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component.
By way of example, the Linux Remoteproc framework may be extended by configuring a heterogeneous multi-core AMP communication software component on the Remote to implement control of the second processor system without using the first processor system (e.g., Master) as the main system. For example, the Core2 MCU may directly first control the launching of the second operating system module 22.
Step S120: and the second control device controls the first control device through the Remoteproc and the AMP communication software component.
The first control device may remotely control the second control device through the Remoteproc and the AMP communication software component to control the first operating system module (e.g., Linux) to operate. For example, the first control device can be controlled by the second control device to realize Linux of opening, loading firmware and closing Master by RTOS or Bar Metal of Remote.
Preferably, the method for operating the system architecture for communication between heterogeneous multi-core devices further includes: the first control device operates according to the control of the Remoteproc and the AMP communication software component; the first control device controls the first operating system module to operate.
As described in steps S110-S120, the Core2 MCU may be first started to start the RTOS or barrel Metal, then run the Core1 MPU via the Remoteproc and AMP communication software component of the second processor system, and run Linux via the Core1 MPU, i.e., running Linux, e.g., turning on, loading firmware, turning off Linux, via the RTOS or barrel Metal.
Preferably, the first processor system further includes a first upper module, the second processor system further includes a second upper module, and the method for operating the system architecture for communication among heterogeneous multi-core further includes: the second upper module communicates with the first upper module via a remote processor messaging (Rpmsg) mechanism.
It should be noted that, for the functional design of the AMP communication software group on the bottom layer three-layer communication service, please refer to the foregoing contents, which are not described herein again.
Therefore, the Linux Remoteproc framework is expanded by configuring a heterogeneous multi-core AMP communication software component on the Remote, so that the high-efficiency work of communication among heterogeneous multi-core cores is achieved, and the cooperative processing among the heterogeneous cores is completed. Meanwhile, the heterogeneous multi-core AMP communication software component is operated and used on host equipment, can realize life cycle management of a remote processor and related software environments thereof, can realize clock control of the remote processor, realizes starting of the remote processor, closes the remote processor when the remote processor needs to be closed after a task is completed, achieves reduction of system power consumption, loads a program applied by the remote processor to a proper position of a memory by the main processor, completes registration of virtio and Rpmsg equipment and other functions, and realizes a channel of IPC communication of the multi-core processor.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A system architecture for communication between heterogeneous multi-core systems, wherein the system architecture for communication between heterogeneous multi-core systems is based on a remote processor Remoteproc framework design, and wherein the system architecture for communication between heterogeneous multi-core systems comprises:
the first processor system comprises a first control device and a first operating system module;
a second processor system comprising a second control device, a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component, the second processor system being configured to control the first processor system to run the first processor system through the Remoteproc and the AMP communication software component.
2. The system architecture for communication between heterogeneous multi-core systems of claim 1, wherein the first processor system further comprises a first upper layer module and the second processor system further comprises a second upper layer module.
3. The system architecture for communication among heterogeneous multi-core cores of claim 2, wherein the second upper module communicates with the first upper module through a remote processor messaging (Rpmsg) mechanism.
4. The system architecture for inter-heterogeneous multi-core communication of claim 1, wherein the second operating system module comprises a Bare Metal and/or an embedded real-time operating system (RTOS).
5. The system architecture for communication between heterogeneous multi-core cores of claim 4, wherein a physical layer of the AMP communication software component is configured to:
taking charge of data receiving and sending and an inter-core interrupt mechanism through a hardware mechanism Mailbox and a device driver thereof;
setting a small memory block without occupying the main memory of the second processor system; and
the access by different processors is allowed by the protection of the synchronous mutual exclusion mechanism.
6. The system architecture for communication between heterogeneous multi-core networks according to claim 5, wherein the medium access layer of the AMP communication software component is configured to:
analyzing a message format, wherein the message format comprises a message header and a message body, and the message header information comprises the length of the message and the check of data in the message; and
and carrying out buffering management on the message through the transceiving buffer area.
7. The system architecture for communication between heterogeneous multi-core cores of claim 6, wherein a transport layer of the AMP communication software component is configured to:
and setting an API (application program interface) of the Rpmsg standard protocol, and shielding interfaces of the physical layer and the media access layer.
8. An operation method of a system architecture for communication between heterogeneous multi-core networks, in the system architecture for communication between heterogeneous multi-core networks of any one of claims 1 to 7, the operation method of the system architecture for communication between heterogeneous multi-core networks comprises:
the second control device starts a second operating system module, wherein the second operating system module is also configured with an asymmetric multiprocessor AMP communication software component; and
and the second control device controls the first control device through the Remoteproc and the AMP communication software component.
9. The method of claim 8, wherein the method further comprises:
the first control device operates according to the control of the Remoteproc and the AMP communication software component;
the first control device controls the first operating system module to operate.
10. The method of claim 8, wherein the first processor system further comprises a first upper layer module, the second processor system further comprises a second upper layer module, and the method further comprises:
the second upper module communicates with the first upper module via a remote processor messaging (Rpmsg) mechanism.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115098430A (en) * | 2022-06-27 | 2022-09-23 | 西安电子科技大学 | Inter-core communication priority scheduling method based on AMP architecture |
| CN115098436A (en) * | 2022-08-24 | 2022-09-23 | 北京智芯微电子科技有限公司 | Multi-core SoC and relay protection method and system |
| CN115657879A (en) * | 2022-12-09 | 2023-01-31 | 北京小米移动软件有限公司 | Input control method, device, equipment and medium based on heterogeneous operating system |
| CN115904295A (en) * | 2023-02-21 | 2023-04-04 | 南京芯驰半导体科技有限公司 | Multi-screen display control method, device, medium, system, chip and panel |
| CN117215992A (en) * | 2023-11-09 | 2023-12-12 | 芯原科技(上海)有限公司 | Heterogeneous core processor, heterogeneous processor and power management method |
| CN117370262A (en) * | 2023-08-31 | 2024-01-09 | 华为技术有限公司 | Communication method, device, chip system and electronic equipment |
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| CN115098430A (en) * | 2022-06-27 | 2022-09-23 | 西安电子科技大学 | Inter-core communication priority scheduling method based on AMP architecture |
| CN115098430B (en) * | 2022-06-27 | 2024-03-19 | 西安电子科技大学 | Inter-core communication priority scheduling method based on AMP architecture |
| CN115098436A (en) * | 2022-08-24 | 2022-09-23 | 北京智芯微电子科技有限公司 | Multi-core SoC and relay protection method and system |
| CN115657879A (en) * | 2022-12-09 | 2023-01-31 | 北京小米移动软件有限公司 | Input control method, device, equipment and medium based on heterogeneous operating system |
| CN115657879B (en) * | 2022-12-09 | 2023-04-07 | 北京小米移动软件有限公司 | Input control method, device, equipment and medium based on heterogeneous operating system |
| CN115904295A (en) * | 2023-02-21 | 2023-04-04 | 南京芯驰半导体科技有限公司 | Multi-screen display control method, device, medium, system, chip and panel |
| CN117370262A (en) * | 2023-08-31 | 2024-01-09 | 华为技术有限公司 | Communication method, device, chip system and electronic equipment |
| CN117215992A (en) * | 2023-11-09 | 2023-12-12 | 芯原科技(上海)有限公司 | Heterogeneous core processor, heterogeneous processor and power management method |
| CN117215992B (en) * | 2023-11-09 | 2024-01-30 | 芯原科技(上海)有限公司 | Heterogeneous core processor, heterogeneous processor and power management method |
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