CN114327930A - System architecture and operating method of system architecture for heterogeneous multi-core inter-core communication - Google Patents

Abstract

Embodiments of the present invention provide a system architecture for heterogeneous multi-core inter-core communication and a method for operating the system architecture, which belong to the technical field of chips. The system architecture for communication between heterogeneous multi-core cores is designed based on the Remoteproc framework of the remote processor, and the system architecture for communication between heterogeneous multi-core cores includes: a first processor system, including a first control device, a third an operating system module; a second processor system including a second control device and a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component, the second processing system The processor system is used to control the operation of the first processor system through the Remoteproc and the AMP communication software component. The Linux Remoteproc framework is extended by configuring an asymmetric multi-processor AMP communication software component on the second processor system, so as to achieve efficient work of communication between heterogeneous multi-core cores and complete heterogeneous inter-core collaborative processing.

Description

System architecture and operating method of system architecture for heterogeneous multi-core inter-core communication

technical field

The present invention relates to the field of chip technology, in particular to a system architecture for communication between heterogeneous multi-core cores and an operation method of the system architecture.

Background technique

With the development of advanced semiconductor technology and microprocessor technology, a variety of heterogeneous multi-core (System On Chip, Soc) chips have appeared, which integrate high-performance microprocessor (Microprocessor Unit, MPU) and Strong real-time microcontroller (Microcontroller Unit, MCU), which is both heterogeneous multi-core Soc. On a heterogeneous multi-core SoC, MPU can run embedded operating system software to support various communication methods and graphics and image display; MCU runs embedded real-time operating system or bare metal program software to realize real-time system control and signals It can realize multiple operating systems and multiple applications running in parallel on different processor cores, and can realize partition isolation and synchronization between operating systems. In order to realize synchronous and cooperative work among heterogeneous multi-cores, software support for communication between heterogeneous multi-cores is required, so as to achieve efficient work among heterogeneous multi-cores and complete cooperative processing among heterogeneous multi-cores.

Remote Processor Messaging (Rpmsg) is a mechanism that provides a communication (Inter-Process Communication, IPC) function between a kernel driver of a main operating system (eg, Linux) and a remote processor. The Remoteproc framework allows different platforms/architectures to be controlled, while abstracting hardware differences so there is no need for duplication of operations. Additionally, the framework adds Rpmsg's virtio device to remote processors that support this type of communication. Just provide some low-level remote handler operation methods to the Remoteproc driver, and then all the Rpmsg drivers will work. However, the existing Remoteproc framework provides some limitations in the infrastructure to affect the heterogeneous multi-core inter-core communication.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present invention is to provide a method for communication between heterogeneous multi-core cores, and the method for communication between heterogeneous multi-core cores can realize efficient communication between heterogeneous multi-core cores.

In order to achieve the above object, an embodiment of the present invention provides a system architecture for communication between heterogeneous multi-core cores, wherein the system architecture for communication between heterogeneous multi-core cores is designed based on a remote processor Remoteproc framework, and The system architecture for communication between heterogeneous multi-cores includes: a first processor system including a first control device and a first operating system module; a second processor system including a second control device and a second operating system module , wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component, and the second processor system is configured to control the first processing through the Remoteproc and the AMP communication software component The processor system runs the first processor system.

Optionally, the first processor system further includes a first upper layer module, and the second processor system further includes a second upper layer module.

Optionally, the second upper-layer module communicates with the first upper-layer module through a remote processor message passing Rpmsg mechanism.

Optionally, the second operating system module includes bare metal Bare Metal and/or an embedded real-time operating system RTOS.

Optionally, the physical layer of the AMP communication software component is configured to: be responsible for data sending and receiving and inter-core interrupt mechanism through the hardware mechanism Mailbox and its device driver; set a small block of memory, which does not occupy the second processor system. main memory; and protected by a synchronous mutual exclusion mechanism, allowing access by different processors.

Optionally, the media access layer of the AMP communication software component is configured to: parse the message format, where the message format includes a message header and a message body, and the message header information includes the length of the message and the content of the data in the message. Checksum; and buffer management of messages through sending and receiving buffers.

Optionally, the transport layer of the AMP communication software component is configured to: set the API interface of the Rpmsg standard protocol, and shield the interface of the physical layer and the media access layer.

An embodiment of the present invention further provides a method for operating a system architecture for communication between heterogeneous multi-core cores. The operating method of the system architecture for inter-communication includes: the second control device starts a second operating system module, wherein the second operating system module is further configured with an asymmetric multi-processor AMP communication software component; and the second control device The device controls the first control device through the Remoteproc and the AMP communication software component.

Optionally, the method for operating the system architecture for heterogeneous multi-core inter-core communication further includes: the first control device operates according to the control of the Remoteproc and the AMP communication software component;

The first control device controls the operation of the first operating system module.

Optionally, the first processor system further includes a first upper layer module, the second processor system further includes a second upper layer module, and the method for operating the system architecture for communication between heterogeneous multi-core cores further includes: the second The upper-layer module communicates with the first upper-layer module through the remote processor message passing Rpmsg mechanism.

Through the above technical solutions, the embodiment of the present invention expands the Linux Remoteproc framework by configuring an asymmetric multi-processor AMP communication software component on the second processor system, so as to achieve efficient work of communication between heterogeneous multi-core cores and complete heterogeneous core co-processing.

Other features and advantages of embodiments of the present invention will be described in detail in the detailed description section that follows.

Description of drawings

The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and are used to explain the embodiments of the present invention together with the following specific embodiments, but do not constitute limitations to the embodiments of the present invention. In the attached image:

Figure 1 is a schematic structural diagram of an example of heterogeneous multi-core software;

2 is a schematic diagram of a remote processor message passing example;

3 is a schematic structural diagram of a system architecture for communication between heterogeneous multi-core cores provided by an embodiment of the present invention;

4 is a schematic structural diagram of an example structure of a system architecture for heterogeneous multi-core inter-core communication provided by an embodiment of the present invention;

FIG. 5 is a schematic flowchart of a method for running a system architecture for heterogeneous multi-core inter-core communication according to an embodiment of the present invention.

Description of reference numerals

10First processor system 20Second processor system

11 The first control device 21 The second control device

12 The first operating system module 22 The second operating system module

13 The first upper module 23 The second upper module

Detailed ways

The specific implementations of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific implementation manners described herein are only used to illustrate and explain the embodiments of the present invention, and are not used to limit the embodiments of the present invention.

Before explaining the embodiments of the present invention in detail, the prior art, the defects of the prior art, and the design ideas of the embodiments of the present application are briefly introduced.

On heterogeneous multi-core (System On Chip, Soc), the microprocessor (Microprocessor Unit, MPU) can run embedded operating system (for example, Linux) software to support a variety of communication technologies and graphics, image display; microcontroller ( Microcontroller Unit, MCU) runs embedded real-time operating system (Real Time Operating System) or runs bare metal program (Bare Metal) software to realize real-time system control and signal processing, and realize multiple operating systems and multiple applications on different processor cores It runs in parallel, and can achieve partition isolation and synchronization between operating systems. In order to realize synchronous and cooperative work among heterogeneous multi-core cores, software support for communication between heterogeneous multi-core cores is required, so as to achieve efficient work among heterogeneous multi-core cores and complete heterogeneous inter-core collaborative processing. A schematic diagram of the example structure of heterogeneous multi-core software is shown in Figure 1.

Remote Processor Messaging (Rpmsg) is a mechanism that provides a communication (Inter-Process Communication, IPC) function between a kernel driver of a main operating system (eg, Linux) and a remote processor. The Remoteproc framework allows different platforms/architectures to be controlled, while abstracting hardware differences so there is no need for duplication of operations. Additionally, the framework adds Rpmsg's virtio device to remote processors that support this type of communication. Just provide some low-level remote handler operation methods to the Remoteproc driver, and then all the Rpmsg drivers will work. A schematic diagram of the Rpmsg example is shown in Figure 2.

But the existing Remoteproc framework provides some limitations in the infrastructure. Taking the Linux Remoteproc framework as an example, Linux is always implicitly assumed to be the primary operating system, and Linux is not supported as a remote operating system configured in an Asymmetric Multi-Processing (AMP) system. Also, Linux kernel space is only available from Rpmsg, and there are no equivalent APIs or libraries for other operating systems and runtimes.

FIG. 3 is a schematic structural diagram of a system architecture for communication between heterogeneous multi-cores according to an embodiment of the present invention, and FIG. 4 is a schematic structural diagram of an example. Please refer to FIG. 3 and FIG. 4 , the system architecture for communication between heterogeneous multi-core cores is designed based on the remote processor Remoteproc framework, and the system architecture for communication between heterogeneous multi-core cores includes: a first processor system ( For example, Master) 10, including a first control device (eg, Core1 MPU) 11, a first operating system module (eg, Linux) 12; a second processor system (eg, Remote) 20, including a second control device (eg, , Core2 MCU) 21, a second operating system module 22, wherein the second operating system module 22 is also configured with an asymmetric multi-processor AMP communication software component, and the second processor system 20 is used to pass the Remoteproc communicating with the AMP software component to control the first processor system to run the first processor system.

The first control device 11 may include: a memory, a processor, and a computer program stored on the memory and running on the processor.

The second control device 21 may include a memory, a processor, and a computer program stored on the memory and executable on the processor.

Preferably, the second operating system module includes bare metal Bare Metal and/or an embedded real-time operating system RTOS.

As shown in FIG. 4 , the system architecture for heterogeneous multi-core inter-core communication provided by the embodiment of the present invention can extend the Linux Remoteproc framework by configuring an asymmetric multi-processor AMP communication software component on the Remote, so as to achieve no first The processor system (eg Master) is the master system to control the second processor system. For example, the first control device can be controlled by the second control device, so as to realize Linux that can be opened, loaded with firmware, and closed of the Master through the bare metal Bare Metal of the Remote and/or the embedded real-time operating system RTOS.

Furthermore, the Remoteproc basic framework provides a way to control a second control device (eg, Core2 MCU) through a first control device (eg, Core1 MPU), and in fact, through the embodiment of the present invention, bidirectional communication between the Master and the Remote processor can be implemented. control.

Wherein, the AMP communication software group mainly provides the bottom layer three communication service, and the embodiment of the present invention preferably provides a set of application program service architecture on this basis, and performs functional design for the bottom layer three communication service.

Preferably, the physical layer of the AMP communication software component can be configured to: be responsible for data transmission and reception and inter-core interrupt mechanism through the hardware mechanism Mailbox and its device driver; set up a small block of memory, which does not occupy the second processor system. main memory; and protected by a synchronous mutual exclusion mechanism, allowing access by different processors.

As a hardware mechanism for process synchronization and data exchange between processors in a multiprocessor system, Mailbox has the advantages of wide application and high speed. The way of using Mailbox is mainly to carry out multi-processor communication by transmitting control information.

As an example, the Mailbox hardware and its device driver are responsible for the most basic data sending and receiving and inter-core interrupt mechanisms. The Mailbox device has a small memory and can realize the data transmission function without occupying the main memory of the system. The Mailbox device can synchronize Under the protection of the mutual exclusion mechanism, different processors (Cores) are allowed to access, write or read messages to the Mailbox unit, and then send interrupt information to the Core that uses the message, and the corresponding Core uses the protection of the synchronous mutual exclusion mechanism to read messages. .

Preferably, the media access layer of the AMP communication software component can be configured to: parse the message format, wherein the message format includes a message header and a message body, and the message header information includes the length of the message and the content of the data in the message. Checksum; and buffer management of messages through sending and receiving buffers.

By way of example, the main functions of the media access layer include: message format parsing, sending and receiving buffer management and other functions. The message format is composed of two parts: message header information and message body. The message header information includes the length of the message and the verification of the data in the message body to ensure that there is no error when the message is output. The sending and receiving buffer realizes the buffer management of the message, ensures the reliable transmission of the message, and can realize the retransmission of the message when the transmission error is found. The maximum transmission capacity of the media access layer is a number of bytes in the header of the message packet deducted from the physical layer.

Preferably, the transport layer of the AMP communication software component may be configured to: set the API interface of the Rpmsg standard protocol, and shield the interface of the physical layer and the media access layer.

As an example, the transport layer mainly provides the API standard interface of the Rpmsg standard protocol, and shields the interface of the media access layer and the physical layer, making the architecture easier to use.

Preferably, the first processor system 10 further includes a first upper layer module 13 , and the second processor system 20 further includes a second upper layer module 23 .

Further preferably, the second upper layer module 23 communicates with the first upper layer module 13 through a remote processor message passing Rpmsg mechanism.

FIG. 5 is a schematic flowchart of a method for running a system architecture for heterogeneous multi-core inter-core communication provided by an embodiment of the present invention. Please refer to FIG. 4 and FIG. 5 . In the above-mentioned system architecture for heterogeneous multi-core inter-core communication, all The operating method described in the system architecture of heterogeneous multi-core inter-core communication may include the following steps:

Step S110: The second control device starts a second operating system module, wherein the second operating system module is further configured with an asymmetric multi-processor AMP communication software component.

By way of example, the Linux Remoteproc framework can be extended by configuring a heterogeneous multi-core AMP communication software component on the Remote, so as to control the second processor system without using the first processor system (eg Master) as the main system. For example, the Core2 MCU can directly control and start the second operating system module 22 first.

Step S120: The second control device controls the first control device through the Remoteproc and the AMP communication software component.

The first control device may remotely control the second control device through the Remoteproc and the AMP communication software component to control the operation of the first operating system module (eg, Linux). For example, the first control device can be controlled by the second control device, so as to realize opening, loading firmware, and closing the Linux of the Master through the RTOS or Bare Metal of the Remote.

Preferably, the method for operating the system architecture for communication between heterogeneous multi-core cores further includes: the first control device operates according to the control of the Remoteproc and the AMP communication software component; the first control device controls all The first operating system module is executed.

According to steps S110-S120, the Core2 MCU can be started first to start RTOS or Bare Metal, then run the Core1 MPU through Remoteproc and the AMP communication software component of the second processor system, and run Linux through the Core1 MPU, that is, through RTOS or Bare Metal to run Linux, e.g. turn on, load firmware, shut down Linux.

Preferably, the first processor system further includes a first upper layer module, the second processor system further includes a second upper layer module, and the method for operating the system architecture for communication between heterogeneous multi-core cores further includes: the second upper layer The module communicates with the first upper layer module through the remote processor message passing Rpmsg mechanism.

It should be noted that, for the functional design of the bottom-layer three-layer communication service by the AMP communication software group, please refer to the foregoing content, which will not be repeated here.

Accordingly, the embodiment of the present invention expands the Linux Remoteproc framework by configuring a heterogeneous multi-core AMP communication software component on the Remote, so as to achieve efficient work of communication between heterogeneous multi-core cores and complete heterogeneous inter-core collaborative processing. At the same time, the heterogeneous multi-core AMP communication software component runs on the host device, can realize the life cycle management of the remote processor and its related software environment, can realize the clock control of the remote processor, realize the start of the remote processor, and When the remote processor needs to be turned off after completing the task, the remote processor is turned off to reduce system power consumption. The main processor loads the remote processor application program to a suitable location in the memory, and completes functions such as registration of virtio and Rpmsg devices to realize multi-core processor IPC. communication channel.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block in the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a flow or flow of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions The apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the flowcharts and/or the block or blocks of the block diagrams.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include non-persistent memory in computer readable media, random access memory (RAM) and/or non-volatile memory in the form of, for example, read only memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media includes both persistent and non-permanent, removable and non-removable media, and storage of information may be implemented by any method or technology. Information may be computer readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Flash Memory or other memory technology, Compact Disc Read Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

It should also be noted that the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device comprising a series of elements includes not only those elements, but also Other elements not expressly listed, or which are inherent to such a process, method, article of manufacture, or apparatus are also included. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article of manufacture or apparatus that includes the element.

The above are merely examples of the present application, and are not intended to limit the present application. Various modifications and variations of this application are possible for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the scope of the claims of this application.

Claims (10)

1. a system architecture for heterogeneous multi-core inter-core communication, characterized in that the described system architecture for heterogeneous multi-core inter-core communication is designed based on the remote processor Remoteproc framework, and the described system for heterogeneous multi-core inter-core communication is designed The system architecture for inter-communication includes: a first processor system, including a first control device and a first operating system module; A second processor system includes a second control device and a second operating system module, wherein the second operating system module is further configured with an asymmetric multi-processor AMP communication software component, and the second processor system is configured to pass The Remoteproc and the AMP communication software components control the first processor system to run the first processor system. 2 . The system architecture for communication between heterogeneous multi-core cores according to claim 1 , wherein the first processor system further includes a first upper layer module, and the second processor system further includes a second upper layer module. 3 . 3 . The system architecture for heterogeneous multi-core inter-core communication according to claim 2 , wherein the second upper layer module communicates with the first upper layer module through a remote processor message passing Rpmsg mechanism. 4 . 4. The system architecture for heterogeneous multi-core inter-core communication according to claim 1, wherein the second operating system module comprises a bare metal Bare Metal and/or an embedded real-time operating system RTOS. 5. The system architecture for heterogeneous multi-core inter-core communication according to claim 4, wherein the physical layer of the AMP communication software component is configured as: Responsible for data sending and receiving and inter-core interrupt mechanism through the hardware mechanism Mailbox and its device driver; providing a small block of memory that does not occupy the main memory of the second processor system; and Through the protection of the synchronous mutual exclusion mechanism, different processors are allowed to access. 6. The system architecture for heterogeneous multi-core inter-core communication according to claim 5, wherein the media access layer of the AMP communication software component is configured as: Parse the message format, wherein the message format includes a message header and a message body, and the message header information includes the length of the message and the verification of the data in the message; and Buffer management of messages by sending and receiving buffers. 7. The system architecture for heterogeneous multi-core inter-core communication according to claim 6, wherein the transport layer of the AMP communication software component is configured as: The API interface of the Rpmsg standard protocol is set, and the interfaces of the physical layer and the media access layer are shielded. 8. A method for operating a system architecture for communication between heterogeneous multi-core cores, wherein in the system architecture for communication between heterogeneous multi-core cores according to any one of claims 1-7, the The operating method of the system architecture for heterogeneous multi-core inter-core communication includes: The second control device starts a second operating system module, wherein the second operating system module is further configured with an asymmetric multiprocessor AMP communication software component; and The second control device controls the first control device through the Remoteproc and the AMP communication software component. 9. The method for operating the system architecture for communication between heterogeneous multi-core cores according to claim 8, wherein the method for operating the system architecture for communication between heterogeneous multi-core cores further comprises: The first control device operates according to the control of the Remoteproc and the AMP communication software component; The first control device controls the operation of the first operating system module. 10. The method for operating a system architecture for heterogeneous multi-core inter-core communication according to claim 8, wherein the first processor system further comprises a first upper layer module, and the second processor system further comprises a second upper layer module, and the method for operating the system architecture for heterogeneous multi-core inter-core communication further includes: The second upper layer module communicates with the first upper layer module through a remote processor messaging Rpmsg mechanism.

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