CN116028402A

CN116028402A - RISC-V based control method, system, chip and storage medium

Info

Publication number: CN116028402A
Application number: CN202211743885.5A
Authority: CN
Inventors: 黄哲; 张凡; 李强; 吴喜广; 张留洋
Original assignee: Peng Cheng Laboratory
Current assignee: Peng Cheng Laboratory
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-04-28

Abstract

The invention relates to the technical field of chip control, and discloses a control method, a system, a chip and a storage medium based on RISC-V, wherein the control method based on RISC-V is applied to a control system based on RISC-V, the control system based on RISC-V comprises an instruction decoding unit, an open source instruction set RISC-V processor and an input/output port GPIO, and the method comprises the following steps: the method comprises the steps of obtaining a control instruction read in by a RISC-V processor through an instruction decoding unit, and determining a decoding instruction corresponding to the control instruction; determining direction switching information according to the decoding instruction and prestored history switching information; and determining a target processing unit corresponding to the direction switching information, and controlling the GPIO by the target processing unit according to the decoding instruction, so that the control efficiency of the input and output of the chip is improved.

Description

RISC-V based control method, system, chip and storage medium

Technical Field

The present invention relates to the field of chip control technologies, and in particular, to a control method, a system, a chip, and a storage medium based on RISC-V.

Background

With the continuous development of chip technology, chips are used more and more frequently in various fields, and the control efficiency is pursued based on the prior art, so that higher requirements are also put on the control of the input and output of the chips.

The conventional control manner of Chip input and output is that GPIO (General-purpose input/output port) is used as a slave device and connected to a SoC (System on Chip) bus in a memory mapping manner; the processor inside the chip is used as a main device to be connected to the SoC bus; the processor controls the control register in the GPIO module by sending a memory read-write command, so as to control/read the level of an IO (input/output) pin of the chip, the control mode of the input/output of the chip has great defects, the problem that the memory read-write command sent by the chip processor can reach the GPIO after passing through bus logic exists, namely the control mode of the input/output of the chip can realize the input/output after the read-write command passes through the bus logic, and the control efficiency of the input/output of the chip is low.

Disclosure of Invention

The invention mainly aims to provide a control method, a control system, a control chip and a control storage medium based on RISC-V, aiming at improving the control efficiency of chip input and output.

To achieve the above object, the present invention provides a RISC-V based control method applied to a RISC-V based control system including an instruction decoding unit, an open source instruction set RISC-V processor, and an input/output port GPIO, the RISC-V based control method comprising the steps of:

the method comprises the steps of obtaining a control instruction read in by a RISC-V processor through an instruction decoding unit, and determining a decoding instruction corresponding to the control instruction;

determining direction switching information according to the decoding instruction and prestored history switching information;

and determining a target processing unit corresponding to the direction switching information, and controlling the GPIO by the target processing unit according to the decoding instruction.

Optionally, the step of determining the direction switching information according to the decoding instruction and the pre-stored history switching information includes:

determining instruction features corresponding to the decoding instructions, and detecting whether the instruction features are matched with preset direction switching instruction features or not;

if the instruction features are not matched with the preset direction switching instruction features, determining a transmission direction corresponding to the pre-stored history switching information, and taking the transmission direction as the direction switching information.

Optionally, after the step of detecting whether the instruction feature matches a preset direction switch instruction feature, the method includes:

if the instruction features are matched with the preset direction switching instruction features, determining a direction instruction corresponding to the decoding instruction;

and controlling the GPIO to switch the direction by a direction switching unit according to the direction instruction, and executing the step of acquiring the control instruction read in by the RISC-V processor by an instruction decoding unit based on the GPIO after the direction switching.

Optionally, the RISC-V based control system includes an input processing unit and an output processing unit, and the step of determining the target processing unit corresponding to the direction switching information includes:

determining a transmission direction in the direction switching information, and detecting whether the transmission direction is matched with a preset input direction or not;

if the transmission direction is matched with a preset input direction, determining the target processing unit as an input processing unit;

and if the transmission direction is not matched with the preset input direction, determining the target processing unit as an output processing unit.

Optionally, the step of controlling, by the target processing unit, the GPIO according to the decoding instruction includes:

if the target processing unit is an input processing unit, determining a level return requirement corresponding to the decoding instruction;

and determining an input value corresponding to the original level of the GPIO input based on the level return requirement, and/or determining an instruction operation corresponding to the decoding instruction, and determining a return value corresponding to the original level and a preset source operand based on the instruction operation.

Optionally, the step of controlling, by the target processing unit, the GPIO according to the decoding instruction further includes:

if the target processing unit is an output processing unit, determining an output numerical instruction in the decoded instruction;

and determining an output value corresponding to the GPIO output based on the output numerical instruction and the decoding instruction.

Optionally, the step of determining an output value corresponding to the GPIO output based on the output numerical instruction and the decoded instruction includes:

determining a first source operand value and a second source operand value corresponding to the output numeric instruction, and determining a numeric operation instruction in the decoded instruction;

and performing instruction operation on the first source operation value and the second source operation value based on the numerical operation instruction to determine an output value of the GPIO output.

In addition, to achieve the above object, the present invention also provides a control system based on RISC-V, the control system based on RISC-V comprising:

the read-in decoding module is used for acquiring a control instruction read in by the RISC-V processor through the instruction decoding unit and determining a decoding instruction corresponding to the control instruction;

the direction switching module is used for determining direction switching information according to the decoding instruction and prestored historical switching information;

and the instruction processing module is used for determining a target processing unit corresponding to the direction switching information, and controlling the GPIO through the target processing unit according to the decoding instruction.

In addition, in order to achieve the above object, the present invention also provides a control chip based on RISC-V, comprising: the control method comprises the steps of a memory, a processor and a RISC-V based control program which is stored in the memory and can run on the processor, wherein the RISC-V based control program is executed by the processor to realize the RISC-V based control method.

In addition, in order to achieve the above object, the present invention also provides a RISC-V based control storage medium having a RISC-V based control program stored thereon, which when executed by a processor, implements the steps of the RISC-V based control method as described above.

The invention discloses a control method based on RISC-V, which comprises the steps of obtaining a control instruction read in by a RISC-V processor through an instruction decoding unit, and determining a decoding instruction corresponding to the control instruction; determining direction switching information according to the decoding instruction and prestored history switching information; and determining a target processing unit corresponding to the direction switching information, and controlling the GPIO by the target processing unit according to the decoding instruction. The instruction decoding unit is used for obtaining the control instruction read in by the RISC-V processor, further realizing the control instruction decoding, determining the target processing unit corresponding to the direction switching information, and further controlling the GPIO according to the decoding instruction by the target processing unit so as to realize the control of GPIO input and output.

Therefore, the invention avoids the phenomenon that the memory read-write instruction sent by the chip processor can reach the GPIO after passing through the bus logic in the prior art, and the control method based on RISC-V not only can ensure the open source of the control instruction through the control instruction read in by the RISC-V processor and further increase the instruction modifying and expanding functions used by users, but also can control the GPIO according to the decoding instruction through the target processing unit, thereby improving the control efficiency of chip input and output.

Drawings

FIG. 1 is a schematic diagram of a control chip architecture based on RISC-V of a hardware operating environment according to an embodiment of the present invention;

FIG. 2 is a flow chart of a RISC-V based control method of the present invention;

FIG. 3 is a schematic diagram of a RISC-V based control system according to the present invention;

FIG. 4 is a schematic diagram of one embodiment of a RISC-V based control system of the present invention;

FIG. 5 is a schematic diagram of a conventional GPIO control structure;

FIG. 6 is a schematic diagram of a RISC-V based control system module.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				10	Open source instruction set RISC-V processor	11	Register file
12	Instruction interface	20	Instruction decoding unit
				30	Direction switching unit	40	Input processing unit
50	Output processing unit	60	Input/output port GPIO
				00	RISC-V based control chip	01～0N	Peripheral 1 to peripheral N

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic diagram of a control chip structure based on RISC-V of a hardware running environment according to an embodiment of the present invention.

As shown in fig. 1, the RISC-V based control chip may include: processor 0003, e.g. central processing unit (Central Processing Unit, CPU), communication bus 0001, fetch interface 0002, processing interface 0004, memory 0005. Wherein a communication bus 0001 is used to enable connected communication between these components. The acquisition interface 0002 may comprise an information acquisition device, an acquisition unit such as a computer, and the optional acquisition interface 0002 may also comprise a standard wired interface, a wireless interface. Processing interface 0004 may optionally comprise a standard wired interface, a wireless interface. The Memory 0005 may be a high-speed random access Memory (Random Access Memory, RAM) or a stable nonvolatile Memory (NVM), such as a disk Memory. The memory 0005 may alternatively be a storage device separate from the aforementioned processor 0003.

It will be appreciated by those skilled in the art that the architecture shown in fig. 1 is not limiting of a RISC-V based control chip, and may include more or fewer components than shown, or certain components may be combined, or a different arrangement of components.

As shown in fig. 1, an operating system, an acquisition interface module, a processing interface module, and a RISC-V based control program may be included in the memory 0005 as a storage medium.

In the RISC-V based control chip shown in fig. 1, the communication bus 0001 is mainly used to implement connection communication between components; the acquisition interface 0002 is mainly used for connecting a background server and carrying out data communication with the background server; the processing interface 0004 is mainly used for connecting a deployment end (user end) and carrying out data communication with the deployment end; the processor 0003 and the memory 0005 in the RISC-V based control chip of the present invention may be provided in the RISC-V based control chip, and the RISC-V based control chip invokes the RISC-V based control program stored in the memory 0005 through the processor 0003 and executes the RISC-V based control system provided by the embodiment of the present invention.

Based on the above hardware structure, the control method embodiment based on RISC-V is provided.

A first embodiment of the RISC-V based control method of the present invention is presented, referring to fig. 2, fig. 2 is a flow chart of the RISC-V based control method, and the RISC-V based control method includes:

step S10, a control instruction read in by a RISC-V processor is obtained through an instruction decoding unit, and a decoding instruction corresponding to the control instruction is determined;

in this embodiment, after the RISC-V processor reads the control instruction according to the instruction information input by the user or the instruction in the memory, the instruction decoding unit obtains the control instruction read by the RISC-V processor, and determines the decoding instruction corresponding to the control instruction. The instruction information refers to an instruction input by a user in a self-definition manner, and a corresponding control instruction is read in a RISC-V processor according to the instruction. After the control instruction is obtained, the control instruction is decoded in the instruction decoding unit to obtain a decoded instruction, and finally the decoded instruction can be sent to a corresponding processing unit according to the internal instruction characteristics of the decoded instruction, so that the accuracy of processing the instruction can be ensured.

Step S20, determining direction switching information according to the decoding instruction and pre-stored history switching information;

in this embodiment, after the decoded instruction is obtained, the direction switching information is determined according to the decoded instruction and the pre-stored history switching information, where the pre-stored history switching information refers to the direction information corresponding to the last decoded instruction, for example, the direction information corresponding to the last decoded instruction is the output direction, the output direction is taken as the pre-stored history switching information, and the direction switching information refers to the switching information for switching the input/output direction of the GPIO. The step of determining the direction switching information according to the decoding instruction and the pre-stored history switching information comprises the following steps:

step A10, determining instruction features corresponding to the decoding instructions, and detecting whether the instruction features are matched with preset direction switching instruction features or not;

in this embodiment, when determining the direction switching information, it is required to determine the instruction feature corresponding to the decoded instruction, and detect whether the instruction feature matches with the preset direction switching instruction feature, because there are at least three cases in the decoded instruction, one is the decoded instruction for switching the direction, one is the decoded instruction for inputting control, and the other is the decoded instruction for outputting control, where the instruction feature is the feature for decoding the decoded instruction by the instruction decoding unit, and the preset direction switching instruction feature is the instruction feature of the direction switching instruction, and by detecting whether the instruction feature matches with the preset direction switching instruction feature, it is further determined whether the decoded instruction is the direction switching instruction. After the step of detecting whether the instruction feature matches with a preset direction switching instruction feature, the method comprises the following steps:

step B10, if the instruction features are matched with preset direction switching instruction features, determining a direction instruction corresponding to the decoding instruction;

and step B20, controlling the GPIO to switch the direction according to the direction instruction by a direction switching unit, and executing the step of acquiring the control instruction read in by the RISC-V processor by an instruction decoding unit based on the GPIO after the direction switching.

In this embodiment, when the instruction feature matches with the preset direction switching instruction feature, a direction instruction corresponding to the decoded instruction is determined, that is, the decoded instruction is determined to be a direction switching instruction, and the direction instruction is an instruction for switching the input or output direction of the GPIO. For example, io.set rs1 = 1, rd, defined as switching GPIO input direction according to the value of rs1 being 1; and the value of rd, which is returned to be successfully executed, can be customized by a user or can be set as a default value. After the decoded instruction determines the value of rs1, determining the instruction feature corresponding to the value, and further determining whether the instruction feature is the input or output direction switching according to the instruction feature of the value, that is, determining that io.set rs 1=1 in the decoded instruction is actually determined, and further determining whether the instruction feature is the direction switching instruction feature, and further determining that the instruction feature is the input or output direction switching instruction according to the value of rs 1. After the direction switching instruction is determined, the decoding instruction is sent to a corresponding direction switching unit, the direction switching unit controls the GPIO to switch the direction according to the direction instruction, meanwhile, the direction instruction is used as pre-stored history switching information, the step of acquiring the control instruction read by the RISC-V processor through the instruction decoding unit is executed by the GPIO after switching, namely, after the direction of the GPIO is switched, the step of acquiring the control instruction read by the RISC-V processor through the instruction decoding unit is continuously executed, so that the input and output control of the GPIO is realized, the input and output control efficiency of the GPIO is further improved, the bus logic and protocol transmission process is not needed, and the input and output efficiency of the whole GPIO is greatly saved.

And step A20, if the instruction characteristic is not matched with the preset direction switching instruction characteristic, determining a transmission direction corresponding to the pre-stored history switching information, and taking the transmission direction as the direction switching information.

In this embodiment, when it is determined that the instruction feature does not match the preset direction switching instruction feature, a transmission direction corresponding to the pre-stored history switching information is determined, and the transmission direction is used as the direction switching information, that is, when the instruction feature does not match the preset direction switching instruction feature, the decoding instruction can be known to be an input or output control instruction, and the transmission direction corresponding to the decoding instruction is further determined by determining the transmission direction corresponding to the pre-stored history switching information, where the transmission direction refers to the input or output direction. That is, the transmission direction of the current decoding instruction is determined according to the last decoding instruction, and since the direction switching instruction is between the last decoding instruction and the current decoding instruction, the last decoding instruction still needs to continue the transmission direction of the last decoding instruction, and when the transmission direction of the input or output control instruction is different from the transmission direction corresponding to the history switching information, the execution instruction fails, and rd returns a failure value. After determining the decoding instruction, determining whether the instruction characteristic of the decoding instruction is matched with the preset input direction instruction characteristic, and if so, determining that the input direction is direction switching information; otherwise, determining the output direction as direction switching information, for example, determining the instruction characteristic in the decoded instruction as out when the decoded instruction is io.out.raw rs1, rd, and further determining that the decoded instruction is matched with the preset output direction instruction characteristic, otherwise determining the instruction characteristic in the decoded instruction as in when the decoded instruction is io.in.tail1 rd, and further determining that the decoded instruction is matched with the preset input direction instruction characteristic, wherein the preset input/output direction instruction characteristic refers to the input/output related control instruction characteristic in the decoded instruction. The destination to which the decoding instruction needs to be sent can be further determined by determining the direction switching information, and the accuracy of control of the decoding instruction is further improved.

And step S30, determining a target processing unit corresponding to the direction switching information, and controlling the GPIO by the target processing unit according to the decoding instruction.

In this embodiment, after determining the direction switching information, a target processing unit corresponding to the direction switching information is determined, and finally the decoded instruction sending value target processing unit is controlled by the GPIO, where the target processing unit refers to a processing unit corresponding to the instruction, and may be a direction switching unit, an input processing unit or an output processing unit. The step of determining the target processing unit corresponding to the direction switching information comprises the following steps:

step C10, determining a transmission direction in the direction switching information, and detecting whether the transmission direction is matched with a preset input direction;

step C20, if the transmission direction is matched with a preset input direction, determining the target processing unit as an input processing unit;

and step C30, if the transmission direction is not matched with the preset input direction, determining the target processing unit as an output processing unit.

In this embodiment, the transmission direction is further detected by determining the transmission direction in the direction switching information, and whether the transmission direction matches with the preset input direction is detected, when the transmission direction matches with the preset input direction, the target processing unit is determined to be the input processing unit, the decoding instruction is sent to the input processing unit, the GPIO is controlled by the input processing unit, otherwise, the target processing unit is determined to be the output processing unit, the decoding instruction is sent to the output processing unit, and the GPIO is controlled by the output processing unit. Or detecting whether the transmission direction matches with a preset output direction, wherein the preset input/output direction refers to the input/output direction of the GPIO. Wherein, the step of controlling the GPIO by the target processing unit according to the decoding instruction includes:

step D10, if the target processing unit is an input processing unit, determining a level return requirement corresponding to the decoding instruction;

and step D20, determining an input value corresponding to the original level of the GPIO input based on the level return requirement, and/or determining an instruction operation corresponding to the decoding instruction, and determining a return value corresponding to the original level and a preset source operand based on the instruction operation.

In this embodiment, when the target processing unit is an input processing unit, a level return requirement corresponding to a decoded instruction is determined, and then an input value corresponding to an original level of the GPIO input is determined according to the level return requirement, and/or an instruction operation corresponding to the decoded instruction is determined, and a return value corresponding to the original level and a preset source operand is determined based on the instruction operation, and the return value is used as an input value, that is: the input original level value may be returned to the RISC-V processor after some operations (such as calculating the number of leading 0 and 1, performing bit operation with the source operand rs2, etc.), where the level return requirement refers to a return requirement for the input level, the original level refers to the level of the GPIO input, and the input value refers to a value corresponding to the original level after the level return requirement is processed. For example, the decoding instruction is io.in/track 1/tail1/count1 rd, and the value of the position of the first bit 1 in the original level value is used as the input value, the value of the position of the last bit 1 in the original level value is used as the input value, and the number of bits 1 in the original level value is used as the input value. The source operand is defined as an input value, the input value corresponding to the original level of the GPIO input is determined based on the source operand requirement by determining the source operand requirement corresponding to the decoding instruction, and the source operand requirement refers to the return requirement of the source operand and does not relate to the original level of the input. For example, io.in.bit rs1, rd means that the designated bit state of rs1 is determined as an input value, and the designated bit can be rs 1=2, so that the bit state of the second bit is determined, and the input is controlled by the decoding instruction, so that not only is the control diversity improved, but also the efficiency of the input is improved through bus processing.

The step of controlling the GPIO by the target processing unit according to the decoding instruction further includes:

step E10, if the target processing unit is an output processing unit, determining an output numerical instruction in the decoded instruction;

and E20, determining an output value corresponding to the GPIO output based on the output numerical instruction and the decoding instruction.

In this embodiment, when the target processing unit is an output processing unit, an output numerical instruction corresponding to the decoding instruction is determined, and then an output value corresponding to the GPIO output is determined according to the output numerical instruction and the decoding instruction, where the output numerical instruction refers to a stored source operand value, and the output value refers to an output value after the output numerical instruction and the decoding instruction are processed. For example, the decoding instruction is io.out.raw rs1, rd, the value of rs1 is correspondingly used as the output value of the GPIO, io.out.and rs1, rs2, rd refers to the value of rs1 and rs2 according to the bit and is used as the output value of the GPIO, io.out.set/clear rs1, rd refers to the state of the designated bit of rs1 in the GPIO is set to 1/0, other bits keep the original state unchanged as the output value, io.out.non rs1, rd refers to the inversion of the designated bit of rs1 in the GPIO, and other bits keep the original state unchanged as the output value. The output is controlled through the decoding instruction, so that the control diversity is improved, and the output efficiency is improved through bus processing. Wherein the step of determining the output value corresponding to the GPIO output based on the output numerical instruction and the decoded instruction comprises: .

Step F10, determining a first source operand value and a second source operand value corresponding to the output numerical instruction, and determining a numerical operation instruction in the decoded instruction;

and step F20, performing instruction operation on the first source operand value and the second source operand value based on the numerical operation instruction to determine an output value of the GPIO output.

In this embodiment, for the output value control of the GPIO output, the output value of the GPIO is mainly output according to the first source operand and the second source operand stored in the register file, and further, the output value of the GPIO output is determined by the relation defined by the values of the two source operands and the instruction, the first source operand is the value of the first source operation and the second source operand is the value of the second source operation, and further, the numerical operation instruction in the decode instruction is the instruction for operating the values of the two source operands, and the instruction operation is performed on the first source operand and the second source operand through the numerical operation instruction.

Further, the present embodiment also provides a control system based on RISC-V, referring to fig. 3, fig. 3 is a schematic structural diagram of the control system based on RISC-V according to the present invention.

In this embodiment, the RISC-V based control system includes an open source instruction set RISC-V processor 10, an instruction decoding unit 20, a direction switching unit 30, an input processing unit 40, an output processing unit 50, and an input/output port GPIO60, where the RISC-V processor 10 includes an instruction interface 12 and a register file 11;

the instruction interface 12 is respectively connected with the register file 11, the instruction decoding unit 20, the input processing unit 40 and the output processing unit 50, and the instruction interface 12 is used for transmitting control instructions generated by the RISC-V processor 10;

the instruction decoding unit 20 is respectively connected with the direction switching unit 30, the input processing unit 40 and the output processing unit 50, and the instruction decoding unit 20 is used for determining a decoding instruction according to the control instruction and determining direction switching information based on the decoding instruction;

the GPIO60 is connected to the direction switching unit 30, the input processing unit 40, and the output processing unit 50, respectively, the input processing unit 40 is configured to control input of the GPIO60 according to the direction switching information and the decoding instruction, and the output processing unit 50 is configured to control output of the GPIO60 according to the direction switching information and the decoding instruction.

Referring to fig. 5, fig. 5 is a schematic diagram of a control structure of a conventional GPIO, in which the GPIO is connected to an SoC bus in a memory mapped manner as a slave device; the chip processor is connected to the SoC bus as a main device; the processor controls a control register in the GPIO module by sending a memory read-write instruction, so that the level of the IO pin of the chip from the peripheral is controlled/read. Because of the bus, the control delay of the GPIO is larger, and the memory read-write instruction sent from the chip processor can reach the GPIO module after passing through the bus logic, so the delay is larger. Therefore, the requirements cannot be met in the scene with requirements on IO response speed; it is also an aspect that the calculation is decoupled from the control. Typically the chip processor controls the output value of the GPIO from the calculation of a previous instruction. For example, the variables a and b are operated (such as addition, subtraction, multiplication, division, etc.) to obtain the result c, and then c is written into the output control register of the GPIO to control the IO pin level of the chip. This process needs to be implemented by at least two instructions, the first instruction operating on a, b and the second instruction writing the value of c to the control register. The response speed of IO can be influenced by the separation of calculation and control, and the real-time performance of the system is reduced; the last point is that the IO direction switches slowly. The switching of the GPIO direction is also controlled by a register suspended on the bus, and there is a problem that the bus delay is large. Therefore, the technical scheme of the application is provided for solving the operability of chip control and improving the control efficiency of chip input and output.

In the present embodiment, the instruction generating unit in the open source instruction set RISC-V processor 10 is configured to generate a control instruction, where the control direction switching unit 30 performs direction switching, the input processing unit 40 performs input control, or the output processing unit 50 performs output control, and the register file 11 is configured to store source operands required to be used by the control instruction and return values after the control instruction is executed. When the open source instruction set RISC-V processor 10 generates a control instruction, the control instruction is sent to the instruction decoding unit 20 through the instruction interface 12 to decode the control instruction to obtain a decoded instruction, and then direction switching information corresponding to the decoded instruction is determined, and finally the direction switching information and the decoded instruction are sent to the direction switching unit 30, the input processing unit 40 and the output processing unit 50, so that the direction and the input/output control of the input/output port GPIO60 are realized. The decoded instruction refers to an instruction after the control instruction is decoded, the decoding may refer to a decoding for determining a control target of the control instruction and a control principle of the instruction, and the direction switching information refers to an input direction or an output direction corresponding to the input/output port GPIO 60. The direction switching of the input/output port GPIO60 can be realized through the direction switching unit 30 by determining the direction switching information and decoding instructions, or the input control of the input/output port GPIO60 can be realized through the input processing unit 40, or the output control of the input/output port GPIO60 can be realized through the output processing unit 50. Yet another aspect is the nature of the open source instruction set RISC-V processor 10 itself, which allows the user to customize control instructions and increase the instruction modification and expansion functions used by the user due to the open source nature of the instruction set. It should be noted that the direction switching unit and the input/output processing unit may be a micro-chip for executing instructions, or may be directly controlled by the open source instruction set RISC-V processor 10, the register file refers to a storage location of the open source instruction set RISC-V processor 10 where source operands are stored, and the instruction interface may refer to a port for transmitting instructions. The control mode can also avoid the phenomenon that the memory read-write instruction sent by the chip processor can reach the GPIO after passing through the bus logic, and the direction switching unit is used for carrying out the input-output direction switching control of the GPIO, or the input processing unit is used for carrying out the input control of the GPIO, or the output processing unit is used for carrying out the output control of the GPIO, so that the control efficiency of the input and output of the chip is improved.

The invention obtains the control instruction read in by RISC-V processor through the instruction decoding unit, and determines the decoding instruction corresponding to the control instruction; determining direction switching information according to the decoding instruction and prestored history switching information; and determining a target processing unit corresponding to the direction switching information, and controlling the GPIO by the target processing unit according to the decoding instruction. The instruction decoding unit is used for obtaining the control instruction read in by the RISC-V processor, further realizing the control instruction decoding, determining the target processing unit corresponding to the direction switching information, and further controlling the GPIO according to the decoding instruction by the target processing unit so as to realize the control of GPIO input and output.

The present invention also provides a control system module schematic diagram based on RISC-V, referring to fig. 6, the control system based on RISC-V includes:

the read-in decoding module A01 is used for acquiring a control instruction read in by the RISC-V processor through the instruction decoding unit and determining a decoding instruction corresponding to the control instruction;

the direction switching module A02 is used for determining direction switching information according to the decoding instruction and prestored history switching information;

the instruction processing module a03 is configured to determine a target processing unit corresponding to the direction switching information, and control the GPIO according to the decoding instruction through the target processing unit.

Optionally, the direction switching module a02 is further configured to:

Optionally, the instruction processing module a03 is further configured to:

Further, based on the first embodiment of the RISC-V based control system described above,

the invention also provides a control chip based on RISC-V.

The chip of the invention comprises: a memory, a processor, and a RISC-V based control program stored on the memory and executable on the processor, which when executed by the processor implements the steps of the RISC-V based control method as described above.

The invention also provides a storage medium.

The storage medium of the present invention has stored thereon a RISC-V based control program which, when executed by a processor, implements the steps of the RISC-V based control method as described above.

The method implemented when the RISC-V based control program running on the processor is executed may refer to various embodiments of the RISC-V based control method of the present invention, and will not be described herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.

The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.

The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. A control method based on RISC-V, wherein the control method based on RISC-V is applied to a control system based on RISC-V, the control system based on RISC-V includes an instruction decoding unit, an open source instruction set RISC-V processor, and an input/output port GPIO, the steps of the control method based on RISC-V include:

2. The RISC-V based control method according to claim 1, wherein the determining direction switching information based on the decoded instruction and pre-stored history switching information comprises:

3. The RISC-V based control method of claim 2, wherein after the step of detecting whether the instruction feature matches a preset direction switch instruction feature, comprising:

4. The RISC-V based control method according to claim 1, wherein the RISC-V based control system includes an input processing unit and an output processing unit, and the step of determining a target processing unit to which the direction switching information corresponds includes:

5. The RISC-V based control method of claim 1, wherein the step of controlling the GPIO by the target processing unit according to the decoded instruction comprises:

6. The RISC-V based control method of claim 1, wherein the step of controlling the GPIO by the target processing unit according to the decoded instruction further comprises:

7. The RISC-V based control method of claim 6, wherein the determining the output value corresponding to the GPIO output based on the output value instruction and the decoded instruction comprises:

8. A RISC-V based control system, the RISC-V based control system comprising:

9. A RISC-V based control chip, the RISC-V based control chip comprising: a memory, a processor and a RISC-V based control program stored on the memory and executable on the processor, which when executed by the processor implements the steps of the RISC-V based control method according to any one of claims 1 to 7.

10. A storage medium having stored thereon a RISC-V based control program which, when executed by a processor, implements the steps of a RISC-V based control method according to any one of claims 1 to 7.