CN116027988B - Wear leveling method for memory and control method for chip controller of wear leveling method - Google Patents
Wear leveling method for memory and control method for chip controller of wear leveling method Download PDFInfo
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Abstract
The invention discloses a wear leveling method for a memory and a control method for a chip controller thereof, and relates to the field of embedded design. The method divides the address space into storage units, performs row-column equalization in the two-dimensional array storage space, realizes in-block equalization, realizes block-to-block equalization, achieves better effect by controlling row size and column size, achieves better effect by controlling row update threshold and column update threshold with lower moving cost at the expense of slight effect, achieves better effect and higher moving cost by controlling row size and column size, and achieves better effect by controlling row update threshold and column update threshold with lower moving cost with slightly lower effect than similar algorithm. The proposed wear-leveling method is built into the self-contained function of the memory, adds a little logic, redesigns the structure of the memory controller, and internalizes the wear-leveling function into the memory.
Description
Technical Field
The invention relates to the field of embedded design, in particular to a wear leveling method for a memory and a control method of a chip controller thereof.
Background
Some nonvolatile memories (e.g., PCM, RRAM, MRAM, flash, etc.) suffer from limited write endurance when used-the number of writes to an address is limited, whereas in practical applications the distribution of each address accessed by the memory will exhibit a near gaussian distribution, and once the number of writes to any portion of the memory exceeds the endurance limit, the entire device is considered inoperable. This is because there is temporal locality of external access to memory, i.e., the memory location that has been accessed is likely to be referenced multiple times in a short period of time, and spatial locality, i.e., when one address of memory is accessed once, then there is a likelihood that the external will then go to access an address in its vicinity.
It can be seen that in this access case, the actual memory utilization is small. When a memory is damaged, a large portion of available space remains, and the life of the device is long enough to be exploited. It is desirable to design algorithms that allow balanced access to the entire memory, rather than just writing to specific areas, distributing operations on certain blocks across the entire memory, and achieving a balance of writing of blocks, such algorithms are known as wear leveling algorithms.
For an emerging nonvolatile memory, a wear-leveling algorithm is a necessary requirement and is supposed to be embedded into a controller in a chip to be used as a part of the memory, meanwhile, the addition of the wear-leveling algorithm tends to increase the read-write time, and the function of accessing while balancing can be realized by embedding algorithm logic into the controller, so that the time cost of the algorithm is greatly reduced. The existing balancing strategy for enhancing the durability of the nonvolatile memory is not limited to carrying out movement balancing in a one-dimensional address space, and the effect is not ideal; there is no special requirement for the read-write address distribution.
Disclosure of Invention
The invention aims to provide a wear leveling method for a memory and a control method of a chip controller thereof. A mapping relation between a logical address and a physical address is designed, and premature damage of a memory caused by excessive centralized access of the outside to some addresses is avoided. The original concentrated access state is converted into the balanced access to the memory as much as possible, and the memory durability is enhanced without generating extra memory overhead and read-write delay as much as possible.
The invention provides a wear-leveling method for a memory, which comprises three modules, namely:
module 1: a read-write address conversion module;
module 2: a counting module;
module 3: an equalization module;
the process of the memory for reading and writing data is as follows: the method comprises the steps of externally inputting addresses, data and commands, wherein the commands firstly flow through a counting module, if the commands are writing commands, the counting module is increased by one, and after the commands reach a set updating threshold value, an equalization module is started; the address passes through a read-write address conversion module, and according to the equalization algorithm parameters transmitted by the equalization module, the externally input logical address is converted into a physical address, and then the physical address, the command and the data are accessed to a memory; when the equalization module is started, carrying out data moving operation on a partial area of the memory, and updating parameters of a corresponding equalization method after moving is completed;
in addition, the moving operation of the balancing module is performed according to a pre-designed memory address dividing operation, wherein the memory address dividing operation is to abstract a memory space into one memory unit (the size of the memory unit is formulated according to the required balancing precision) under a certain memory storage space size, one memory unit is composed of a plurality of actual physical addresses of a memory, one memory unit is abstract into an address in an algorithm, and one-dimensional memory space, namely a continuous memory address space from small to large, is rearranged into a two-dimensional array memory space; dividing effective addresses and idle addresses on a two-dimensional address space of segmentation and recombination, so as to carry out row and column moving operation of the equalization module; meanwhile, different updating thresholds are needed for the row moving operation and the column moving operation, namely, the row moving operation needs a row updating threshold, the column moving operation needs a column updating threshold, and the setting of the updating threshold is closely related to the row and column size of the divided two-dimensional array storage space;
the module 1 comprises: decomposing an address array and calculating a physical address;
the method for decomposing the address array comprises the following steps: the input logical address addr_LA is used for calculating the position of the logical address in the array, namely row and column coordinates according to the size of the row and the column col, and the calculation mode is as follows:
the reason that the row coordinate xadr is equal to the logical address addr_la divided by the column col-1 and then the remainder is divided by the column col-1 is that both the row and the column have one inaccessible row and column;
the reason why the column coordinate yadr is equal to the logical address addr_la divided by the column col-1 and then rounded, divided by the column col-1 is that the rows and columns have one inaccessible row and column, which is understood as arranging the whole logical address range into a matrix array according to the rows and columns, the last row and the last column of the matrix array are inaccessible, and the logical address range is calculated by subtracting the row from the column plus 1 from the address space, so that the address in the logically accessible address space needs to be converted into the address in the physical space first;
the method for calculating the physical address comprises the following steps: the resultant rows of xadr and yadr were calculated separately:
the new address xnew of the row coordinate xadr is equal to xadr plus start_col and then the column col-1 is left, and then, if xnew is greater than or equal to the column coordinate gap_col_num where the empty column is located, xnew is added with 1; if xnew is less than gap_col_num, xnew is unchanged; start_col is responsible for recording the number of cycles that the empty column gap_col has for the column;
the new address ynew of the column coordinate yadr is equal to yadr plus start_row and then the row-1 is left, next, if ynew is larger than or equal to row coordinate gap_row_num where the empty interlace is located, then ynew is added with 1, and if ynew is smaller than gap_row_num, then ynew is unchanged; start_row is responsible for recording the number of cycles that the empty interlace gap_row is made to line;
after xnew and ynew are obtained, the physical address addr_PA to be accessed is calculated, and the calculation method is as follows:
addr_PA= ynew * col + xnew
the functions of module 1 are: after balanced movement, the logical address is converted into a physical address, so that normal reading and writing are realized;
the module 2 comprises: a row counting module and a column counting module;
the row counting module: for the input logical address, if the write operation is performed, the write_num_row is added with 1; if the write_num_row is greater than the row update threshold write_time_row, then the write_num_row is set to 0 while the row equalization module is started;
the column count module: for the input logical address, if it is a write operation, then write_num_col is incremented by 1; if the write_num_col is greater than the column update threshold write_time_col, then the write_num_col is set to 0 while the column equalization module is started;
the function of the module 2 is to account for row writing operation counting, reach the corresponding row updating threshold value, and start a row balancing module; the column writing operation counting is responsible, the corresponding column updating threshold value is reached, and a column balancing module is started;
the module 3 comprises: a row equalization module and a column equalization module;
the line equalization module: two cases: the empty interlace gap_row is equal to 0, then the last line and the current empty interlace gap_row are moved to each other; if the empty interlace gap_row is not equal to 0, the empty interlace gap_row is moved forward;
the column equalization module: two cases: the gap_col is equal to 0, and the last column and the current gap_col are moved mutually; if the space column gap_col is not equal to 0, the space column gap_col is moved forward;
the function of the module 3 is to balance the rows and columns respectively and to carry out data movement;
equalization principle: the one-dimensional address space is divided into a two-dimensional matrix array, row-column alternate equalization is respectively carried out on rows and columns, and through converting the addresses into x coordinates and y coordinates, the read-write addresses are in one-to-one correspondence when the row equalization and the column equalization are simultaneously carried out.
The working process comprises the following steps:
when not balanced: the logic address, read-write operation and other signals input from the outside are converted into physical addresses which are required to be accessed after equalization through read-write address array conversion, meanwhile, the counting module counts according to whether the logic address, the read-write operation and other signals are read or write operation, if the logic address, the read-write operation and other signals are write operation, row counting or column counting reaches a row updating threshold value or a column updating threshold value, and row equalization or column equalization in the equalization module is started;
equalization: when the line is balanced: the empty interlace gap_row is equal to 0, then the last line and the current empty interlace gap_row are moved to each other; if the empty interlace gap_row is not equal to 0, the empty interlace gap_row is moved forward; after the moving is finished, starting the row writing operation counting; column equalization: the gap_col is equal to 0, and the last column and the current gap_col are moved mutually; if the space column gap_col is not equal to 0, the space column gap_col is moved forward; starting row writing operation counting after the moving is finished; the alternate proceeding of row equalization and column equalization is ensured.
The algorithm is simple and effective, the address space is divided into storage units, row and column equalization is carried out in the two-dimensional array storage space, the in-block equalization is realized, the row equalization is realized, the equalization among blocks is realized, the better effect is achieved by controlling the row size and the column size, the better effect is achieved by controlling the row updating threshold value and the column updating threshold value, the moving expense is greatly reduced at the cost of a slight effect, the better effect and the higher moving expense are achieved by controlling the row size and the column size, the moving expense is greatly reduced by controlling the row updating threshold value and the column updating threshold value, the effect is slightly reduced, and the better effect and the lower expense than those of the similar algorithm are achieved.
A method of controlling a memory chip controller employing a wear leveling algorithm, the method comprising:
the control process of the chip controller adopting the wear-leveling algorithm comprises the following steps: when the chip starts the wear-leveling function, external addresses and commands are subjected to address conversion and threshold value counting update through the above-mentioned module 1 (read-write address conversion module) and module 2 (counting module), and then the converted addresses and corresponding signals are transmitted into the control core, and the control core decides whether to start the leveling operation according to the transmitted signals; if the control core starts the equalization operation, the corresponding row and column moving operation is carried out on the two-dimensional array storage space which is recombined according to the storage space of the memory, and the physical address which needs to be moved is given by the equalization module; in addition, when the balanced moving operation is performed, the control core can start the balanced access mode at the same time, the moving address and the accessed address can be compared in the control core, and corresponding operation is adopted according to the comparison result, so that the balanced access operation is realized, and the condition that the memory is periodically occupied due to the balanced moving operation is greatly relieved.
The method is simple and effective, the address space is divided into storage units, row and column balancing is carried out in the two-dimensional array storage space, the in-block balancing is realized, the row balancing is realized, the block-to-block balancing is realized, the better effect is achieved by controlling the row size and the column size, the row updating threshold value and the column updating threshold value are controlled to be greatly lower in moving cost and at the cost of slightly effect, the better effect and the higher moving cost can be achieved by controlling the row size and the column size, the row updating threshold value and the column updating threshold value are controlled to be greatly lower in moving cost, the effect is slightly reduced, and the better effect and the lower cost than those of the similar algorithm are achieved. The proposed wear leveling method can be built into the self-contained function of the memory by the proposed design method of the embeddable memory controller, a little logic is added, the structure of the memory controller is redesigned, and the wear leveling function is internalized into the memory.
Drawings
FIG. 1 is a schematic diagram of memory space division and reorganization according to the present invention;
FIG. 2 is a schematic diagram of a row moving operation according to the present invention;
FIG. 3 is a schematic diagram of a column shifting operation according to the present invention;
FIG. 4 is a flow chart of the method of the present invention;
FIG. 5 is a schematic diagram of a memory architecture according to the present invention;
FIG. 6 is a diagram of a nonvolatile memory controller framework in accordance with the present invention.
Detailed Description
For the split reorganization of the memory address space, a reorganization method and a column and row moving method are described, taking one memory cell as 512 bits and a total of 25 memory cells (physical addresses) as an example:
as shown in fig. 1, 25 memory cells are rearranged into a two-dimensional address space of 5*5, and the last row and the last column are set to free addresses (red-marked portions), at which time the logical address, i.e., the externally accessible address space, is 16 memory cells.
As shown in fig. 2, the row shifting operation is embodied in a two-dimensional address space, in which the free address of a row and the address of the previous row are shifted, and in a one-dimensional address space, as indicated by the arrow marks in fig. 2.
The column shifting is performed after the row shifting, and the column shifting operation is performed on the two-dimensional address space, in which the free address of a column and the address of the previous column are shifted, and the one-dimensional address space is shown in fig. 3.
As shown in fig. 4, the flow of the present invention is as follows, and an array type equalization wear-out algorithm for enhancing the endurance of the nonvolatile memory, which includes the above three blocks, is illustrated by the address space size addr_space=8192, endurance=10ζ4, and access total number visit_num=8.192×10ζ7
visit_num = addr_space * endurance
Row=16, column col=512, row update threshold 2000, column update threshold 2000 is exemplified:
module one: read-write address translation
Address array decomposition: the input logical address addr_la, the logical address range is address space size-row size-column size +1=7665, because the last row is empty interlaced and the last column is also empty interlaced, the position of the logical address in the physical address array, i.e. row column coordinates, are calculated according to the row and column col sizes, as follows:
xadr= mod（addr_LA ，col-1)
yard=fix(addr_LA,col-1)
mod (a, B) represents a divided by B, and fix (a, B) represents a divided by B.
Physical address calculation: the obtained xadr and yadr are judged in a row-column separation mode:
the blank interlace initial coordinate gap_row_num is equal to 16 for the last row and the blank column initial coordinate gap_col_num is equal to 512 for the last column. The number of empty interlace cycles start_row is initially 0 and the number of empty bay loop cycles start_col is initially 0.
Line xadr: xnew= (xadr+start_col) mod (col-1), xnew equals xadr plus start_col and then leaves column col-1, next, xnew adds 1 if xnew is equal to or greater than gap_col_num (column coordinate where the space column is located), and xnew is unchanged if xnew is less than gap_col_num. start_col is responsible for recording the number of cycles that the empty column gap_col is made to column.
Column yadr: ynew=mod (yadr+start_row, row-1), ynew is equal to yadr plus start_row and then the remainder is made for row-1, next, ynew is added 1 if ynew is equal to or greater than gap_row_num (row coordinate where empty interlace is located), and ynew is unchanged if ynew is less than gap_row_num. start_row is responsible for recording the number of cycles that the empty interlace gap_row is cycling through for the lines.
After obtaining new xnew and ynew, calculating the physical address addr_pa to be accessed, wherein the calculating method is as follows:
addr_PA=ynew * col + xnew
the conversion of the input logical address to the accessed physical address is completed so far.
And a second module: counting module
And a row counting module: for the input logical address, if the write operation is performed, the write_num_row is added with 1; if the write_num_row is greater than the write_time_row (row update threshold), then the write_num_row is set to 0 while the row equalization module is started;
column counting module: for the input logical address, if it is a write operation, then write_num_col is incremented by 1; if write_num_col is greater than write_time_col (column update threshold), then write_num_col is set to 0 while the column equalization module is started;
thus, the counting of the rows and the starting of the corresponding row and column balancing module are completed.
And a third module: equalization module
a) And a line equalization module: two cases: the head address of the empty interlace gap_row is equal to 0, and the last line and the current empty interlace gap_row are mutually moved; if the head address of the empty interlace gap_row is not equal to 0, the empty interlace gap_row is shifted forward, and the line number is subtracted from each address in the empty interlace. Starting column counting after completion;
b) Column equalization module: two cases: the head address of the gap_col is equal to 0, and the last column and the current gap column are mutually moved; if the head address of the empty column gap_col is not equal to 0, the empty column gap_col is shifted forward, and the column number is subtracted from each address in the empty column. Starting row counting after completion;
so far, the line and line alternate equalization is completed, and the corresponding line and line counting module is returned.
The service life of the memory can be improved by several times compared with that of unbalanced improvement by using an equalizing algorithm, and experiments show that the effect of improvement is more obvious when the memory capacity is larger. Meanwhile, algorithm parameters including the row and column size of the two-dimensional address space, the size of a row and column updating threshold value and the like can be adjusted according to the size of the memory and actual use requirements, so that different effects and different moving expenses can be obtained.
The chip controller adopting wear-leveling algorithm provided by the invention is positioned at the position of the memory chip as shown in fig. 5 and is used for controlling different nonvolatile memory blocks. As shown in fig. 6, in the case of the data paths and the control paths in the nonvolatile memory controller, external signals including commands, addresses, data, etc. are passed through different data paths according to whether or not the equalization enable is valid. When the equalization enable is disabled, external signals flow directly into the control core. When the equalization enabling is effective, external signals can flow into the counting module and the read-write address conversion module separately, and then the two modules interact with the control core to realize the equalization function and the access function while equalizing.
The invention realizes the read-write correspondence after balancing by converting the address space into a two-dimensional matrix and adopting a coordinate system mode; the line size and the line updating threshold value are parameterized, so that a better effect is achieved, and the cost is lower; the algorithm logic is embedded into the memory controller, so that the access is realized at the same time conveniently, and the performance loss of the memory caused by the wear-leveling function is reduced to the greatest extent; the wear-leveling algorithm is decomposed into algorithm logic and specific operation, the controller structure is redesigned, and the leveling function is multiplexed with the function of the controller, so that the leveling is embedded into the controller.
Claims (2)
1. A wear leveling method for a memory, the method comprising three modules, respectively:
module 1: a read-write address conversion module;
module 2: a counting module;
module 3: an equalization module;
the process of the memory for reading and writing data is as follows: the method comprises the steps of externally inputting addresses, data and commands, wherein the commands firstly flow through a counting module, if the commands are writing commands, the counting module is increased by one, and after the commands reach a set updating threshold value, an equalization module is started; the address passes through a read-write address conversion module, and according to the equalization algorithm parameters transmitted by the equalization module, the externally input logical address is converted into a physical address, and then the physical address, the command and the data are accessed to a memory; when the equalization module is started, carrying out data moving operation on a partial area of the memory, and updating parameters of a corresponding equalization method after moving is completed;
in addition, the moving operation of the balancing module is performed according to a pre-designed memory address dividing operation, wherein the memory address dividing operation is to abstract a memory space into one memory unit under a certain memory storage space size, one memory unit is composed of a plurality of actual physical addresses of a memory, one memory unit is abstract into an address in an algorithm, and one-dimensional memory space, namely a continuous memory address space from small to large, is rearranged into a two-dimensional array memory space; dividing effective addresses and idle addresses on a two-dimensional address space of segmentation and recombination, so as to carry out row and column moving operation of the equalization module; meanwhile, different updating thresholds are needed for the row moving operation and the column moving operation, namely, the row moving operation needs a row updating threshold, the column moving operation needs a column updating threshold, and the setting of the updating threshold is closely related to the row and column size of the divided two-dimensional array storage space;
the module 1 is characterized by comprising: decomposing an address array and calculating a physical address;
the method for decomposing the address array comprises the following steps: the input logical address addr_LA is used for calculating the position of the logical address in the array, namely row and column coordinates according to the size of the row and the column col, and the calculation mode is as follows:
the reason that the row coordinate xadr is equal to the logical address addr_la divided by the column col-1 and then the remainder is divided by the column col-1 is that both the row and the column have one inaccessible row and column;
the reason why the column coordinate yadr is equal to the logical address addr_la divided by the column col-1 and then rounded, divided by the column col-1 is that the rows and columns have one inaccessible row and column, which is understood as arranging the whole logical address range into a matrix array according to the rows and columns, the last row and the last column of the matrix array are inaccessible, and the logical address range is calculated by subtracting the row from the column plus 1 from the address space, so that the address in the logically accessible address space needs to be converted into the address in the physical space first;
the method for calculating the physical address comprises the following steps: the resultant rows of xadr and yadr were calculated separately:
the new address xnew of the row coordinate xadr is equal to xadr plus start_col and then the column col-1 is left, and then, if xnew is greater than or equal to the column coordinate gap_col_num where the empty column is located, xnew is added with 1; if xnew is less than gap_col_num, xnew is unchanged; start_col is responsible for recording the number of cycles that the empty column gap_col has for the column;
the new address ynew of the column coordinate yadr is equal to yadr plus start_row and then the row-1 is left, next, if ynew is larger than or equal to row coordinate gap_row_num where the empty interlace is located, then ynew is added with 1, and if ynew is smaller than gap_row_num, then ynew is unchanged; start_row is responsible for recording the number of cycles that the empty interlace gap_row is made to line;
after xnew and ynew are obtained, the physical address addr_PA to be accessed is calculated, and the calculation method is as follows:
addr_PA= ynew * col + xnew
the functions of module 1 are: after balanced movement, the logical address is converted into a physical address, so that normal reading and writing are realized;
the module 2 comprises: a row counting module and a column counting module;
the row counting module: for the input logical address, if the write operation is performed, the write_num_row is added with 1; if the write_num_row is greater than the row update threshold write_time_row, then the write_num_row is set to 0 while the row equalization module is started;
the column count module: for the input logical address, if it is a write operation, then write_num_col is incremented by 1; if the write_num_col is greater than the column update threshold write_time_col, then the write_num_col is set to 0 while the column equalization module is started;
the function of the module 2 is to account for row writing operation counting, reach the corresponding row updating threshold value, and start a row balancing module; the column writing operation counting is responsible, the corresponding column updating threshold value is reached, and a column balancing module is started;
the module 3 comprises: a row equalization module and a column equalization module;
the line equalization module: two cases: the empty interlace gap_row is equal to 0, then the last line and the current empty interlace gap_row are moved to each other; if the empty interlace gap_row is not equal to 0, the empty interlace gap_row is moved forward;
the column equalization module: two cases: the gap_col is equal to 0, and the last column and the current gap_col are moved mutually; if the space column gap_col is not equal to 0, the space column gap_col is moved forward;
the function of the module 3 is to balance the rows and columns respectively and to carry out data movement;
equalization principle: dividing a one-dimensional address space into a two-dimensional matrix array, respectively carrying out row-column alternate equalization on rows and columns, and realizing one-to-one correspondence of read-write addresses when carrying out row equalization and column equalization simultaneously by converting the addresses into x coordinates and y coordinates;
the working process comprises the following steps:
when not balanced: the logic address and the read-write operation signal input from the outside are converted into the physical address to be accessed after equalization through read-write address array conversion, meanwhile, the counting module counts according to whether the read operation or the write operation is performed, if the read operation or the write operation is performed, the row counting or the column counting reaches a row updating threshold value or a column updating threshold value, and row equalization or column equalization in the equalization module is started;
equalization: when the line is balanced: the empty interlace gap_row is equal to 0, then the last line and the current empty interlace gap_row are moved to each other; if the empty interlace gap_row is not equal to 0, the empty interlace gap_row is moved forward; after the moving is finished, starting the row writing operation counting; column equalization: the gap_col is equal to 0, and the last column and the current gap_col are moved mutually; if the space column gap_col is not equal to 0, the space column gap_col is moved forward; starting row writing operation counting after the moving is finished; the alternate proceeding of row equalization and column equalization is ensured.
2. A control method of a memory chip controller employing a wear leveling method for a memory as claimed in claim 1, the method comprising:
the control process of the chip controller adopting the wear-leveling algorithm comprises the following steps: when the chip starts the wear-leveling function, external addresses and commands are converted and threshold value count is updated through the modules 1 and 2, and then the converted addresses and corresponding signals are transmitted into the control core, and the control core decides whether to start the leveling operation according to the transmitted signals; if the control core starts the equalization operation, the corresponding row and column moving operation is carried out on the two-dimensional array storage space which is recombined according to the storage space of the memory, and the physical address which needs to be moved is given by the equalization module; in addition, when the balanced moving operation is performed, the control core can start the balanced access mode at the same time, the moving address and the accessed address can be compared in the control core, and corresponding operation is adopted according to the comparison result, so that the balanced access operation is realized, and the condition that the memory is periodically occupied due to the balanced moving operation is greatly relieved.
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