CN107045424B - A method for time-division multiplexing management of small satellite solid-state memory to read and write files - Google Patents

Abstract

The invention relates to a time-division multiplexing management read-write file method of small satellite solid-state memory, which integrates the storage array of the solid-state memory into a whole and uniformly arranges storage addresses, opens up an input data cache and an output data cache, and has a data cache of a DMA controller. The bus connects the storage array with the input data cache and the output data cache; when the solid-state memory records data, the data in the input data cache is recorded into the storage space through the data bus to complete the write operation, and when the solid-state memory reads data, the input and output data caches pass through. The data bus reads the data in the storage space to complete the read operation; the DMA controller controls the time occupied by the read and write operations on the data bus to correspond to the read time and write time, and realizes time-division multiplexing of the data bus. The time slice is divided and assigned to read and write operations in turn, and the solid-state memory can read and write at the same time, which meets the needs of the solid-state memory to write the current file data while reading the current or historically written file data.

Description

A method for time-division multiplexing management of small satellite solid-state memory to read and write files

technical field

The invention relates to a time-division multiplexing management read-write file method for small satellite solid-state memory, so as to meet the requirements of satellites to write current file data to solid-state memory while reading current or historically written file data.

Background technique

The small satellite-to-ground data transmission is affected by the visible range of the ground station, and the satellite-to-ground data transmission can only be completed within the visible range of the ground station. This method can only transmit the data obtained by the payload within the visible range of the ground station to the Ground station; if the data obtained by the payload outside the visible range of the ground station needs to be stored in the solid-state memory in the form of files first, when it enters the visible range of the ground station, the file data in the solid-state memory will be played back to the ground station. The read and write operations of the memory are not performed at the same time. The above two methods are the basic working modes for small satellites to transmit payload data to the ground.

In order to meet two new requirements of users: 1. The payload obtains high-quality data, which significantly increases the amount of original data received by data transmission, but the rate of the data transmission radio frequency channel is fixed, and a large amount of data will be obtained within the visible range of the ground station. 2. Continuously obtain high-quality data within and outside the visible range of the ground station and transmit it to the ground station in time. These requirements all require the on-board solid-state memory to have a data cache function and to read and write data to the current file at the same time. The existing solid-state memory realizes the function of "recording and releasing" through internal storage space partition scheduling. The specific mechanism is as follows:

When the solid-state memory works while recording and storing, in order to solve the access conflict problem of the single-port FLASH memory chip, the entire memory array is divided into three sub-arrays (BANK) and equipped with two sets of buses, one for recording and the other for recording. playback. Each bus has three branches, respectively corresponding to a sub-array, and each sub-array can only work in read mode or write mode at a time. Each sub-array is divided into several partitions (also called sectors) from top to bottom. When working in the buffer mode, the partitions of the three sub-arrays are alternately recorded and played back under the unified scheduling of the task management unit, so as to achieve macro simultaneous reading For the purpose of writing, the partition scheduling strategy is shown in Figure 1 and Figure 1.

However, users and satellite designers put forward the requirement of solid-state memory to write current data and read currently written data or historical written data, that is, the function of recording multiple files at the same time, this design cannot be realized. In the "3BANK" partition scheduling design, the playback address and the recording address must satisfy the matching relationship (such as putting the address of BANK1 and recording the address of BANK3) to start recording and recording, so each time playback starts, it takes 3 to 5 seconds for the matching process (depending on how fast the recording rate is). Therefore, when multiple files are placed while recording, there must be a 3-5 second gap between the files. And because each file is composed of a large number of addresses located in different banks, in view of the effective resources of the single-chip microcomputer, the software design of storing multiple files while recording is extremely difficult.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is: in order to meet the requirement that the solid-state memory supports playback of arbitrary files, supports playback of multiple files, and has no constraint on the relative speed between the recording rate and the playback rate, a small satellite solid-state memory is provided. The memory time-sharing multiplexing management method of reading and writing files, integrates the solid-state memory storage space from "3BANK" into a complete storage space, and uses the DMA controller to control the storage array in the storage space to occupy and read and write the only data bus in a time-sharing manner. In order to achieve macroscopically, the read operation and write operation of the solid-state memory are independent, and finally meet the requirement of the solid-state memory to write the current data and read the current write data or historical write data.

The technical solution of the present invention is: the solid-state memory storage space is unifiedly integrated, and the DMA controller is used to control the solid-state memory read and write operations time-division multiplexing and shared data bus scheduling strategy, so as to realize the independent operation of solid-state memory recording and playback.

The implementation steps of the present invention are as follows:

(1) The storage array of the solid-state memory is integrated into an overall unified arrangement of storage addresses, the input data cache and the output data cache are opened, and the storage array is connected to the input data cache and the output data cache through a data bus with a DMA controller;

(2) When the solid-state memory records data, the data in the input data cache is recorded into the storage space through the data bus to complete the write operation. When the solid-state memory reads data, the input and output data cache reads the data in the storage space through the data bus to complete the read operation. ;

(3) The read and write operations share a data bus, and the DMA controller controls the time that the read and write operations occupy the data bus, which is correspondingly divided into read time and write time, so that the read and write operations are performed independently, and the time-sharing multiplexing of the data bus is realized. Especially when the solid-state memory is read and written at the same time, the DMA controller divides the data bus occupied time into small time slices, and assigns them to read and write operations in turn. Macroscopically, the solid-state memory can read and write at the same time.

In the step (1), the addresses of the storage array of the solid-state memory are arranged in sequence through the address management software, so that the storage array of the solid-state memory is integrated into a whole, and the solid-state memory has an input data cache and an output data cache, and the two independent caches are based on the input data. Different cache devices are selected for output rate requirements, such as high-speed DDR, MRAM, FPGA, etc. The two caches and the storage array are connected by a data bus with a DMA controller. The DMA controller controls the input buffer and the output buffer to complete the operation and occupation through the data bus time.

In the step (2), when the solid-state memory performs data recording, the external input data enters the input data cache, the input data cache transmits the input data to the storage array through the data bus, and the storage array management software controls the writing of the input data and generates a file. This process It is called a write operation; when the solid-state memory performs data playback, the storage array management software reads the file data in the storage array, transmits it to the output data cache through the data bus, and then outputs it through the output interface. This process is called a read operation.

When the read and write operations share a data bus in the step (3), the DMA controller controls the read and write operations to occupy the data bus time to control the read and write operations, so as to realize the time-division multiplexing of the data bus, and the read and write operations are performed independently. When the solid-state memory performs data recording, that is, a write operation is performed inside the solid-state memory, and the DMA controller allocates the occupied data bus time to the write operation, which is called the write time; For read operations, the DMA controller allocates the occupied data bus time to the read operation, and the data bus time is called read time; when the solid-state memory is recorded and placed, that is, when the solid-state memory is simultaneously read and written, the DMA controller will The occupied data bus time is divided into small time slices (time), that is, the recording time slice and the playback time slice are 200-300 microseconds, the recording time slice is smaller than the recording buffer time, the playback time slice is smaller than the playback buffer time, and the recording time slice is satisfied. Fast, playback time slices are slow, and are allocated to read and write operations in turn. In terms of time, it seems that solid-state memory is reading and writing at the same time. Because read and write operations are time-sharing independent operations, solid-state memory can write current file data and read current write or read data at the same time. Historical write file data.

The advantages of the present invention compared with the prior art are:

(1) The present invention controls the solid-state memory read and write operations to occupy the data bus time through the DMA controller, so that the solid-state memory read and write operations are completely independent from the "3BANK" design, and can complete separate recording and playback of files. Playing while playing, recording the current file and playing back the previous file at the same time, and other working modes, make the use of solid-state memory more diverse and flexible.

(2) The storage array of the present invention is integrated into one, which greatly simplifies the address resource management and usage complexity at the software level.

(3) The shared data bus for read and write operations in the present invention simplifies the structural design at the hardware level of the solid-state memory.

Description of drawings

Figure 1 is a schematic diagram of the original solid-state memory storage space for the "3BANK" structure partition scheduling design;

FIG. 2 is a design architecture diagram of time-division multiplexing scheduling of solid-state memory storage space according to the present invention;

Fig. 3 is a time slice division and allocation diagram when DMA controls solid-state memory to read and write at the same time in the present invention;

Detailed ways

As shown in Figure 2, compared with the "3BANK" structure design shown in Figure 1, the solid-state memory structure integrates the storage array as a whole, and no longer relies on the serial operation of the three BANK sub-arrays to record data and playback data. The independent data bus is replaced by a data bus with a DMA controller, that is, the entire storage array physically has only one external data bus corresponding to the input data buffer and the output data buffer. Whether it is recorded or played back, it is through DMA. The controller time-division multiplexing schedules the read and write operations to occupy the data bus time. When the solid-state memory performs data recording, that is, a write operation is performed inside the solid-state memory, the DMA controller allocates the occupied data bus time to the write operation, and this time is called write time; when the solid-state memory performs data playback, that is, the solid-state memory is internally read operation, the DMA controller will allocate the occupied data bus time to the read operation, which is called the read time; when the solid-state memory works in the record-and-play mode, the DMA controller needs to divide the data bus working time axis into write and read. The data bus is occupied by the corresponding write operation when the time slice is written, and the data bus is occupied by the corresponding read operation when the time slice is read.

As shown in Figure 3, when the solid-state memory is in the recording-while-playing mode, the DMA controller divides the data bus time occupied by the read and write operations into write and read time slices in turn: the write operation is performed in the "write time slice 1", and the input The recorded data occupies the data bus, and the data is written into the storage array for storage; at time t0, the write operation is stopped, the recorded data releases the bus, the bus is switched to the playback data, and the read operation is performed. The stored data is fetched and written into the output data buffer, and at the same time, the recorded data is written into the input data buffer for storage; at time t1, the read operation is stopped, the playback data releases the bus, the bus switches to the recorded data, and the write operation is performed. Recording time slice 2", the data in the input data buffer is taken out and written to the storage array for storage, and the data in the output data buffer is sent to the output interface board and played back at the rate required by the subsystem. By analogy, in the whole process of recording and playing, the read and write operations are controlled by the DMA controller to time-division and multiplex the data bus at the microscopic level, while the solid-state memory appears to be read and written at the same time at the macroscopic time.

After the solid-state memory adopts the bus time-division multiplexing strategy, the internal read and write operations of the solid-state memory are independently performed. can be seamlessly connected.

Claims (1)

1. The method for managing read-write files by time-sharing multiplexing of the moonlet solid-state memory is characterized by comprising the following steps:

(1) the storage arrays of the solid-state memory are integrated into a whole, the storage addresses are arranged uniformly, an input data cache and an output data cache are opened up, and the storage arrays are connected with the input data cache and the output data cache through a data bus with a DMA controller; when addresses of a storage array of the solid-state memory are arranged in sequence through address management software, the storage array of the solid-state memory is integrated, an input data cache and an output data cache of the solid-state memory are used as two independent caches, different cache devices are selected according to input and output speed requirements, the different cache devices comprise a high-speed DDR (double data rate), an MRAM (magnetic random access memory) or an FPGA (field programmable gate array), a data bus with a DMA (direct memory access) controller is arranged between the two independent caches and the storage array, and the DMA controller controls the input data cache and the output data cache to finish operation occupation time through the data bus;

(2) when the solid-state memory records data, the data in the input data cache is recorded into the storage space through the data bus to complete the write operation, and when the solid-state memory reads the data, the output data cache reads the data in the storage space through the data bus to complete the read operation; when the solid-state memory records data, external input data enter an input data cache, the input data cache transmits the input data to the storage array through a data bus, and the storage array management software controls the input data to be written and generates a file, wherein the process is called writing operation; when the solid-state memory plays back data, the storage array management software reads file data in the storage array, transmits the file data to an output data cache through a data bus, and then outputs the file data through an output interface, wherein the process is called read operation;

(3) the read-write operation shares one data bus, the DMA controller controls the time of the read-write operation occupying the data bus, and the read-write operation is divided into read time and write time correspondingly, so that the read-write operation is carried out independently, and the time-sharing multiplexing of the data bus is realized; when the solid-state memory reads and writes simultaneously, the DMA controller divides the occupied time of the data bus into small time slices, and distributes the small time slices to the read-write operation in sequence to realize the function of simultaneously reading and writing the solid-state memory; when the read-write operation shares one data bus, the DMA controller controls the read-write operation to occupy the time of the data bus to control the read-write operation, time-sharing multiplexing of the data bus is realized, the read-write operation is independently performed, when the solid-state memory performs data recording, namely, the write operation is performed in the solid-state memory, the DMA controller distributes the time occupied by the data bus to the write operation, and the time occupied by the data bus is called as write time; when the solid-state memory plays back data, namely, the solid-state memory carries out read operation, the DMA controller allocates the occupied data bus time to the read operation, and the occupied data bus time is called as read time; when the solid-state memory is played while recording, namely when the inside of the solid-state memory is simultaneously read and written, the DMA controller divides the time occupying a data bus into tiny time slices, namely a recording time slice and a playback time slice are 200 plus 300 microseconds, the recording time slice is less than the recording cache time, the playback time slice is less than the playback cache time, the recording time slice is fast, the playback time slice is slow, and the recording time slice and the playback time slice are sequentially distributed to the read-write operation, the solid-state memory is simultaneously read and written in time, and the solid-state memory is realized to write current file data and read current written file data or historical written file data due to the time-sharing independent operation of the read-;

wherein:

the storage spaces of the solid-state memories are uniformly integrated, and a DMA controller is adopted to control the read-write operation of the solid-state memories and a scheduling strategy of a time-sharing multiplexing shared data bus, so that the recording and playback of the solid-state memories can be independently operated; the data bus independent data buses of the recorded data and the played back data are replaced by a data bus with a DMA controller without depending on the serial work of three BANK subarrays, namely the whole storage array only has a unique data bus corresponding to an input data cache and an output data cache physically, and the DMA controller is used for time-division multiplexing scheduling read-write operation to occupy the data bus time during recording or playback;

when the solid-state memory records data, namely, writing operation is carried out in the solid-state memory, the DMA controller allocates the time occupying a data bus to the writing operation, and the time is called writing time; when the solid-state memory plays back data, namely, a read operation is carried out in the solid-state memory, the DMA controller allocates the time of occupying a data bus to the read operation, and the time is called as a read time; when the solid-state memory works in a read-while-write mode, the DMA controller needs to divide the working time axis of the data bus into a write time slice and a read time slice for polling, wherein the data bus is occupied by corresponding write operation when the time slice is written, and the data bus is occupied by corresponding read operation when the time slice is read;

when the solid-state memory is in a memory-while-play mode, the DMA controller sequentially divides the time of the data bus occupied by the read-write operation into a write time slice and a read time slice: executing write operation in the 'write time slice 1', wherein the input recording data occupies a data bus, and writing the data into a storage array for storage; at time t0, stopping writing, recording data releasing the data bus, switching the data bus to playback data, executing reading, and in 'playback time slice 1', taking out the data stored in the storage array and writing the data into the output data cache, and simultaneously writing the recorded data into the input data cache for waiting storage; at the time t1, stopping reading operation, playing back data to release a data bus, switching the data bus to record data, executing writing operation, and in the 'recording time slice 2', taking out the data in the input data cache and writing the data into a storage array for storage, and simultaneously sending the data in the output data cache to an output interface board and playing back the data according to the speed required by the subsystem; in the whole process of recording and playing, the DMA controller controls the read-write operation to multiplex the data bus in a time-sharing way microscopically, and the solid-state memory reads and writes simultaneously in a macroscopic time;

after the solid-state memory adopts a data bus time-sharing multiplexing strategy, the internal reading and writing operations of the solid-state memory are independently carried out, the mode of recording and playing while recording the current file can support the playback of any file, and the cross-file can be seamlessly connected.

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