CN107045424B - Time-sharing multiplexing management file reading and writing method for moonlet solid-state memory - Google Patents
Time-sharing multiplexing management file reading and writing method for moonlet solid-state memory Download PDFInfo
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Abstract
The invention relates to a time-sharing multiplexing management read-write file method of a minisatellite solid-state memory, which integrates a storage array of the solid-state memory into a whole and uniformly arranges storage addresses, develops an input data cache and an output data cache, and a data bus with a DMA controller connects the storage array with the input data cache and the output data cache; when the solid-state memory records data, the data in the input data cache is recorded into the storage space through the data bus to complete the write operation, and when the solid-state memory reads the data, the input data cache reads the data in the storage space through the data bus to complete the read operation; the DMA controller controls the time that the read-write operation occupies the data bus to correspond to the read time and the write time, time division multiplexing of the data bus is achieved, the DMA controller divides the time occupied by the data bus into time slices and sequentially distributes the time slices to the read-write operation, and the solid-state storage has a simultaneous read-write function, so that the requirement that the solid-state storage writes current file data and reads current written file data or historically writes file data is met.
Description
Technical Field
The invention relates to a method for managing read-write files by time-sharing multiplexing of a solid-state memory of a small satellite, which is used for meeting the requirement that the satellite writes current file data into the solid-state memory and reads the current written file data or the historical written file data.
Background
The small satellite to ground data transmission is influenced by the visual range of the ground station, and the satellite to ground data transmission can be completed in the visual range of the ground station, so that only the data acquired by the effective load in the visual range of the ground station can be transmitted to the ground station in real time; if the payload acquisition data outside the visual range of the ground station needs to be stored in the solid-state memory in a file form, the file data in the solid-state memory is played back to the ground station when the visual range of the ground station is entered, and the reading and writing operations of the solid-state memory are not performed simultaneously in this way. The two above modes are the basic mode of operation where the small satellite transmits payload data to ground.
To accommodate two new requirements of the user: 1. the effective load obtains high-quality data, so that the data transmission receiving original data volume is obviously improved, but the data transmission radio frequency channel speed is fixed, and the obtained large data volume is transmitted to the ground station within the visible range of the ground station; 2. high-quality data are continuously acquired in the area inside and outside the visible range boundary of the ground station and need to be transmitted to the ground station in time. These requirements all require the on-board solid-state memory to have a data caching function and to be able to read and write data to the current file at the same time, and this solid-state memory operation mode is called "write while read". The existing solid-state memory realizes the function of 'recording while releasing' through internal storage space partition scheduling, and the specific mechanism is as follows:
when the solid-state memory works while recording and playing, in order to solve the problem of access conflict of a single-port FLASH memory chip, the whole memory array is equally divided into three sub-arrays (BANK) and is provided with two sets of buses, wherein one set is used for recording and the other set is used for playback. Each set of bus has three branches respectively corresponding to a sub-array, and each sub-array can only work in a read mode or a write mode at one moment. Each sub-array is divided into a plurality of partitions (also called sectors) from top to bottom, and when the buffer mode works, the partitions of the three sub-arrays are alternately recorded and played back under the unified scheduling of the task management unit, so that the purpose of macroscopically reading and writing simultaneously is achieved, and the partition scheduling strategy is as shown in fig. 1 and fig. 1.
However, for users and satellite designers, the requirement that the solid-state memory writes current data and reads the current written data or historical written data is provided, that is, the function of storing multiple files while recording is performed, and the design cannot be realized. In the '3 BANK' partition scheduling design, the playback address and the recording address must satisfy a matching relationship (such as the address of playing BANK1 and the address of recording BANK 3) to start recording and playing simultaneously, so that a matching process (depending on the speed of the recording rate) of 3-5 seconds is required for starting playback each time. Therefore, when multiple files are stored while recording, a neutral period of 3-5 seconds is inevitably generated between the files. And because each file is composed of a large number of addresses located in different BANKs, the software design difficulty of storing multiple files while recording is extremely high in view of the effectiveness of single chip microcomputer resources.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in order to meet the requirements that a solid-state memory supports playback of any file and multiple files and has no constraint on the relative speed relationship between the recording rate and the playback rate, a microsatellite solid-state memory time-sharing multiplexing management read-write file method is provided, the storage space of a solid-state memory is integrated into a complete storage space from 3BANK, a DMA controller is used for controlling a storage array in the storage space to occupy read and write a unique data bus in a time-sharing manner, so that the macroscopically read operation and write operation of the solid-state memory are independent, and the requirements that the solid-state memory writes current data and reads current write data or historical write data are finally met.
The technical solution of the invention is as follows: the storage spaces of the solid-state memories are uniformly integrated, and the DMA controller is adopted to control the solid-state memory to read and write, time-sharing and multiplexing scheduling strategy of the shared data bus, so that the recording and playback of the solid-state memories can be independently operated.
The invention has the following implementation steps:
(1) the storage arrays of the solid-state memory are integrated into a whole, the storage addresses are arranged uniformly, an input data cache and an output data cache are opened up, and the storage arrays are connected with the input data cache and the output data cache through a data bus with a DMA (direct memory access) controller;
(2) when the solid-state memory records data, the data in the input data cache is recorded into the storage space through the data bus to complete the write operation, and when the solid-state memory reads the data, the input data cache reads the data in the storage space through the data bus to complete the read operation;
(3) the DMA controller controls the time of the read-write operation occupying the data bus, and correspondingly divides the read-write operation into read time and write time, so that the read-write operation is independently carried out, the time-sharing multiplexing of the data bus is realized, particularly when the solid-state memories read and write simultaneously, the DMA controller divides the time of the data bus occupying into small time slices, and the small time slices are sequentially allocated to the read-write operation, and macroscopically the solid-state memories have the function of simultaneously reading and writing.
In the step (1), addresses of the storage arrays of the solid-state memory are arranged in sequence through address management software, so that the storage arrays of the solid-state memory are integrated, the solid-state memory inputs a data cache and outputs the data cache, two independent caches select different cache devices such as high-speed DDR, MRAM, FPGA and the like according to the input and output speed requirements, a data bus with a DMA controller is arranged between the two caches and the storage arrays, and the DMA controller controls the input cache and the output cache to complete the operation through the data bus and occupy time.
When the solid-state memory in the step (2) records data, external input data enters an input data cache, the input data cache transmits the input data to the storage array through a data bus, and the storage array management software controls the input data to be written and generates a file, wherein the process is called writing operation; when the solid-state memory plays back data, the storage array management software reads file data in the storage array, transmits the file data to an output data cache through a data bus, and then outputs the file data through an output interface, and the process is called read operation.
When the read-write operation in the step (3) shares one data bus, the DMA controller controls the read-write operation to occupy the time of the data bus to control the read-write operation, so that time-sharing multiplexing of the data bus is realized, the read-write operation is performed independently, when the solid-state memory performs data recording, namely, the write operation is performed inside the solid-state memory, the DMA controller distributes the time occupied by the data bus to the write operation, and the time occupied by the data bus is called as write time; when the solid-state memory plays back data, namely, the solid-state memory carries out read operation, the DMA controller allocates the occupied data bus time to the read operation, and the occupied data bus time is called as read time; when the solid-state memory is played while recording, namely, when the inside of the solid-state memory is simultaneously read and written, the DMA controller divides the time occupying a data bus into tiny time slices (time), namely, the recording time slice and the playback time slice are 200 plus 300 microseconds, the recording time slice is smaller than the recording cache time, the playback time slice is smaller than the playback cache time, and the requirements that the recording time slice is fast and the playback time slice is slow are met, and the recording time slice and the playback time slice are sequentially distributed to the read-write operation.
Compared with the prior art, the invention has the advantages that:
(1) the invention controls the solid-state memory read-write operation to occupy the time of the data bus through the DMA controller, so that the solid-state memory read-write completely and independently operates relative to the design of '3 BANK', can complete the independent recording and independent playback of files, record and play the same file simultaneously, record the current file and play back the previous file simultaneously, and the like, and makes the use modes of the solid-state memory more diversified and flexible.
(2) The memory array is integrated into a whole, so that the address resource management and use complexity at the software level is greatly simplified.
(3) The invention uses the common data bus for read-write operation, so that the hardware level of the solid-state memory simplifies the structural design.
Drawings
FIG. 1 is a partition scheduling architecture diagram of a 3BANK structure of an original solid-state memory;
FIG. 2 is a diagram of a solid-state memory storage space time-division multiplexing scheduling design architecture according to the present invention;
FIG. 3 is a time slice partitioning and allocation diagram for DMA controlled solid state memory read and write simultaneously according to the present invention;
Detailed Description
As shown in fig. 2, compared with the "3 BANK" structure design shown in fig. 1, the solid-state memory structure integrates the memory array into a whole, and does not rely on the serial operation of three BANK sub-arrays, and the independent data bus of the recorded data and the played back data is replaced by a data bus with a DMA controller, i.e. the whole memory array only has a unique data bus corresponding to the input data buffer and the output data buffer, and the time of the data bus is occupied by the DMA controller in time-sharing multiplexing scheduling of read and write operations during recording and playback. When the solid-state memory records data, namely, writing operation is carried out in the solid-state memory, the DMA controller allocates the time occupying a data bus to the writing operation, and the time is called writing time; when the solid-state memory plays back data, namely, a read operation is carried out in the solid-state memory, the DMA controller allocates the time of occupying a data bus to the read operation, and the time is called as a read time; when the solid-state memory works in a read-while-write mode, the DMA controller needs to divide the working time axis of the data bus into two time slices of writing and reading for polling, wherein the data bus is occupied by corresponding writing operation during writing the time slices, and the data bus is occupied by corresponding reading operation during reading the time slices.
As shown in fig. 3, when the solid-state memory is in the write-while-read mode, the DMA controller sequentially divides the data bus time occupied by the read-write operation into write and read time slices: executing write operation in the 'write time slice 1', wherein the input recording data occupies a data bus, and writing the data into a storage array for storage; at time t0, stopping writing, releasing the bus of the recorded data, switching the bus to playback data, executing reading operation, and in the playback time slice 1, taking out the data stored in the storage array and writing the data into the output data cache, and simultaneously writing the recorded data into the input data cache for waiting storage; at time t1, the read operation is stopped, the playback data releases the bus, the bus is switched to the recording data, the write operation is executed, in "recording time slice 2", the data in the input data buffer is taken out and written into the storage array for storage, and meanwhile, the data in the output data buffer is sent to the output interface board and played back according to the speed required by the subsystem. In the whole process of recording and playing, the DMA controller controls the read-write operation to multiplex the data bus in a time-sharing way microscopically, and the solid-state memory reads and writes simultaneously in a macroscopic time.
After the solid-state memory adopts a bus time division multiplexing strategy, the internal reading and writing operations of the solid-state memory are independently carried out, and the mode of recording and playing while recording the current file can support the playback of any file (the current file or the historical file), and the cross-file can be seamlessly connected.
Claims (1)
1. The method for managing read-write files by time-sharing multiplexing of the moonlet solid-state memory is characterized by comprising the following steps:
(1) the storage arrays of the solid-state memory are integrated into a whole, the storage addresses are arranged uniformly, an input data cache and an output data cache are opened up, and the storage arrays are connected with the input data cache and the output data cache through a data bus with a DMA controller; when addresses of a storage array of the solid-state memory are arranged in sequence through address management software, the storage array of the solid-state memory is integrated, an input data cache and an output data cache of the solid-state memory are used as two independent caches, different cache devices are selected according to input and output speed requirements, the different cache devices comprise a high-speed DDR (double data rate), an MRAM (magnetic random access memory) or an FPGA (field programmable gate array), a data bus with a DMA (direct memory access) controller is arranged between the two independent caches and the storage array, and the DMA controller controls the input data cache and the output data cache to finish operation occupation time through the data bus;
(2) when the solid-state memory records data, the data in the input data cache is recorded into the storage space through the data bus to complete the write operation, and when the solid-state memory reads the data, the output data cache reads the data in the storage space through the data bus to complete the read operation; when the solid-state memory records data, external input data enter an input data cache, the input data cache transmits the input data to the storage array through a data bus, and the storage array management software controls the input data to be written and generates a file, wherein the process is called writing operation; when the solid-state memory plays back data, the storage array management software reads file data in the storage array, transmits the file data to an output data cache through a data bus, and then outputs the file data through an output interface, wherein the process is called read operation;
(3) the read-write operation shares one data bus, the DMA controller controls the time of the read-write operation occupying the data bus, and the read-write operation is divided into read time and write time correspondingly, so that the read-write operation is carried out independently, and the time-sharing multiplexing of the data bus is realized; when the solid-state memory reads and writes simultaneously, the DMA controller divides the occupied time of the data bus into small time slices, and distributes the small time slices to the read-write operation in sequence to realize the function of simultaneously reading and writing the solid-state memory; when the read-write operation shares one data bus, the DMA controller controls the read-write operation to occupy the time of the data bus to control the read-write operation, time-sharing multiplexing of the data bus is realized, the read-write operation is independently performed, when the solid-state memory performs data recording, namely, the write operation is performed in the solid-state memory, the DMA controller distributes the time occupied by the data bus to the write operation, and the time occupied by the data bus is called as write time; when the solid-state memory plays back data, namely, the solid-state memory carries out read operation, the DMA controller allocates the occupied data bus time to the read operation, and the occupied data bus time is called as read time; when the solid-state memory is played while recording, namely when the inside of the solid-state memory is simultaneously read and written, the DMA controller divides the time occupying a data bus into tiny time slices, namely a recording time slice and a playback time slice are 200 plus 300 microseconds, the recording time slice is less than the recording cache time, the playback time slice is less than the playback cache time, the recording time slice is fast, the playback time slice is slow, and the recording time slice and the playback time slice are sequentially distributed to the read-write operation, the solid-state memory is simultaneously read and written in time, and the solid-state memory is realized to write current file data and read current written file data or historical written file data due to the time-sharing independent operation of the read-;
wherein:
the storage spaces of the solid-state memories are uniformly integrated, and a DMA controller is adopted to control the read-write operation of the solid-state memories and a scheduling strategy of a time-sharing multiplexing shared data bus, so that the recording and playback of the solid-state memories can be independently operated; the data bus independent data buses of the recorded data and the played back data are replaced by a data bus with a DMA controller without depending on the serial work of three BANK subarrays, namely the whole storage array only has a unique data bus corresponding to an input data cache and an output data cache physically, and the DMA controller is used for time-division multiplexing scheduling read-write operation to occupy the data bus time during recording or playback;
when the solid-state memory records data, namely, writing operation is carried out in the solid-state memory, the DMA controller allocates the time occupying a data bus to the writing operation, and the time is called writing time; when the solid-state memory plays back data, namely, a read operation is carried out in the solid-state memory, the DMA controller allocates the time of occupying a data bus to the read operation, and the time is called as a read time; when the solid-state memory works in a read-while-write mode, the DMA controller needs to divide the working time axis of the data bus into a write time slice and a read time slice for polling, wherein the data bus is occupied by corresponding write operation when the time slice is written, and the data bus is occupied by corresponding read operation when the time slice is read;
when the solid-state memory is in a memory-while-play mode, the DMA controller sequentially divides the time of the data bus occupied by the read-write operation into a write time slice and a read time slice: executing write operation in the 'write time slice 1', wherein the input recording data occupies a data bus, and writing the data into a storage array for storage; at time t0, stopping writing, recording data releasing the data bus, switching the data bus to playback data, executing reading, and in 'playback time slice 1', taking out the data stored in the storage array and writing the data into the output data cache, and simultaneously writing the recorded data into the input data cache for waiting storage; at the time t1, stopping reading operation, playing back data to release a data bus, switching the data bus to record data, executing writing operation, and in the 'recording time slice 2', taking out the data in the input data cache and writing the data into a storage array for storage, and simultaneously sending the data in the output data cache to an output interface board and playing back the data according to the speed required by the subsystem; in the whole process of recording and playing, the DMA controller controls the read-write operation to multiplex the data bus in a time-sharing way microscopically, and the solid-state memory reads and writes simultaneously in a macroscopic time;
after the solid-state memory adopts a data bus time-sharing multiplexing strategy, the internal reading and writing operations of the solid-state memory are independently carried out, the mode of recording and playing while recording the current file can support the playback of any file, and the cross-file can be seamlessly connected.
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