CN116027597A - Array substrate, display device and driving method - Google Patents
Array substrate, display device and driving method Download PDFInfo
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Abstract
The embodiment of the invention discloses an array substrate, a display device and a driving method. In a specific embodiment, the array substrate includes a driving circuit board, N rows and 2M columns of sub-pixels arranged in an array, 2N gate lines and M data lines, where the M data lines are respectively connected to the 2M-1 th and 2M columns of sub-pixels, the 8n+1 th gate line is connected to the odd columns of sub-pixels in the 4n+1 th row, the 8n+2 th gate line is connected to the even columns of sub-pixels in the 4n+2 th row, the 8n+3 th gate line is connected to the even columns of sub-pixels in the 4n+1 th row, the 8n+4 th gate line is connected to the odd columns of sub-pixels in the 4n+2 th row, the 8n+5 th gate line is connected to the odd columns of sub-pixels in the 4n+3 th row, the 8n+7 th gate line is connected to the odd columns of sub-pixels in the 4n+4 th row, and the 8n+8 th gate line is connected to the even columns of sub-pixels in the 4n+4 th row, and the M belongs to a natural integer; the driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.
Description
Technical Field
The invention relates to the technical field of display. And more particularly, to an array substrate, a display device, and a driving method.
Background
The TFT LCD liquid crystal panel is required to adopt a positive and negative voltage driving method due to characteristics of liquid crystal, and common liquid crystal driving Inversion methods include Frame Inversion (Frame Inversion method), row Inversion (Column Inversion method), dot Inversion (Dot Inversion method), and Column Inversion method, as shown in fig. 1, wherein the common Inversion methods are the Column Inversion method and the Dot Inversion method. The column inversion mode has the advantage of low power consumption, but has poor performances such as low flicker, low crosstalk and the like; the dot inversion mode has good performances of low flicker, low crosstalk and the like, but has higher power consumption.
Disclosure of Invention
The invention aims to provide an array substrate, a display device and a driving method, which are used for solving at least one of the problems existing in the prior art.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the first aspect of the present invention provides an array substrate, including a driving circuit board, N rows and 2M columns of subpixels arranged in an array, 2N gate lines, and M data lines, where the M data lines are respectively connected to the 2M-1 th and 2M columns of subpixels, the 8n+1 th gate line is connected to the subpixels of the odd columns in the 4n+1 th row, the 8n+2 th gate line is connected to the subpixels of the even columns in the 4n+2 th row, the 8n+3 th gate line is connected to the subpixels of the even columns in the 4n+1 th row, the 8n+4 th gate line is connected to the subpixels of the odd columns in the 4n+2 th row, the 8n+5 th gate line is connected to the subpixels of the even columns in the 4n+3 th row, the 8n+6 th gate line is connected to the subpixels of the odd columns in the 4n+4 th row, and the 8n+8 th gate line is connected to the subpixels of the even columns in the 4n+3 th row, and the 8n+8 th gate line is connected to the positive integer of N belongs to nature;
The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.
In a specific embodiment, the driving circuit board is configured to scan the 2N gate lines line by line in a current frame period, wherein the data signals of the first polarity are charged to the 4n+1th row 2m—1th column sub-pixel through the mth data line when the 8n+1th gate line is scanned, the data signals of the first polarity are charged to the 4n+2th row 2m column sub-pixel through the mth data line when the 8n+2th gate line is scanned, the data signals of the second polarity are charged to the 4n+1th row 2m column sub-pixel through the mth data line when the 8n+1th gate line is scanned, the data signals of the second polarity are charged to the 4n+2nd column sub-pixel through the mth data line when the 8n+5th gate line is scanned, and the data signals of the first polarity are charged to the 4n+2m column sub-pixel through the mth data line when the 8n+2th gate line is scanned, and the data signals of the second polarity are charged to the 4n+2m+1th row sub-1 th column sub-pixel through the mth data line when the 8n+1th gate line is scanned.
In a specific embodiment, the driving circuit board is configured to scan the 2N gate lines line by line in a next frame period, wherein the data signals of the second polarity are charged through the m-th data line to the 4n+1th row 2m-1 th column sub-pixel when the 8n+1th gate line is scanned, the data signals of the second polarity are charged through the m-th data line to the 4n+2th row 2 m-th column sub-pixel when the 8n+2th gate line is scanned, the data signals of the first polarity are charged through the m-th data line to the 4n+1th row 2 m-th column sub-pixel when the 8n+4th gate line is scanned, the data signals of the first polarity are charged through the m-th data line to the 4n+2nd row 2m-1 th column sub-pixel when the 8n+5th gate line is scanned, and the data signals of the first polarity are charged through the m-th data line to the 4n+2th row 2m-1 th column sub-pixel when the 8n+4n+1th gate line is scanned.
In a specific embodiment, two gate lines respectively connected to partial columns of sub-pixels in two adjacent rows of sub-pixels are disposed between the two adjacent rows of sub-pixels.
In a specific embodiment, the data line is disposed between two adjacent columns of sub-pixels connected thereto.
In a specific embodiment, the sub-pixel includes a transistor and a pixel electrode, wherein a control electrode of the transistor is connected to a corresponding gate line, a first electrode is connected to a corresponding data line, and a second electrode is connected to the pixel electrode.
A second aspect of the present invention provides a display device comprising an array substrate as described above.
The third aspect of the present invention provides a driving method of an array substrate, where the array substrate includes a driving circuit board, N rows and 2M columns of subpixels arranged in an array, 2N gate lines, and M data lines, where the M data lines are respectively connected to the 2M-1 th and 2M column subpixels, the 8n+1 th gate line is connected to the subpixels of the odd columns in the 4n+1 th row, the 8n+2 th gate line is connected to the subpixels of the even columns in the 4n+2 th row, the 8n+3 th gate line is connected to the subpixels of the even columns in the 4n+1 th row, the 8n+4 th gate line is connected to the subpixels of the odd columns in the 4n+2 th row, the 8n+6 th gate line is connected to the subpixels of the odd columns in the 4n+4 th row, the 8n+7 th gate line is connected to the subpixels of the odd columns in the 4n+3 th row, and the 8n+8 th gate line is connected to the subpixels of the odd columns in the 4n+4 th row, and the M belongs to a natural integer;
The driving method includes: the driving circuit board drives the array of sub-pixels in a dot inversion manner.
In a specific embodiment, the driving circuit board drives the array of the sub-pixels in a dot inversion manner includes: the 2N gate lines are scanned line by line in a current frame period, wherein the 2m-1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+1 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th gate line is scanned, the 4n+1 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+4 th gate line is scanned, the 4n+3 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column sub-pixel is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column is scanned.
In a specific embodiment, the driving circuit board drives the array of sub-pixels in a dot inversion manner further includes: the 2N gate lines are scanned line by line in a next frame period, wherein the 2n+1th gate line is charged with a data signal of a second polarity through the mth data line when the 8n+1th gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+1th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+3th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+5th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th column is scanned.
The beneficial effects of the invention are as follows:
according to the technical scheme, the display power consumption can be reduced by reducing the voltage polarity switching times of the data lines, and the dot inversion mode with low flicker and good low crosstalk performance can be adopted while the display power consumption is reduced. Furthermore, the driving circuit does not need to additionally use a charge pump circuit, so that electronic components can be saved, and the product cost is reduced.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Fig. 1 shows a schematic diagram of four conventional liquid crystal driving inversion schemes.
FIG. 2 is a schematic diagram showing a conventional Dual gate+ (1+2DotInvitation) (double-gate+ (1+2 dot inversion)) inversion driving scheme.
FIG. 3 is a schematic diagram showing the driving timing of the conventional Dual gate+ (1+2DotInvitation) inversion scheme.
Fig. 4 is a schematic diagram of a driving architecture of an array substrate according to an embodiment of the invention.
Fig. 5 shows a schematic diagram of a driving timing of an array substrate according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the present invention, the present invention will be further described with reference to examples and drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this invention is not limited to the details given herein.
In the process of implementing the present invention, the inventor finds that at least the following problems exist in the prior art:
the TFT LCD liquid crystal panel is required to adopt a positive and negative voltage driving method due to the characteristics of liquid crystal, and common liquid crystal driving Inversion methods include Frame Inversion (Frame Inversion method), row Inversion (Column Inversion method), dot Inversion (Dot Inversion method), and Column Inversion method, as shown in fig. 1 and table 1, wherein the common Inversion methods are the Column Inversion method and the Dot Inversion method.
TABLE 1
The column inversion mode has the advantage of low power consumption, but the quality performances such as low flicker, low crosstalk and the like are poor; because of the Feed Through effect of the TFT, the optimal VCOM (LCD common voltage) at different positions of the display image is different, and the voltage asymmetry is dispersed to each position of the TFT LCD liquid crystal panel by the dot inversion mode, so that the voltage asymmetry is offset to the greatest extent, the optimal VCOM is uniform to the greatest extent, and the dot inversion mode has good quality performances of low flicker, low crosstalk and the like, but the power consumption is highest.
Taking the vehicle-mounted TFT LCD panel as an example, currently, the vehicle-mounted TFT LCD panel mostly adopts a Dual gate+ (1+2dot inversion) inversion mode, fig. 2 shows a driving architecture of an array substrate adopting a Dual gate+ (1+2dot inversion) inversion mode in the prior art, and it is understood that fig. 2 shows only a partial driving architecture, including 6 rows and 8 columns of subpixels, 12 Gate lines Gate1-Gate12 and 4 data lines Source1-Source4 arranged in an array. The 1 st Gate line Gate1 is respectively connected with the 1 st row and odd column sub-pixels, the 2 nd Gate line Gate2 is respectively connected with the 1 st row and even column sub-pixels, the 3 rd Gate line Gate3 is respectively connected with the 2 nd row and odd column sub-pixels, the 4 th Gate line Gate4 is respectively connected with the 2 nd row and even column sub-pixels, the 5 th Gate line Gate5 is respectively connected with the 3 rd row and odd column sub-pixels, the 6 th Gate line Gate6 is respectively connected with the 3 rd row and even column sub-pixels, the 7 th Gate line Gate7 is respectively connected with the 4 th row and odd column sub-pixels, the 8 th Gate line Gate8 is respectively connected with the 4 th row and even column sub-pixels, the 9 th Gate line Gate9 is respectively connected with the 5 th row and odd column sub-pixels, the 10 th Gate line Gate10 is respectively connected with the 5 th row and even column sub-pixels, the 11 th Gate line Gate11 is respectively connected with the 6 th row and odd column sub-pixels, the 12 th Gate line Gate12 is respectively connected with the 6 th row and even column sub-pixels, the 1 st and 3 rd line is respectively connected with the 3 rd line Source column 2, and the 3 rd line 2 wire is respectively connected with the 3 rd line and the 3 rd line 1 st line and the 3 th line. The sub-pixel comprises a Thin Film Transistor (TFT) and a pixel electrode, wherein a control electrode (grid electrode) of the TFT is connected with a corresponding grid line, a source electrode of the TFT is connected with a corresponding data line, and a drain electrode of the TFT is connected with the pixel electrode.
One sub-pixel is correspondingly connected with a data line and a grid line, two grid lines are arranged between two adjacent rows of sub-pixels, and one grid line is arranged on one side of the first row of sub-pixels and the last row of sub-pixels, which are not adjacent to the sub-pixels; in combination with 1+2dot inversion, i.e., the polarity of the voltage is switched once after charging each pair of two sub-pixels on the data line, which is +5v to-5V or-5v to +5v (except for the 1 st Gate line Gate1 and the last 1 Gate line Gate12 in fig. 2), it is understood that in actual driving, the voltage amplitude of the data signal is changed, and the fixed amplitude 5 is taken as an example only for convenience of illustration in this embodiment, because the switching times are mainly focused in this embodiment. As shown in fig. 3, a specific driving method of the conventional array substrate adopting the Dual gate+ (1+2dotinversion) method is as follows:
and scanning the 12 grid lines line by line in the current frame period, wherein when scanning the 1 st grid line Gate1, charging data signals of +5V to 1 st row 1 st and 5 th column sub-pixels through 1 st and 3 rd data lines Source1 and Source3 respectively, and charging data signals of-5V to 1 st row 3 rd and 7 th column sub-pixels through 2 nd and 4 th data lines Source2 and Source4 respectively.
When scanning the 2 nd Gate line Gate2, the 1 st row, the 2 nd column and the 6 th column of sub-pixels are charged with data signals of-5V through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 1 st row, the 4 th column and the 8 th column of sub-pixels are charged with data signals of +5V through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 3 rd Gate line Gate3, the 1 st and 5 th row sub-pixels are charged with-5V data signals through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 2 nd row 3 rd and 7 th column sub-pixels are charged with +5V data signals through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 4 th Gate line Gate4, the 2 nd row, 2 nd column and 6 th column sub-pixels are charged with +5v data signals through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 2 nd row, 4 th column and 8 th column sub-pixels are charged with-5V data signals through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 5 th Gate line Gate5, the 1 st and 5 th row sub-pixels are charged with +5v data signals through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 3 rd row sub-pixels are charged with-5V data signals through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 6 th Gate line Gate6, the 3 rd row 2 nd and 6 th column sub-pixels are charged with a data signal of-5V through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 3 rd row 4 th and 8 th column sub-pixels are charged with a data signal of +5v through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 7 th Gate line Gate7, the 1 st and 5 th row sub-pixels are charged with-5V data signals through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 4 th row 3 rd and 7 th column sub-pixels are charged with +5V data signals through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 8 th Gate line Gate8, the data signals of +5v are charged to the 4 th row 2 nd and 6 th column sub-pixels through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the data signals of-5V are charged to the 4 th row 4 th and 8 th column sub-pixels through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 9 th Gate line Gate9, the 1 st and 5 th row 1 st and 5 th column sub-pixels are charged with a +5v data signal through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 5 th row 3 rd and 7 th column sub-pixels are charged with a-5V data signal through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When the 10 th Gate line Gate10 is scanned, the 5 th row 2 and 6 th column sub-pixels are charged with a data signal of-5V through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 5 th row 4 and 8 th column sub-pixels are charged with a data signal of +5v through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 11 th Gate line Gate11, the 1 st and 5 th row sub-pixels are charged with-5V data signals through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the 3 rd and 7 th row sub-pixels are charged with +5V data signals through the 2 nd and 4 th data lines Source2 and Source4, respectively.
When scanning the 12 th Gate line Gate12, the data signals of +5v are charged to the 6 th row 2 nd and 6 th column sub-pixels through the 1 st and 3 rd data lines Source1 and Source3, respectively, and the data signals of-5V are charged to the 6 th row 4 th and 8 th column sub-pixels through the 2 nd and 4 th data lines Source2 and Source4, respectively.
In the next frame period, the 12 gate lines are scanned line by line, and the driving method is the same as that of the current frame period, but only converts the +5V data signal of the current frame period into the-5V data signal, and converts the-5V data signal of the current frame period into the +5V data signal, which is not repeated here.
The power consumption of the vehicle-mounted TFT LCD panel is positively correlated with the switching times and the switching amplitude values of the voltages on the data lines, namely the power consumption is larger as the switching times of the voltages on the data lines are larger; the larger the amplitude of the voltage switching on the data line, the larger the power consumption, e.g., the +5V switching to-5V (voltage absolute 10V) is greater than the +5V switching to 0V (voltage absolute 5V). Therefore, according to the specific driving method of the array substrate of the Dual gate+ (1+2dot inversion) inversion method, the voltage polarity is switched once after charging each pair of two sub-pixels of the data line, for example, the 1 st data line Source1 provides a data signal of-5V when scanning the 2 nd Gate line Gate2 and the 3 rd Gate line Gate3, the 1 st data line Source1 provides a data signal of +5v when scanning the 4 th Gate line Gate4 and the 5 th Gate line Gate5, the 1 st data line Source1 switches back to a data signal of-5V when scanning the 6 th Gate line Gate6 and the 7 th Gate line Gate7, and so on, and the power consumption is high. In addition, the Dual gate+ (1+2dot inversion) inversion still shows two-column/two-column alternate switching of sub-pixels, i.e., the quality performance such as low flicker and low crosstalk is still inferior to that of the true dot inversion shown in fig. 1.
At present, each large panel factory takes a high resolution, high display quality, low power consumption and low cost of a vehicle-mounted TFT LCD liquid crystal panel as future development targets, and therefore, the embodiment of the invention provides an array substrate which has the advantages of low power consumption, high display quality and low cost under the condition of high resolution.
The array substrate includes: the pixel array comprises a driving circuit board, N rows and 2M columns of sub-pixels, 2N grid lines and M data lines which are arranged in an array mode, wherein the M data lines are respectively connected with the 2M-1 th and 2M column of sub-pixels, the 8n+1 th grid line is connected with the odd column of sub-pixels in the 4n+1 th row, the 8n+2 th grid line is connected with the even column of sub-pixels in the 4n+2 th row, the 8n+4 th grid line is connected with the odd column of sub-pixels in the 4n+2 th row, the 8n+5 th grid line is connected with the even column of sub-pixels in the 4n+3 th row, the 8n+6 th grid line is connected with the odd column of sub-pixels in the 4n+4 th row, the 8n+7 th grid line is connected with the even column of sub-pixels in the 4n+3 th row, and the 8n+8 th grid line is connected with the even column of sub-pixels in the 4n+4 th row, and the M belongs to a positive integer. N and M are positive integers and can be the same or different.
In one possible implementation, two gate lines respectively connecting partial columns of sub-pixels in two adjacent rows of sub-pixels are disposed between the two adjacent rows of sub-pixels. The data line is disposed between two adjacent columns of subpixels connected thereto. Illustratively, the subpixel includes a transistor having a control electrode (gate) connected to a corresponding gate line, a first electrode (e.g., source) connected to a corresponding data line, and a second electrode (e.g., drain) connected to the pixel electrode.
The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.
In one possible implementation, the driving circuit board is configured to:
the 2N gate lines are scanned line by line in a current frame period, wherein the 2m-1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+1 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th gate line is scanned, the 4n+1 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+4 th gate line is scanned, the 4n+3 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column sub-pixel is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column is scanned.
Further, the driving circuit board is configured to:
the 2N gate lines are scanned line by line in a next frame period, wherein the 2n+1th gate line is charged with a data signal of a second polarity through the mth data line when the 8n+1th gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+1th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+3th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+5th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th column is scanned.
It can be understood that the connection mode of "8n+1th gate line is connected to the even column sub-pixel in 4n+1th row, 8n+2th gate line is connected to the odd column sub-pixel in 4n+2th row, 8n+3th gate line is connected to the odd column sub-pixel in 4n+1th row, 8n+4th gate line is connected to the even column sub-pixel in 4n+2th row, 8n+5th gate line is connected to the odd column sub-pixel in 4n+3th row, 8n+6th gate line is connected to the even column sub-pixel in 4n+4th row, 8n+7th gate line is connected to the odd column sub-pixel in 4n+4th row" can also achieve the same effects of low power consumption, low flicker and low crosstalk.
In a specific example, as shown in fig. 4, fig. 4 shows a driving architecture of an array substrate provided in this embodiment, and it is understood that fig. 4 shows only a part of the driving architecture.
The array substrate includes a driving circuit board (not shown), 6 rows and 8 columns of subpixels arranged in an array, 12 Gate lines Gate1 to Gate12, and 4 data lines Source1 to Source4.
The 1 st data line Source1 is connected with the 1 st and 2 nd row of sub-pixels respectively, the 2 nd data line Source2 is connected with the 3 rd and 4 th row of sub-pixels respectively, the 3 rd data line Source3 is connected with the 5 th and 6 th row of sub-pixels respectively, and the 4 th data line Source4 is connected with the 7 th and 8 th row of sub-pixels respectively.
Gate1 connects the odd numbered columns of the 1 st row, gate2 connects the even numbered columns of the 2 nd row, gate3 connects the even numbered columns of the 1 st row, gate4 connects the odd numbered columns of the 2 nd row, gate5 connects the even numbered columns of the 3 rd row, gate6 connects the odd numbered columns of the 4 th row, gate7 connects the odd numbered columns of the 3 rd row, gate8 connects the even numbered columns of the 4 th row, gate9 connects the odd numbered columns of the 5 th row, gate10 connects the even numbered columns of the 6 th row, gate11 connects the even numbered columns of the 5 th row, gate12 connects the odd numbered columns of the 6 th row.
The sub-pixel comprises a Thin Film Transistor (TFT) and a pixel electrode, wherein a grid electrode of the TFT is connected with a corresponding grid line, a first electrode of the TFT is connected with a corresponding data line, a second electrode of the TFT is connected with the pixel electrode, and the first electrode and the second electrode are respectively a source electrode and a drain electrode; or, a drain and a source. Taking the sub-pixel of row 2 and column 2 of fig. 4 as an example, the Gate of the thin film transistor needs to be connected to Gate2 of Gate2 across Gate3 of Gate3, only a via hole is needed, so that the technology has no difficulty and the cost is not increased.
Wherein the 1 st Gate line Gate1 is disposed at a side of the 1 st row sub-pixel far from the 2 nd row sub-pixel; the 2 nd Gate line Gate2 and the 3 rd Gate line Gate3 are disposed between the 1 st row and the 2 nd row sub-pixels; the 4 th Gate line Gate4 and the 5 th Gate line Gate5 are disposed between the 2 nd and 3 rd row sub-pixels; the 6 th Gate line Gate6 and the 7 th Gate line Gate7 are disposed between the 3 rd and 4 th row sub-pixels; the 8 th Gate line Gate8 and the 9 th Gate line Gate9 are disposed between the 4 th and 5 th rows of sub-pixels; the 10 th Gate line Gate10 and the 11 th Gate line Gate11 are disposed between the 5 th and 6 th row sub-pixels; the 12 th Gate line Gate12 is disposed at a side of the 6 th row sub-pixel distant from the 5 th row sub-pixel.
The 1 st data line Source1 is arranged between the 1 st column and the 2 nd column sub-pixels; the 2 nd data line Source2 is arranged between the 3 rd column and the 4 th column sub-pixels; the 3 rd data line Source3 is disposed between the 5 th column and the 6 th column sub-pixels; the 4 th data line Source4 is disposed between the 7 th column and the 8 th column sub-pixels.
The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner, as shown in fig. 5, where it is understood that in actual driving, the voltage amplitude of the data signal is changed, and in this embodiment, the fixed amplitude 5 is taken as an example only for convenience of explanation, because the switching times are mainly focused on in this embodiment, the specific driving manner is as follows:
The 12 Gate lines are scanned line by line in a current frame period, wherein the 1 st row 1 st column sub-pixel is charged with a data signal of +5v through the 1 st data line Source1, the 1 st row 3 rd column sub-pixel is charged with a data signal of +5v through the 2 nd data line Source2, the 1 st row 5 th column sub-pixel is charged with a data signal of +5v through the 3 rd data line Source3, and the 1 st row 7 th column sub-pixel is charged with a data signal of +5v through the 4 th data line Source4 when the 1 st Gate line Gate1 is scanned.
The 2 nd row and 2 nd column sub-pixels are charged with the data signal of +5v through the 1 st data line Source1, the 2 nd row and 4 th column sub-pixels are charged with the data signal of +5v through the 2 nd data line Source2, the 2 nd row and 6 th column sub-pixels are charged with the data signal of +5v through the 3 rd data line Source3, and the 2 nd row and 8 th column sub-pixels are charged with the data signal of +5v through the 4 th data line Source4 when the 2 nd Gate line Gate2 is scanned.
The 1 st row and 2 nd column sub-pixels are charged with a data signal of-5V through the 1 st data line Source1, the 1 st row and 4 th column sub-pixels are charged with a data signal of-5V through the 2 nd data line Source2, the 1 st row and 6 th column sub-pixels are charged with a data signal of-5V through the 3 rd data line Source3, and the 1 st row and 8 th column sub-pixels are charged with a data signal of-5V through the 4 th data line Source4 when the 3 rd Gate line Gate3 is scanned.
The 2 nd row 1 st column sub-pixel is charged with a data signal of-5V through the 1 st data line Source1, the 2 nd row 3 rd column sub-pixel is charged with a data signal of-5V through the 2 nd data line Source2, the 2 nd row 5 th column sub-pixel is charged with a data signal of-5V through the 3 rd data line Source3, and the 2 nd row 7 th column sub-pixel is charged with a data signal of-5V through the 4 th data line Source4 when the 4 th Gate line Gate4 is scanned.
The 3 rd row 2 nd column sub-pixel is charged with a data signal of-5V through the 1 st data line Source1, the 3 rd row 4 th column sub-pixel is charged with a data signal of-5V through the 2 nd data line Source2, the 3 rd row 6 th column sub-pixel is charged with a data signal of-5V through the 3 rd data line Source3, and the 3 rd row 8 th column sub-pixel is charged with a data signal of-5V through the 4 th data line Source4 when the 5 th Gate line Gate5 is scanned.
The 1 st column and 4 th row sub-pixels are charged with a data signal of-5V through the 1 st data line Source1, the 3 rd column and 4 th row sub-pixels are charged with a data signal of-5V through the 2 nd data line Source2, the 5 th column and 4 th row sub-pixels are charged with a data signal of-5V through the 3 rd data line Source3, and the 7 th column and 4 th row sub-pixels are charged with a data signal of-5V through the 4 th data line Source4 when the 6 th Gate line Gate6 is scanned.
The 3 rd row 1 st column subpixel is charged with a data signal of +5v through the 1 st data line Source1, the 3 rd row 3 rd column subpixel is charged with a data signal of +5v through the 2 nd data line Source2, the 3 rd row 5 th column subpixel is charged with a data signal of +5v through the 3 rd data line Source3, and the 3 rd row 7 th column subpixel is charged with a data signal of +5v through the 4 th data line Source4 when the 7 th Gate line Gate7 is scanned.
The 4 th row and 2 nd column sub-pixels are charged with a data signal of +5v through the 1 st data line Source1, the 4 th row and 4 th column sub-pixels are charged with a data signal of +5v through the 2 nd data line Source2, the 4 th row and 6 th column sub-pixels are charged with a data signal of +5v through the 3 rd data line Source3, and the 4 th row and 8 th column sub-pixels are charged with a data signal of +5v through the 4 th data line Source4 when the 8 th Gate line Gate8 is scanned.
The 1 st row and 1 st column sub-pixels are charged with a data signal of +5v through the 1 st data line Source1, the 3 rd row and 3 rd column sub-pixels are charged with a data signal of +5v through the 2 nd data line Source2, the 5 th row and 5 th column sub-pixels are charged with a data signal of +5v through the 3 rd data line Source3, and the 5 th row and 7 th column sub-pixels are charged with a data signal of +5v through the 4 th data line Source4 when the 9 th Gate line Gate9 is scanned.
The data signal of +5v is charged to the 6 th row and 2 nd column sub-pixels through the 1 st data line Source1, the data signal of +5v is charged to the 6 th row and 4 th column sub-pixels through the 2 nd data line Source2, the data signal of +5v is charged to the 6 th row and 6 th column sub-pixels through the 3 rd data line Source3, and the data signal of +5v is charged to the 6 th row and 8 th column sub-pixels through the 4 th data line Source4 when the 10 th Gate line Gate10 is scanned.
The 11 th Gate line Gate11 is scanned by charging the 5 th row and 2 nd column sub-pixels with a data signal of-5V through the 1 st data line Source1, charging the 5 th row and 4 th column sub-pixels with a data signal of-5V through the 2 nd data line Source2, charging the 5 th row and 6 th column sub-pixels with a data signal of-5V through the 3 rd data line Source3, and charging the 5 th row and 8 th column sub-pixels with a data signal of-5V through the 4 th data line Source 4.
The 1 st row and 1 st column sub-pixels are charged with a data signal of-5V through the 1 st data line Source1, the 3 rd row and 3 rd column sub-pixels are charged with a data signal of-5V through the 2 nd data line Source2, the 5 th row and 5 th column sub-pixels are charged with a data signal of-5V through the 3 rd data line Source3, and the 7 th row and 7 th column sub-pixels are charged with a data signal of-5V through the 4 th data line Source4 while the 12 th Gate line Gate12 is scanned.
In the next frame period, the 12 gate lines are scanned line by line, and the driving method is the same as that of the current frame period, but only converts the +5V data signal of the current frame period into the-5V data signal, and converts the-5V data signal of the current frame period into the +5V data signal, which is not repeated here.
As can be seen from the above driving method, in the array substrate provided in this embodiment, the data signal of the data line switches the voltage polarity once every four sub-pixels are charged, and compared with the conventional Dual gate+ (1+2dotconversion) inversion method, the number of times of switching the voltage polarity on the data line is reduced by half, thereby achieving the purpose of reducing the power consumption. In the existing vehicle-mounted TFT LCD liquid crystal panel, the customer generally provides VDD 3.3V voltage, VSP and VSN voltages are generated by DCDC circuits on PCBA and FPCA on the module, and VGH and VGL voltages are generated by a charge pump circuit, i.e. VDD, VSP, VSN, VGH and VGL voltages are required for driving the TFT LCD liquid crystal panel. If the power consumption of the TFT LCD panel is low, the charge pump circuit is not needed to be additionally used, and the driving circuit board of the array substrate is used. Therefore, the charge pump circuit is not required to be additionally used in the embodiment, a large number of electronic components can be saved, the purpose of reducing the cost is achieved, the power consumption and the cost are reduced, and meanwhile, the arrangement mode of the sub-pixels also achieves the true point inversion, so that the embodiment also has good quality performances of low flicker, low crosstalk and the like.
Another embodiment of the present invention provides a display device, including the array substrate provided in the foregoing embodiment. The display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and a vehicle-mounted display screen, which is not limited in this embodiment.
Another embodiment of the present invention provides a driving method of an array substrate, in which,
the array substrate comprises a driving circuit board, N rows and 2M columns of sub-pixels, 2N grid lines and M data lines which are arranged in an array mode, wherein the M data lines are respectively connected with the 2M-1 th and 2M column of sub-pixels, the 8n+1 th grid line is connected with the odd column of the 4n+1 th row, the 8n+2 th grid line is connected with the even column of the 4n+2 th row, the 8n+3 th grid line is connected with the even column of the 4n+1 th row, the 8n+4 th grid line is connected with the odd column of the 4n+2 th row, the 8n+5 th grid line is connected with the even column of the 4n+3 th row, the 8n+6 th grid line is connected with the odd column of the sub-pixel in the 4n+4 th row, the 8n+8 th grid line is connected with the even column of the sub-pixel in the 4n+3 th row, and the M belongs to a natural integer.
The driving method includes: the driving circuit board drives the array of sub-pixels in a dot inversion manner.
In one possible implementation, the driving circuit board drives the array of sub-pixels in a dot inversion manner includes: the 2N gate lines are scanned line by line in a current frame period, wherein the 2m-1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+1 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th gate line is scanned, the 4n+1 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+4 th gate line is scanned, the 4n+3 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column sub-pixel is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column is scanned.
Further, the driving circuit board drives the array of sub-pixels in a dot inversion manner further includes: the 2N gate lines are scanned line by line in a next frame period, wherein the 2n+1th gate line is charged with a data signal of a second polarity through the mth data line when the 8n+1th gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+1th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+3th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+5th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th column is scanned.
It should be noted that, the driving method provided in this embodiment is similar to the principle and the workflow of the array substrate provided in the foregoing embodiment, and the relevant portions may refer to the foregoing description and are not repeated herein.
In the description of the present invention, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
It is further noted that in the description of the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the foregoing examples of the present invention are provided merely for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a driving circuit board, N rows and 2M columns of sub-pixels, 2N grid lines and M data lines which are arranged in an array mode, wherein the M data lines are respectively connected with the 2M-1 th and 2M th columns of sub-pixels, the 8n+1 th grid line is connected with the odd columns of sub-pixels in the 4n+1 th rows, the 8n+2 th grid line is connected with the even columns of sub-pixels in the 4n+2 th rows, the 8n+3 th grid line is connected with the even columns of sub-pixels in the 4n+1 th rows, the 8n+4 th grid line is connected with the odd columns of sub-pixels in the 4n+2 th rows, the 8n+5 th grid line is connected with the odd columns of sub-pixels in the 4n+4 th rows, the 8n+7 th grid line is connected with the odd columns of sub-pixels in the 4n+3 th rows, and the 8n+8 th grid line is connected with the even columns of sub-pixels in the 4n+4 th rows, and the n+5 th grid lines belong to natural integers;
The driving circuit board is configured to drive the array of sub-pixels in a dot inversion manner.
2. The array substrate of claim 1, wherein the driving circuit board is configured to scan the 2N gate lines line by line in a current frame period, wherein the 4n+1th row 2m_1 th column sub-pixel is charged with a data signal of a first polarity through the m data line when the 8n+1th gate line is scanned, the 4n+2nd column sub-pixel is charged with a data signal of a first polarity through the m data line when the 8n+2th gate line is scanned, the 4n+1th row 2m column sub-pixel is charged with a data signal of a second polarity through the m data line when the 8n+3gate line is scanned, the 4n+2nd column sub-pixel is charged with a data signal of a second polarity through the m data line when the 8n+4th gate line is scanned, the 4n+2nd column sub-pixel is charged with a data signal of a second polarity through the m data line when the 8n+5th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the m data line when the 8n+2th column is scanned, and the data line is charged with a data signal of a first polarity through the m+2n+2th column when the 8 n+2th column is scanned.
3. The array substrate of claim 2, wherein the driving circuit board is configured to scan the 2N gate lines line by line in a next frame period, wherein the 4n+1th row 2m_1 th column sub-pixel is charged with a data signal of a second polarity through the m data line when the 8n+2th gate line is scanned, the 4n+2nd column sub-pixel is charged with a data signal of a second polarity through the m data line when the 8n+3gate line is scanned, the 4n+1th column sub-pixel is charged with a data signal of the first polarity through the m data line when the 8n+4th gate line is scanned, the 2m_1 th column sub-pixel is charged with a data signal of the first polarity through the m data line when the 8n+2th gate line is scanned, the 4n+2nd column sub-pixel is charged with a data signal of the first polarity through the m data line when the 8n+5th gate line is scanned, and the 4n+2m_1 th column sub-pixel is charged with a data signal of the second polarity through the m data line when the 8n+2th gate line is scanned, and the data line is charged with the data signal of the first polarity through the m data line when the 4n+2n+2th column sub-1 th column is scanned.
4. The array substrate of claim 1, wherein two gate lines respectively connecting partial columns of sub-pixels in two adjacent rows of sub-pixels are disposed between the two adjacent rows of sub-pixels.
5. The array substrate of claim 1, wherein the data lines are disposed between two adjacent columns of subpixels connected thereto.
6. The array substrate of claim 1, wherein the sub-pixels comprise transistors and pixel electrodes, wherein control electrodes of the transistors are connected to corresponding gate lines, first electrodes are connected to corresponding data lines, and second electrodes are connected to the pixel electrodes.
7. A display device comprising the array substrate according to any one of claims 1 to 6.
8. The driving method of the array substrate is characterized in that the array substrate comprises a driving circuit board, N rows and 2M columns of sub-pixels, 2N grid lines and M data lines which are arranged in an array mode, wherein the M data lines are respectively connected with the 2M-1 th and 2M-th column of sub-pixels, the 8n+1 th grid line is connected with the odd column of sub-pixels in the 4n+1 th row, the 8n+2 th grid line is connected with the even column of sub-pixels in the 4n+2 th row, the 8n+3 th grid line is connected with the even column of sub-pixels in the 4n+1 th row, the 8n+4 th grid line is connected with the odd column of sub-pixels in the 4n+2 th row, the 8n+6 th grid line is connected with the odd column of sub-pixels in the 4n+4 th row, the 8n+7 th grid line is connected with the odd column of sub-pixels in the 4n+3 th row, and the 8n+8 th grid line is connected with the even column of sub-pixels in the 4n+4 th row, and the n+5 th grid line belongs to the natural integer;
The driving method includes: the driving circuit board drives the array of sub-pixels in a dot inversion manner.
9. The method of claim 8, wherein the driving circuit board driving the array of subpixels in a dot inversion manner comprises: the 2N gate lines are scanned line by line in a current frame period, wherein the 2m-1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+1 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th gate line is scanned, the 4n+1 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, the 4n+2 nd column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+4 th gate line is scanned, the 4n+3 th column sub-pixel is charged with a data signal of a second polarity through the m-th data line when the 8n+3 th gate line is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column sub-pixel is scanned, and the 4n+1 th column sub-pixel is charged with a data signal of a first polarity through the m-th data line when the 8n+2 th column is scanned.
10. The method of claim 9, wherein the driving circuit board driving the array of subpixels in a dot inversion manner further comprises: the 2N gate lines are scanned line by line in a next frame period, wherein the 2n+1th gate line is charged with a data signal of a second polarity through the mth data line when the 8n+1th gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+1th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3gate line is scanned, the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+2th gate line is scanned, the 4n+3th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+5th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a first polarity through the mth data line when the 8n+3th gate line is scanned, and the 4n+2th column sub-pixel is charged with a data signal of a second polarity through the mth data line when the 8n+2th column is scanned.
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