CN116017980A - Method for manufacturing flash memory - Google Patents

Abstract

The invention discloses a method for manufacturing a flash memory, which comprises the following steps: step one, providing a semiconductor substrate. Step two, forming a first shallow trench isolation in the memory cell area, comprising the following steps: step 21, defining a forming area of the first shallow trench in the memory cell area. And step 22, etching to form a first shallow trench, wherein the first shallow trench defines a first active region in the memory cell region. The first active area is in a strip shape in a top view, the memory cells in the same column are formed in the same first active area, each memory cell in the same column is connected to a bit line in the same column, and a spacing area between the bit lines in two adjacent columns is determined by the width of the first shallow trench isolation. And step 23, performing first ion implantation to treat the inner side surface of the first shallow trench. And step 24, filling the oxide layer to form a first shallow trench isolation. Step 25, performing a first well implantation in the memory cell region and forming a first well region. The invention can reduce the programming crosstalk between two adjacent columns of memory cells.

Description

Method for manufacturing flash memory

Technical Field

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a Flash memory (Flash).

Background

When the memory Cell (Cell) of the existing NOR Flash technology is continuously reduced (shrnk) to 50nm/45nm along with the technology node from 0.13 mu m to 65nm/55n, the spacing area (space) of 2 cells corresponding to adjacent Bit Lines (BL) can be reduced due to excessive Cell size reduction, and the isolation performance can be deteriorated, so that electric leakage can be caused; wherein the bit lines are located above the active region, the size of the spacer region between the bit lines is also separated by Shallow Trench Isolation (STI). When one Cell selects Programming (PGM) for writing, bitline is high voltage, and the other adjacent Cell also generates a certain voltage on Bitline due to electric leakage, and since the adjacent cells in the same row share the same Word Line (WL), weak writing (Weak PGM) exists to change the adjacent Cell from the Erased (ERS) "1" state to Weak (Weak) "1", that is, program crosstalk (PGM Disturb) is generated to the adjacent Cell.

FIG. 1 is a flow chart of a method for manufacturing a conventional flash memory; the existing manufacturing method of the flash memory comprises the following steps:

step S101, cell AA-PH/ET. Cell represents a memory Cell, AA represents an active region, and AA is typically defined by forming shallow trench isolation; in step S101, a photolithography process is used to define a formation region of the Cell AA, and then etching is performed to form a shallow trench of the Cell region. PH denotes a photolithography process, and ET denotes an etching process.

Step S102, peripheral AA-PH/ET. The periphery represents a peripheral device; in step S102, a photolithography process is used to define a forming region of the periphery AA, and then etching is performed to form a shallow trench of the periphery region.

Step S103, STI linker & DEP; STI means shallow trench isolation, liner means an inner Liner oxide layer formed on the inner surface of the shallow trench, DEP means an oxide layer formed by a deposition process, and after the Liner is formed, the shallow trench is completely filled with the oxide layer formed by DEP deposition and the shallow trench isolation is formed.

Step S104, peripheral & Cell Well, i.e., performing Well implantation in the memory Cell region and the peripheral device region.

Step S105, cell Vt. Vt represents the threshold voltage, threshold voltage adjustment implants for the memory cells are made.

Step S106, tunOX; tunOX represents a tunnel oxide layer.

Step S107, FG; FG denotes a floating gate (floating gate).

Step S108, ONO; the ONO layer represents an oxide layer, a nitride layer, and an overlying layer of oxide layers.

Step S109, CG; CG denotes Control Gate (CG). The gate structure of the memory cell is formed by superposition of TunOX, FG, ONO and CG.

Step S110, peripheral GT; GT represents a gate (gate), i.e., a gate structure forming a peripheral device.

Step S111, periphery & Cell LDD. Indicating that Lightly Doped Drain (LDD) implants are performed to self-align the LDD regions of the memory cells and the LDD regions of the peripheral devices.

Step S112, SPACER1& 2. Representing the process of forming the sidewall, the sidewall typically includes a bilayer sidewall, SPACER1 representing a first layer of sidewall and SPACER 2 representing a second layer of sidewall.

Step S113, cell S/D; S/D represents the implantation of the source region and the drain region, i.e. the source and drain implantation of the memory cell.

Step S114, N+P+S/D; n+ represents N-type heavy doping of the peripheral NMOS, P+ represents P-type heavy doping of the peripheral PMOS, and S/D represents source drain injection.

Step S115, SAB. SAB represents the metal silicide blocking layer.

Step S116, CT. CT indicates the contact hole, which passes through the interlayer film. It is also necessary to form a first interlayer film before CT.

Step S117, BEOL. BEOL refers to a subsequent process including the formation of subsequent layers of films and front side metal layers after CT.

Disclosure of Invention

The invention aims to provide a manufacturing method of a flash memory, which can increase isolation between two rows of memory cells, thereby reducing programming crosstalk between two adjacent rows of memory cells.

In order to solve the technical problems, the manufacturing method of the flash memory provided by the invention comprises the following steps:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage unit area of a flash memory and a peripheral device area.

Step two, forming a first shallow trench isolation in the memory cell area, which comprises the following sub-steps:

step 21, defining a forming area of the first shallow trench in the memory cell area.

And step 22, etching to form a first shallow trench, wherein the first shallow trench defines a first active region in the memory cell region.

In a top view, the first active area is in a strip shape, memory cells in the same column are formed in the same first active area, each memory cell in the same column is connected to a bit line in the same column, and a spacing area between the bit lines in two adjacent columns is determined by the width of the first shallow trench isolation.

Step 23, performing a first ion implantation to form a first doped region in the semiconductor substrate at the bottom surface and the side surface of the first shallow trench.

And step 24, filling an oxide layer in the first shallow trench to form the first shallow trench isolation.

Step 25, performing first well injection in the storage unit region and forming a first well region; the junction depth of the first well region is larger than the depth of the first shallow trench isolation, the first shallow trench isolation can generate a blocking effect on the first well injection in the process of the first well injection, so that the doping concentration of the first well region at the bottom surface and the side surface of the first shallow trench is reduced, and the first doping region is used for compensating the doping concentration reduction of the first well region at the bottom surface and the side surface of the first shallow trench, thereby improving the isolation between adjacent first active regions, reducing the electric leakage between two adjacent columns of bit lines and reducing the programming crosstalk between adjacent memory cells.

A further improvement is that step 24 comprises the following substeps:

and 241, forming a double-layer lining oxide layer, and eliminating damage generated by the first ion implantation through the double-layer lining oxide layer.

And 242, depositing a shallow trench oxide layer to completely fill the first shallow trench, and forming the first shallow trench isolation by overlapping the liner oxide layer filled in the first shallow trench and the shallow trench oxide layer.

Further improvement is that the method further comprises:

forming a second shallow trench isolation in the peripheral device region, wherein the second shallow trench isolation comprises the following sub-steps:

and step 31, defining a forming area of a second shallow trench in the peripheral device region.

And step 32, etching to form a second shallow trench, wherein the second shallow trench defines a second active region in the peripheral device region.

And step 33, filling an oxide layer in the second shallow trench to form the second shallow trench isolation.

A further improvement is that after the step 23 is finished, the steps 31 and 32 are directly carried out, and after the step 32 is finished, the steps 24 and 33 are simultaneously carried out; step 25 is then performed.

In a further improvement, in step 23, the implanted impurities of the first ion implantation include phosphorus at an implantation dose of 1E12cm ^-2 ～5E13cm ^-2 。

Further improvement is that in step 241, the total thickness of the double layer liner oxide is

Further improvement is that the method further comprises:

and step four, forming a first grid structure of the memory cell in the memory cell area.

And fifthly, forming a second grid structure of the peripheral device in the peripheral device region.

And step six, forming side walls on the side surfaces of the first grid electrode structure and the second grid electrode structure.

And seventh, forming a source region and a drain region of each storage unit in the storage unit region.

And eighth, forming a source region and a drain region of the peripheral device in the outer ring device region.

In the fourth step, the first gate structure includes a first tunneling dielectric layer, a second polysilicon floating gate, a third control dielectric layer and a fourth polysilicon control gate which are sequentially stacked.

In the fifth step, the second gate structure includes a first gate dielectric layer and a second polysilicon gate which are sequentially stacked.

The further improvement is that the first tunneling dielectric layer adopts an oxide layer, the third control dielectric layer adopts an ONO layer, and the ONO layer is an oxide layer, a nitride layer and an oxide layer superposition layer.

And the first gate dielectric layer is made of an oxide layer.

Further improvement is that after the step five is completed and before the step six, the method further comprises the step of performing LDD injection to form an LDD region of the memory cell in a self-aligned mode on the side face of the first grid structure and forming an LDD region of the peripheral device in a self-aligned mode on the side face of the second grid structure.

The further improvement is that the side wall is formed by overlapping a first layer of side wall and a second layer of side wall.

A further improvement is that after the step eight, the method further comprises:

and step nine, forming a metal silicide blocking layer and forming the metal silicide in a self-aligned mode.

And step ten, forming an interlayer film, a contact hole and a front metal layer and patterning the front metal layer.

Further improvement is that step 25 further comprises the steps of:

performing a second well implant in the peripheral device region;

after the completion of step 25 and before step four, the method further comprises:

a threshold voltage adjustment implant of the memory cell is performed.

A further improvement is that the flash memory is a NOR flash memory.

In a further improvement, in a top view, in a fourth step, the fourth polysilicon control gates of the first gate structures of the memory cells in the same row are connected together and form a polysilicon row.

After the step ten is completed, the fourth polysilicon control gate of the first gate structure of each memory cell of the same row is connected to the same word line formed by patterning the front metal layer, and the drain region of the memory cell of the same column is connected to the same bit line formed by patterning the front metal layer through a contact hole corresponding to the top.

According to the invention, after the first shallow trench in the memory cell region is etched and before filling, the first ion implantation is added, impurities can be implanted into the inner side surface of the first shallow trench by the first ion implantation, and the implanted impurities, namely the first doped region, can increase the isolation performance of the first shallow trench isolation.

According to the invention, in the filling process of the first shallow trench, the lining oxide layer is arranged as the double-layer lining oxide layer, and the double-layer lining oxide layer can eliminate the damage caused by the first ion implantation, so that the isolation performance of the first shallow trench isolation can be further improved.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a flow chart of a method of manufacturing a conventional flash memory;

FIG. 2 is a flow chart of a method of manufacturing a flash memory according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method for manufacturing a flash memory according to a preferred embodiment of the present invention;

FIG. 4A is a diagram showing an array structure in a memory cell region of a flash memory according to a method for manufacturing the flash memory according to the preferred embodiment of the present invention;

FIG. 4B is a cross-sectional view taken along line AA in FIG. 4A;

FIG. 4C is a cross-sectional view taken along line BB in FIG. 4A;

FIG. 5 is a diagram showing a failure bit number (FBC) test of a memory cell region of a flash memory formed by the manufacturing method of the flash memory according to the prior art and the preferred embodiment of the present invention.

Detailed Description

FIG. 2 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention; FIG. 3 is a flow chart showing a method for manufacturing a flash memory according to a preferred embodiment of the invention; FIG. 4A is a diagram showing an array structure in a memory cell region of a flash memory according to a method for manufacturing the flash memory according to a preferred embodiment of the present invention; as shown in fig. 4B, a cross-sectional structure along the AA line in fig. 4A; FIG. 4C is a cross-sectional view taken along line BB in FIG. 4A; the manufacturing method of the flash memory comprises the following steps:

step one, a semiconductor substrate 201 is provided, and a memory cell area and a peripheral device area of a flash memory are simultaneously included on the semiconductor substrate 201.

Step two, forming a first shallow trench isolation 106 in the memory cell region, including the following sub-steps:

step 21, defining a forming region of the first shallow trench 212 in the memory cell region. In some preferred embodiments, the formation region of the first shallow trench 212 in the memory cell region is defined by a photolithography process

Step 22, etching is performed to form a first shallow trench 212, where the first shallow trench 212 defines the first active region 101 in the memory cell region.

Step 21 and step 22 correspond to step S201, cell AA-PH/ET in FIG. 3. Cell represents a memory Cell, AA represents an active region, and AA in the memory Cell region is the first active region 101. In step S201, a photolithography process is used to define a formation region of the Cell AA, and then etching is performed to form a shallow trench of the Cell region. PH denotes a photolithography process, and ET denotes an etching process.

As shown in fig. 4A, the first active area 101 is in a stripe shape in a top view, memory cells in the same column are formed in the same first active area 101, each memory cell in the same column is connected to a bit line 211 in the same column, and a space between the bit lines 211 in two adjacent columns is determined by a width of the first shallow trench isolation 106.

In step 23, as shown in fig. 4C, a first ion implantation is performed to form a first doped region 213 in the semiconductor substrate 201 at the bottom surface and the side of the first shallow trench 212.

In some preferred embodiments, the first ion implantation implant impurities comprise phosphorus at an implant dose of 1E12cm ^-2 ～5E13cm ^-2 。

Step 23 corresponds to step S202, ISO IMP in fig. 3. ISO means isolation, i.e. the first shallow trench isolation, IMP means the first ion implantation.

Step 24, filling an oxide layer in the first shallow trench 212 to form the first shallow trench isolation 106.

In some preferred embodiments, step 24 includes the following substeps:

step 241, forming a double-layer liner oxide layer 214, and eliminating the damage generated by the first ion implantation by double-layer liner oxide layer 214.

More preferably, the dual layer liner oxide 214 has a total thickness of

Step 242, depositing a shallow trench oxide layer 215 to completely fill the first shallow trench 212, and superposing the liner oxide layer 214 filled in the first shallow trench 212 and the shallow trench oxide layer 215 to form the first shallow trench isolation 106.

Step 25, performing first well injection in the storage unit region and forming a first well region; the junction depth of the first well region is greater than the depth of the first shallow trench 212 isolation 106, and during the first well implantation, the first shallow trench 212 isolation 106 may act as a barrier to the first well implantation, such that the doping concentration of the first well region at the bottom surface and the side surface of the first shallow trench 212 is reduced, and the first doping region 213 is used to compensate for the reduction of the doping concentration of the first well region at the bottom surface and the side surface of the first shallow trench 212, thereby improving the isolation between adjacent first active regions 101, reducing the leakage between adjacent two columns of bit lines and thereby reducing the program crosstalk between adjacent memory cells.

In some embodiments, step 25 further comprises the steps of:

a second well implant is performed in the peripheral device region. This step corresponds to step S205 in fig. 3, peripheral & Cell Well, i.e., well implantation is performed in the memory Cell region and the peripheral device region.

After the completion of step 25 and before the subsequent step four, the method further comprises:

a threshold voltage adjustment implant of the memory cell is performed. This step corresponds to step S206, cell Vt in fig. 3. Vt represents the threshold voltage, threshold voltage adjustment implants for the memory cells are made.

In the embodiment of the invention, the method further comprises the following steps:

step three, forming a second shallow trench isolation (not shown) in the peripheral device region, including the following sub-steps:

and step 31, defining a forming area of a second shallow trench in the peripheral device region. In some preferred embodiments, a photolithographic process is used to define the formation region of the second shallow trench in the peripheral device region.

And step 32, etching to form a second shallow trench, wherein the second shallow trench defines a second active region in the peripheral device region.

Step 31 and step 32 correspond to step S203, peripheral AA-PH/ET in fig. 3. The periphery represents a peripheral device; in step S203, a photolithography process is used to define a forming region of the periphery AA, and then etching is performed to form the second shallow trench of the peripheral region.

And step 33, filling an oxide layer in the second shallow trench to form the second shallow trench isolation.

In some preferred embodiments, steps 31 and 32 are performed directly after step 23 is completed, and steps 24 and 33 are performed simultaneously after step 32 is completed. Step 25 is then performed.

The steps 24 and 33 performed simultaneously correspond to step S204, STI Double link & DEP in fig. 3. STI means shallow trench isolation, liner means a Liner oxide layer formed on the inner surface of the shallow trench, double Liner means a Double Liner oxide layer, and DEP means an oxide layer formed by a deposition process. After the Liner is formed, the shallow trenches are completely filled with oxide layers formed by DEP deposition and corresponding shallow trench isolation is formed.

And step four, forming a first grid structure of the memory cell in the memory cell area.

In some embodiments, as shown in fig. 4B, the first gate structure includes a first tunneling dielectric layer 202, a second polysilicon floating gate 203, a third control dielectric layer 204, and a fourth polysilicon control gate 205 that are stacked in sequence.

In some preferred embodiments, the first tunneling dielectric layer 202 is an oxide layer, and the third control dielectric layer 204 is an ONO layer, which is an oxide layer, a nitride layer, and an oxide layer stack. In fig. 3, the step of forming the first gate structure includes:

step S207, tunOX; tunOX represents a tunneling oxide layer, i.e., the first tunneling dielectric layer is formed.

Step S208, FG; FG means a floating gate, i.e. forming said second polysilicon floating gate.

Step S209, ONO; the formation of the third control dielectric layer consisting of an ONO layer is shown.

Step S210, CG; CG denotes the control gate, i.e. the fourth polysilicon control gate is formed.

And fifthly, forming a second grid structure of the peripheral device in the peripheral device region.

The second gate structure comprises a first gate dielectric layer and a second polysilicon gate which are sequentially overlapped.

In some preferred embodiments, the first gate dielectric layer is formed of an oxide layer.

In fig. 3, the step of forming the second gate structure includes:

step S211, peripheral GT; GT represents the gate, i.e. the second gate structure.

In some preferred embodiments, the method further comprises:

an LDD implant is performed to self-align the LDD region 207 of the memory cell on the side of the first gate structure and to self-align the LDD region 207 of the peripheral device on the side of the second gate structure. This step corresponds to step S212, periphery & Cell LDD in fig. 3.

And step six, forming side walls 206 on the side surfaces of the first gate structure and the second gate structure.

In some preferred embodiments, the sidewall 206 is formed by stacking a first sidewall 2061 and a second sidewall 2062. In fig. 3, step six corresponds to steps S213, space 1&2; space represents a side wall, space 1 represents a first layer of side wall, and space 2 represents a second layer of side wall.

Step seven, a source region 208 and a drain region 209 of each memory cell are formed in the memory cell region. In FIG. 3, step seven corresponds to step S214, cell S/D; S/D represents the implantation of the source region and the drain region, i.e. the source and drain implantation of the memory cell.

And step eight, forming a source region (not shown) and a drain region (not shown) of the peripheral device in the outer ring device region. In FIG. 3, step eight corresponds to steps S215, N+P+S/D; n+ represents N-type heavy doping of the peripheral NMOS, P+ represents P-type heavy doping of the peripheral PMOS, and S/D represents source drain injection.

Step nine, forming a metal silicide 210 barrier layer and self-aligning to form the metal silicide 210. In fig. 3, step nine corresponds to steps S216, SAB. SAB represents the metal silicide blocking layer.

Step ten, an interlayer film and a contact hole 103 are formed. This step corresponds to step S216, CT in fig. 3. CT indicates the contact hole, which passes through the interlayer film. It is also necessary to form a first interlayer film before CT.

And continuing to form the following interlayer films and the front metal layer and patterning the front metal layer. This step corresponds to step S218, BEOL in fig. 3. BEOL refers to a subsequent process including the formation of subsequent layers of films and front side metal layers after CT.

In the embodiment of the invention, the flash memory is a NOR flash memory.

As shown in fig. 4A, in a top view, in a fourth step, the fourth polysilicon control gates 205 of the first gate structures of the memory cells of the same row are connected together and constitute a polysilicon row 102.

After step ten is completed, the fourth polysilicon control gate 205 of the first gate structure of each of the memory cells of the same row is connected to the same word line patterned by the front side metal layer. The drain regions of the memory cells of the same column are connected to the same bit line 211 patterned by the front side metal layer through the corresponding contact holes 103 at the top.

In fig. 4A, the area indicated by the dashed box 104 is the formation area of one of the memory cells. The area indicated by the dashed box 105 is the formation area of the second polysilicon floating gate 203, which is the intersection area between the polysilicon row 102 and the first active region 101.

In the embodiment of the invention, after the etching of the first shallow trench 212 in the memory cell region is completed and before the filling, the first ion implantation is added, the first ion implantation can implant impurities into the inner side surface of the first shallow trench 212, the implanted impurities, namely, the first doped region 213, can increase the isolation performance of the first shallow trench isolation 106, mainly because the first doped region 213 can compensate the reduced doping concentration of the first well region of the memory cell at the bottom surface and the side surface of the first shallow trench isolation 106, the isolation between the adjacent first active regions 101 can be improved, namely, the isolation performance between the two adjacent columns of bit lines 211 is improved, the electric leakage between the two columns of bit lines is reduced, and when Programming (PGM) is performed, the high voltage of the bit lines 211 of the programming unit can be prevented from being transferred to the adjacent bit lines 211, thereby preventing the weak writing on the adjacent memory cell, and thus the programming crosstalk between the two adjacent columns of memory cells can be reduced.

In the embodiment of the invention, in the filling process of the first shallow trench 212, the liner oxide layer 214 is set to be a double-layer liner oxide layer 214, and the double-layer liner oxide layer 214 can eliminate the damage caused by the first ion implantation, so that the isolation performance of the first shallow trench isolation 106 can be further improved.

In the embodiment of the invention, the adjacent Cell PGM Disturb is improved by adding Cell AA STI Isolation (ISO) IMP after the conventional Cell AA Photo (PH)/Etch (ET) process. Then performing peripheral AA Photo/Etch process, STI Double Liner & STI-DEP process, cell and peripheral Well ion implantation process, cell VT adjustment, tunnel Oxide, FG, ONO, CG and other Cell related processes; gate process at periphery, followed by periphery and Cell LDD ion implantation process; then SPACER1&2 process and Cell S/D ion implantation; finally, peripheral S/D ion implantation, SAB, CT process and BEOL metal routing process are carried out. The embodiment of the invention can improve PGM Disturb of NOR Flash products in shrinking (spring) Cell process, and can provide a scheme for developing other Memory products in small technology node process and providing Cell AA & STI isolation.

As shown in fig. 5, the FBC test chart of the memory cell area of the flash memory formed by the conventional and preferred embodiment flash memory manufacturing method of the present invention is shown with the horizontal axis being the Bias voltage (Bias) of the word line WL and the vertical axis being the FBC value. Wherein curve 301 is the FBC test curve of the memory cell area of the flash memory that is not programmed after erase; curve 302 is the FBC test curve of the memory cell area of the flash memory formed by the method of the preferred embodiment of the present invention after erasing and after programming; curve 302 is the FBC test curve of the memory cell area of the flash memory formed by the prior art method after erasing and programming; it can be seen that curve 302 and curve 301 are substantially coincident, with no offset; curve 303 is shifted to the right by 0.4V, i.e., shift 0.4V, from curve 301. As can be seen by comparing curves 302 and 303, there is substantially no program cross-talk in the flash memory according to the preferred embodiment of the present invention.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (15)

1. A method of manufacturing a flash memory, comprising the steps of:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage unit area of a flash memory and a peripheral device area;

step two, forming a first shallow trench isolation in the memory cell area, which comprises the following sub-steps:

step 21, defining a forming area of a first shallow trench in the memory cell area;

step 22, etching to form a first shallow trench, wherein the first shallow trench defines a first active region in the memory cell region;

on a top view, the first active area is in a strip shape, memory cells in the same column are formed in the same first active area, each memory cell in the same column is connected to a bit line in the same column, and a spacing area between the bit lines in two adjacent columns is determined by the width of the first shallow trench isolation;

step 23, performing first ion implantation to form a first doped region in the semiconductor substrate at the bottom surface and the side surface of the first shallow trench;

step 24, filling an oxide layer in the first shallow trench to form the first shallow trench isolation;

step 25, performing first well injection in the storage unit region and forming a first well region; the junction depth of the first well region is larger than the depth of the first shallow trench isolation, the first shallow trench isolation can generate a blocking effect on the first well injection in the process of the first well injection, so that the doping concentration of the first well region at the bottom surface and the side surface of the first shallow trench is reduced, and the first doping region is used for compensating the doping concentration reduction of the first well region at the bottom surface and the side surface of the first shallow trench, thereby improving the isolation between adjacent first active regions, reducing the electric leakage between two adjacent columns of bit lines and reducing the programming crosstalk between adjacent memory cells.

2. The method of manufacturing a flash memory according to claim 1, wherein step 24 comprises the sub-steps of:

step 241, forming a double-layer lining oxide layer, and eliminating damage generated by the first ion implantation through the double-layer lining oxide layer;

and 242, depositing a shallow trench oxide layer to completely fill the first shallow trench, and forming the first shallow trench isolation by overlapping the liner oxide layer filled in the first shallow trench and the shallow trench oxide layer.

3. The method of manufacturing a flash memory of claim 2, further comprising:

forming a second shallow trench isolation in the peripheral device region, wherein the second shallow trench isolation comprises the following sub-steps:

step 31, defining a forming area of a second shallow trench in the peripheral device region;

step 32, etching to form a second shallow trench, wherein the second shallow trench defines a second active region in the peripheral device region;

and step 33, filling an oxide layer in the second shallow trench to form the second shallow trench isolation.

4. The method for manufacturing a flash memory according to claim 3, wherein: after step 23 is completed, step 31 and step 32 are directly performed, and after step 32 is completed, step 24 and step 33 are simultaneously performed, and then step 25 is performed.

5. The method for manufacturing a flash memory according to claim 2, wherein: in step 23, the first ion implantation impurity comprises phosphorus with an implantation dose of 1E12cm ^-2 ～5E13cm ^-2 。

6. The method for manufacturing a flash memory according to claim 2, wherein: in step 241, the total thickness of the double layer liner oxide is

7. The method of manufacturing a flash memory of claim 4, further comprising:

forming a first grid structure of the memory unit in the memory unit area;

forming a second grid structure of the peripheral device in the peripheral device region;

forming side walls on the side surfaces of the first grid electrode structure and the second grid electrode structure;

step seven, forming a source region and a drain region of each storage unit in the storage unit region;

and eighth, forming a source region and a drain region of the peripheral device in the outer ring device region.

8. The method for manufacturing a flash memory according to claim 7, wherein: in the fourth step, the first gate structure comprises a first tunneling dielectric layer, a second polysilicon floating gate, a third control dielectric layer and a fourth polysilicon control gate which are sequentially overlapped;

in the fifth step, the second gate structure includes a first gate dielectric layer and a second polysilicon gate which are sequentially stacked.

9. The method for manufacturing a flash memory according to claim 8, wherein: the first tunneling dielectric layer adopts an oxide layer, the third control dielectric layer adopts an ONO layer, and the ONO layer is an oxide layer, a nitride layer and an oxide layer superposition layer;

and the first gate dielectric layer is made of an oxide layer.

10. The method for manufacturing a flash memory according to claim 7, wherein: after the step five is completed and before the step six, the method further comprises the step of performing LDD injection to form an LDD region of the memory cell in a self-aligned mode on the side face of the first grid structure and forming an LDD region of the peripheral device in a self-aligned mode on the side face of the second grid structure.

11. The method for manufacturing a flash memory according to claim 7, wherein: the side wall is formed by overlapping a first layer of side wall and a second layer of side wall.

12. The method for manufacturing a flash memory according to claim 9, further comprising, after the eighth step:

step nine, forming a metal silicide blocking layer and forming metal silicide in a self-aligned manner;

and step ten, forming an interlayer film, a contact hole and a front metal layer and patterning the front metal layer.

13. The method for manufacturing flash memory according to claim 7, wherein the step 25 further comprises the steps of:

performing a second well implant in the peripheral device region;

after the completion of step 25 and before step four, the method further comprises:

a threshold voltage adjustment implant of the memory cell is performed.

14. The method for manufacturing a flash memory according to claim 12, wherein: the flash memory is NOR flash memory.

15. The method for manufacturing a flash memory according to claim 14, wherein: in a top view, in a fourth step, the fourth polysilicon control gates of the first gate structures of the memory cells in the same row are connected together and form a polysilicon row;

after the step ten is completed, the fourth polysilicon control gate of the first gate structure of each memory cell of the same row is connected to the same word line formed by patterning the front metal layer, and the drain region of the memory cell of the same column is connected to the same bit line formed by patterning the front metal layer through a contact hole corresponding to the top.

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