CN116016057A - Method, device, processor and storage medium for realizing random interpolation and high sampling processing of parallel architecture based on optimized frequency response - Google Patents
Method, device, processor and storage medium for realizing random interpolation and high sampling processing of parallel architecture based on optimized frequency response Download PDFInfo
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Abstract
The invention relates to a method for realizing random interpolation and high sampling processing of a parallel architecture based on optimized frequency response, wherein the method comprises the following steps: after receiving N pairs of IQ data to be converted, the upper computer performs fast Fourier transform to generate N pairs of frequency domain complex data F iq0 [N]The method comprises the steps of carrying out a first treatment on the surface of the Obtain the sampling rate f nearest to the original data sa1 Is the sampling rate f of (2) sa2 The method comprises the steps of carrying out a first treatment on the surface of the Obtaining the length Ls of interpolation or extraction required by the system, and carrying out corresponding processing; inputting data and judging whether the interpolation number is larger than x2; the first Fifo first-in first-out queue is entered for interpolation processing, and the second Fifo first-in first-out queue is entered for interpolation processing; and sending the processed data to a DAC chip according to JESD204B protocol, and outputting a corresponding analog baseband signal by the DAC chip. The invention also relates to a corresponding device, a processor and a storage medium thereof. The method and the device of the invention are adopted,The processor and the storage medium thereof realize the conversion of sampling rate by utilizing an FPGA real-time interpolation mode, convert data into analog signals, and the data rate can be more than 2 Gs/s.
Description
Technical Field
The invention relates to the technical field of digital communication processing, in particular to the technical field of vector modulation signal interpolation processing under high sampling rate, and specifically relates to a method, a device, a processor and a computer readable storage medium for realizing random interpolation and high sampling processing of a parallel architecture based on optimized frequency response.
Background
In a common baseband transmission system, the problem of adopting rate conversion is encountered in order to meet different communication systems and application situations. Common ways are implemented by either FPGA lagrangian arbitrary interpolation, half-band interpolation, CIC interpolation, or by software interpolation algorithms. However, in order to meet the requirement of a high-bandwidth transmission system, the sampling rate is generally higher, and if the low sampling rate is considered, the interpolation stage number is huge, so that the cost is further increased; if the whole interpolation process is processed by the software system, the software platform is required to have excellent performance and occupy several tens of GB of memory, the algorithm is extremely low in realization efficiency, and the depth of a hardware storage part is required to be extremely large, so that the method is not practical. If the FPGA is used for all processing, lagrange interpolation, CIC and half-band hierarchical algorithm are generally adopted, and parallel data processing is generally carried out on a high-sampling transmission platform, so that required algorithm resources are increased rapidly, the algorithm is obvious in frequency response deterioration of a large-bandwidth signal, and the method is not suitable for interpolation scenes with high bandwidth proportion and sampling rate.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a method, a device, a processor and a computer readable storage medium thereof for realizing random interpolation and high sampling processing of a parallel architecture based on optimized frequency response.
In order to achieve the above object, the method, the device, the processor and the computer readable storage medium thereof for implementing any interpolation and high sampling processing of a parallel architecture based on optimized frequency response according to the present invention are as follows:
the method for realizing random interpolation and high sampling processing of the parallel architecture based on the optimized frequency response is mainly characterized by comprising the following steps:
(1) In a transmitting system, after receiving N pairs of IQ data to be converted, an upper computer performs fast Fourier transform to generate N pairs of frequency domain complex data F iq0 [N]；
(2) Sampling rate f of system original data sa1 And the sampling rate actually required by the systemf sa0 Performing relative operation to the actually required sampling rate f of the system sa0 Acquiring the sampling rate f of the original data closest to the system in a manner of dividing 2 sa1 Is the sampling rate f of (2) sa2 ；
(3) Obtaining the length Ls of interpolation or extraction required by the current system, and carrying out corresponding processing;
(4) Inputting data, judging whether the data is greater than 2 times of interpolation, if so, entering the step (5), otherwise, entering the step (6);
(5) Entering a first Fifo first-in first-out queue for interpolation processing;
(6) Entering a second Fifo first-in first-out queue for interpolation processing;
(7) And sending the processed data to a DAC chip according to JESD204B protocol, and outputting a corresponding analog baseband signal by the DAC chip.
Preferably, in the step (1), the fast fourier transform is performed according to the following formula:
preferably, the step (3) calculates the length Ls of the required interpolation or extraction according to the following formula:
when Ls is>At 0, for F iq0 [N]Intermediate position of array
Performing interpolation on complex numbers of Ls to 0; when Ls is<At 0, for F iq0 [N]Intermediate position +.>
And extracting Ls pair complex data.
Preferably, the step (5) specifically includes the following steps:
(5.1) judging whether the interpolation multiple required by the current data is greater than 4 times of interpolation, if not, entering a step (5.2); if yes, single-channel half-band interpolation processing is carried out, whether the interpolation multiple required by the current data is greater than 8 times interpolation, 16 times interpolation, 32 times interpolation, 64 times interpolation, 128 times interpolation or more than 256 times interpolation and less than 2048 times interpolation is respectively judged, if not, a step (5.2) is carried out, and if yes, corresponding single-channel half-band interpolation processing is carried out;
(5.2) selecting a 1 st single-channel filter module to process a data output channel when the interpolation is less than or equal to 4 times of interpolation; when the interpolation is 8, selecting a 2 nd single-channel filter module to process a data output channel; interpolation is 16, and a 3 rd single-channel filter module is selected to process a data output channel; interpolation is 32, and a 4 th single-channel filter module is selected to process a data output channel; interpolation is 64, and a 5 th single-channel filter module is selected to process a data output channel; interpolation is 128, and a 6 th single-channel filter module is selected to process a data output channel; interpolation is 256, and a 7 th single-channel filter module is selected to process a data output channel; interpolation is 512, and the 8 th single-channel filter module is selected to process a data output channel; a 7 th single-channel filter module is selected by default to process a data output channel;
and (5.3) after the selection of the step (5.2) is completed, adopting a 1-channel to 2-channel parallel output half-band filter for processing, and entering the step (6).
Preferably, the step (6) specifically includes the following steps:
(6.1) selecting the data after the processing;
(6.2) converting the one-channel parallel architecture into a two-channel parallel architecture to output a half-band filter;
(6.3) performing arbitrary interpolation processing using a CIC interpolation filter.
The device for realizing random interpolation and high sampling processing of parallel architecture based on optimized frequency response is mainly characterized by comprising the following components:
a processor configured to execute computer-executable instructions;
and a memory storing one or more computer-executable instructions which, when executed by the processor, implement the steps of the method for implementing any interpolation and high sampling processing of a parallel architecture based on optimized frequency response described above.
The processor for realizing the parallel architecture random interpolation and high sampling processing based on the optimized frequency response is mainly characterized in that the processor is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the parallel architecture random interpolation and high sampling processing based on the optimized frequency response are realized.
The computer readable storage medium is mainly characterized in that the computer program is stored thereon, and the computer program can be executed by a processor to realize the steps of the method for realizing the random interpolation and the high sampling processing of the parallel architecture based on the optimized frequency response.
The method, the device, the processor and the computer readable storage medium thereof for realizing random interpolation and high sampling processing of the parallel architecture based on the optimized frequency response have the main purposes of completing fractional interpolation, reducing FPGA logic resources and reducing deteriorated frequency response. And the FPGA utilizes DSP and memory unit resources to complete any integer interpolation mode, and the framework is divided into parallel architecture data processing half-band interpolation and CIC interpolation combination. And realizing conversion of sampling rate by utilizing an FPGA real-time interpolation mode. The high-speed DAC converts the data into analog signals by JESD204B protocol, and the data rate can be up to more than 2 Gs/s.
Drawings
Fig. 1 is a schematic flow chart of FPGA cascade interpolation transmission based on the method for implementing parallel architecture arbitrary interpolation and high sampling processing based on optimized frequency response in the present invention.
FIG. 2 is a schematic diagram of the software arbitrary review process of the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, a further description will be made below in connection with specific embodiments.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1, the method for implementing arbitrary interpolation and high sampling processing of a parallel architecture based on optimized frequency response includes the following steps:
(1) In a transmitting system, after receiving N pairs of IQ data to be converted, an upper computer performs fast Fourier transform to generate N pairs of frequency domain complex data F iq0 [N]；
(2) Sampling rate f of system original data sa1 And the sampling rate f actually required by the system sa0 Performing relative operation to the actually required sampling rate f of the system sa0 Acquiring the sampling rate f of the original data closest to the system in a manner of dividing 2 sa1 Is the sampling rate f of (2) sa2 ；
(3) Obtaining the length Ls of interpolation or extraction required by the current system, and carrying out corresponding processing;
(4) Inputting data, judging whether the required interpolation multiple is greater than 2 times of interpolation, if so, entering a step (5), otherwise, entering a step (6);
(5) Entering a first Fifo first-in first-out queue for interpolation processing;
(6) Entering a second Fifo first-in first-out queue for interpolation processing;
(7) And sending the processed data to a DAC chip according to JESD204B protocol, and outputting a corresponding analog baseband signal by the DAC chip.
As a preferred embodiment of the present invention, in the step (1), the fast fourier transform is performed according to the following formula:
as a preferred embodiment of the present invention, said step (3) calculates the required interpolated or extracted length Ls according to the following formula:
when Ls is>At 0, for F iq0 [N]Intermediate position of array
Performing interpolation on complex numbers of Ls to 0; when Ls is<At 0, for F iq0 [N]Intermediate position +.>
And extracting Ls pair complex data.
As a preferred embodiment of the present invention, the step (5) specifically includes the steps of:
(5.1) judging whether the interpolation multiple required by the current data is greater than 4 times of interpolation, if not, entering a step (5.2); if yes, single-channel half-band interpolation processing is carried out, whether the interpolation multiple required by the current data is greater than 8 times interpolation, 16 times interpolation, 32 times interpolation, 64 times interpolation, 128 times interpolation or more than 256 times interpolation and less than 2048 times interpolation is respectively judged, if not, a step (5.2) is carried out, and if yes, corresponding single-channel half-band interpolation processing is carried out;
(5.2) selecting a 1 st single-channel filter module to process a data output channel when the interpolation is less than or equal to 4 times of interpolation; when the interpolation is 8, selecting a 2 nd single-channel filter module to process a data output channel; interpolation is 16, and a 3 rd single-channel filter module is selected to process a data output channel; interpolation is 32, and a 4 th single-channel filter module is selected to process a data output channel; interpolation is 64, and a 5 th single-channel filter module is selected to process a data output channel; interpolation is 128, and a 6 th single-channel filter module is selected to process a data output channel; interpolation is 256, and a 7 th single-channel filter module is selected to process a data output channel; interpolation is 512, and the 8 th single-channel filter module is selected to process a data output channel; a 7 th single-channel filter module is selected by default to process a data output channel;
and (5.3) after the selection of the step (5.2) is completed, adopting a 1-channel to 2-channel parallel output half-band filter for processing, and entering the step (6).
As a preferred embodiment of the present invention, the step (6) specifically includes the steps of:
(6.1) selecting the data after the processing;
(6.2) converting the one-channel parallel architecture into a two-channel parallel architecture to output a half-band filter;
(6.3) performing arbitrary interpolation processing using a CIC interpolation filter.
In one embodiment of the present invention, in the transmitting system, after the upper computer receives the N pairs of IQ data to be converted, the upper computer performs a fast fourier transform (according to equation 1)) to generate N pairs of frequency domain complex data F iq0 [N]According to the sampling rate f of the original data sa1 And the sampling rate f actually required by the system sa0 Performing relative operation to sample rate f of system sa0 Acquiring the closest to the original data sampling rate f in a manner of dividing 2 sa1 Is the sampling rate f of (2) sa2 Obtaining the desired interpolated or extracted length Ls according to equation 2), when Ls>At 0, for F iq0 [N]Intermediate position of array
Performing interpolation on complex numbers of Ls to 0; when Ls is<At 0, for F iq0 [N]Intermediate position +.>
And extracting Ls pair complex data.
After the above operation, frequency domain data F is generated iq1 [M]Then the sample rate f is generated through fast Fourier transform sa2 Is a block of IQ data. And issuing the IQ data to hardware, and performing the next processing in the low-level HDL logic code.
Equation 1):
；k＝0,1,2,……,N-1
equation 2):
to minimize the degradation of interpolation to frequency response, half-band interpolation and CIC interpolation combination is processed in the underlying HDL logic code using parallel architecture data; however, because the DSP resources of the multichannel half-band interpolation FIR are multiple of the single channel and cannot be similar to the single-channel optimization coefficient multiplication architecture, 1 single-channel to double-channel interpolation FIR and 1 double-channel to 4-channel interpolation FIR are adopted, and 9 single-channel half-band interpolation filters are adopted to finish the interpolation filter with the maximum interpolation of 512, so that the resource consumption is reduced from 2232 of the original theory to 436, and the DSP resource quantity of about 80.5% is optimized. The half-band scheme is as follows:
when the interpolation is 2, only a two-channel parallel architecture is used for converting into a four-channel parallel architecture interpolation filter;
when the interpolation is 4, converting the one-channel parallel architecture into two-channel parallel architecture channel interpolation and converting the two-channel parallel architecture into four-channel parallel architecture channel interpolation;
when the interpolation is 8, the single-channel-order 58 half-band filter is used for carrying out the channel interpolation from the one-channel parallel architecture to the two-channel parallel architecture and the two-channel parallel architecture to the four-channel parallel architecture.
When the interpolation is 16, the single-channel order is 58 half-band interpolation filter, the single-channel order is 34 half-band interpolation filter, and finally the single-channel parallel architecture is converted into two-channel parallel architecture channel interpolation and the two-channel parallel architecture is converted into four-channel parallel architecture channel interpolation.
When the interpolation is 32, a single-channel order is 58 half-band interpolation filter, a single-channel order is 34 half-band interpolation filter, a single-channel order is 22 half-band interpolation filter, and finally the single-channel parallel architecture-to-two-channel parallel architecture-to-four-channel interpolation is performed.
When the interpolation is 64, the single-channel order is 58 half-band interpolation filter, the single-channel order is 34 half-band interpolation filter, the two single-channel orders are 22 half-band interpolation filter, and finally the two-channel parallel architecture channel interpolation and the two-channel parallel architecture channel interpolation are converted into four-channel parallel architecture channel interpolation.
When the interpolation is 128, the single-channel order is 58 half-band interpolation filter, the single-channel order is 34 half-band interpolation filter, the two single-channel orders are 22 half-band interpolation filter, the single-channel order is 10 half-band interpolation filter, and finally the single-channel parallel architecture to two-channel parallel architecture channel interpolation and the two-channel parallel architecture to four-channel parallel architecture channel interpolation are carried out.
When the interpolation is 256, a single-channel-order 58-half-band interpolation filter is adopted, then a single-channel-order 34-half-band interpolation filter is adopted, two single-channel-order 22-half-band interpolation filters are adopted, then two single-channel-order 10-half-band interpolation filters are adopted, and finally one-channel parallel architecture to two-channel parallel architecture channel interpolation and two-channel parallel architecture to four-channel parallel architecture channel interpolation are adopted.
When the interpolation is 512, a single-channel-order 58-half-band interpolation filter is adopted, then a single-channel-order 34-half-band interpolation filter is adopted, two single-channel-order 22-half-band interpolation filters are adopted, then three single-channel-order 10-half-band interpolation filters are adopted, and finally one-channel parallel architecture to two-channel parallel architecture channel interpolation and two-channel parallel architecture to four-channel parallel architecture channel interpolation are adopted.
When the interpolation is more than 512, processing half-band interpolation filter cascade according to the interpolation 256, and then connecting CIC filters of any integer interpolation parallel architecture;
and then the processed data is sent to a DAC chip according to JESD204B protocol, and the DAC chip outputs corresponding analog baseband signals.
The device for realizing random interpolation and high sampling processing of parallel architecture based on optimized frequency response comprises:
a processor configured to execute computer-executable instructions;
and a memory storing one or more computer-executable instructions which, when executed by the processor, implement the steps of the method for implementing any interpolation and high sampling processing of a parallel architecture based on optimized frequency response described above.
The processor for realizing the parallel architecture random interpolation and high sampling processing based on the optimized frequency response is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the steps of the method for realizing the parallel architecture random interpolation and high sampling processing based on the optimized frequency response are realized.
The computer readable storage medium has stored thereon a computer program executable by a processor to perform the steps of the method for implementing any interpolation and high sampling processing of a parallel architecture based on optimized frequency response as described above.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution device.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the program when executed includes one or a combination of the steps of the method embodiments.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
The method, the device, the processor and the computer readable storage medium thereof for realizing random interpolation and high sampling processing of the parallel architecture based on the optimized frequency response have the main purposes of completing fractional interpolation, reducing FPGA logic resources and reducing deteriorated frequency response. And the FPGA utilizes DSP and memory unit resources to complete any integer interpolation mode, and the framework is divided into parallel architecture data processing half-band interpolation and CIC interpolation combination. And realizing conversion of sampling rate by utilizing an FPGA real-time interpolation mode. The high-speed DAC converts the data into analog signals by JESD204B protocol, and the data rate can be up to more than 2 Gs/s.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (8)
1. A method for realizing random interpolation and high sampling processing of parallel architecture based on optimized frequency response is characterized by comprising the following steps:
(1) In a transmitting system, after receiving N pairs of IQ data to be converted, an upper computer performs fast Fourier transform to generate N pairs of frequency domain complex data F iq0 [N]；
(2) Sampling rate f of system original data sa1 And the sampling rate f actually required by the system sa0 Performing relative operation to the actually required sampling rate f of the system sa0 Acquiring the sampling rate f of the original data closest to the system in a manner of dividing 2 sa1 Is the sampling rate f of (2) sa2 ；
(3) Obtaining the length Ls of interpolation or extraction required by the current system, and carrying out corresponding processing;
(4) Inputting data, judging whether the interpolation number is greater than 2 times of interpolation, if so, entering the step (5), otherwise, entering the step (6);
(5) Entering a first Fifo first-in first-out queue for interpolation processing;
(6) Entering a second Fifo first-in first-out queue for interpolation processing;
(7) And sending the processed data to a DAC chip according to JESD204B protocol, and outputting a corresponding analog baseband signal by the DAC chip.
2. The method for implementing parallel architecture arbitrary interpolation and high sampling processing based on optimized frequency response according to claim 1, wherein in the step (1), the fast fourier transform is performed according to the following formula:
3. the method for implementing parallel architecture arbitrary interpolation and high sampling processing based on optimized frequency response according to claim 1, wherein the step (3) calculates the length Ls of the required interpolation or extraction according to the following formula:
when Ls is>At 0, for F iq0 [N]Intermediate position of array
Performing interpolation on complex numbers of Ls to 0; when Ls is<At 0, for F iq0 [N]Intermediate position +.>
And extracting Ls pair complex data.
4. The method for implementing parallel architecture arbitrary interpolation and high sampling processing based on optimized frequency response according to claim 3, wherein the step (5) specifically comprises the following steps:
(5.1) judging whether the interpolation multiple required by the current data is greater than 4 times of interpolation, if not, entering a step (5.2); if yes, single-channel half-band interpolation processing is carried out, whether the interpolation multiple required by the current data is greater than 8 times interpolation, 16 times interpolation, 32 times interpolation, 64 times interpolation, 128 times interpolation or more than 256 times interpolation and less than 2048 times interpolation is respectively judged, if not, a step (5.2) is carried out, and if yes, corresponding single-channel half-band interpolation processing is carried out;
(5.2) selecting a 1 st single-channel filter module to process a data output channel when the interpolation is less than or equal to 4 times of interpolation; when the interpolation is 8, selecting a 2 nd single-channel filter module to process a data output channel; interpolation is 16, and a 3 rd single-channel filter module is selected to process a data output channel; interpolation is 32, and a 4 th single-channel filter module is selected to process a data output channel; interpolation is 64, and a 5 th single-channel filter module is selected to process a data output channel; interpolation is 128, and a 6 th single-channel filter module is selected to process a data output channel; interpolation is 256, and a 7 th single-channel filter module is selected to process a data output channel; interpolation is 512, and the 8 th single-channel filter module is selected to process a data output channel; a 7 th single-channel filter module is selected by default to process a data output channel;
and (5.3) after the selection of the step (5.2) is completed, adopting a 1-channel to 2-channel parallel output half-band filter for processing, and entering the step (6).
5. The method for implementing parallel architecture arbitrary interpolation and high sampling processing based on optimized frequency response according to claim 4, wherein said step (6) specifically comprises the steps of:
(6.1) selecting the data after the processing;
(6.2) converting the one-channel parallel architecture into a two-channel parallel architecture to output a half-band filter;
(6.3) performing arbitrary interpolation processing using a CIC interpolation filter.
6. An apparatus for implementing arbitrary interpolation and high sampling processing of parallel architecture based on optimized frequency response, characterized in that the apparatus comprises:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions which, when executed by the processor, perform the steps of the method of implementing any of the interpolation and high sampling processes of the parallel architecture based on optimized frequency response of any of claims 1 to 5.
7. A processor for implementing parallel architecture arbitrary interpolation and high sampling based on optimized frequency response, characterized in that the processor is configured to execute computer executable instructions, which when executed by the processor, implement the steps of the method for implementing parallel architecture arbitrary interpolation and high sampling based on optimized frequency response as claimed in any one of claims 1 to 5.
8. A computer readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method of any of claims 1 to 5 for implementing parallel architecture arbitrary interpolation and high sampling processing based on optimized frequency response.
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