CN116015511A - Door operation control method, device, equipment and storage medium - Google Patents
Door operation control method, device, equipment and storage medium Download PDFInfo
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Abstract
The present disclosure provides a method, apparatus, device and storage medium for controlling door operation, including: obtaining the maximum estimated frequency offset ratio of a time source; calculating estimated duration based on time synchronization errors allowed by a time sensitive network, an absolute value of a maximum steady state synchronization error of the time source and the maximum estimated frequency offset ratio; a control signal for controlling the gate operation is generated based on the estimated duration. Compared with the existing control method of the door operation, the scheme provided by the embodiment of the disclosure can rapidly realize the starting of the door operation. In the case that the time source of the network node fails and the time synchronization with the main time source cannot be realized, the door operation can still be controlled to be in a usable state within a period of time by adopting the scheme.
Description
Technical Field
The disclosure relates to the technical field of time-sensitive networks, and in particular relates to a method, a device, equipment and a storage medium for controlling door operation.
Background
To ensure that the total delay and jitter of time sensitive traffic in the time sensitive network (Time Sensitive Network) in the network is highly predictable, in the related art, a network node creates a protection window for data frames of the time sensitive traffic such that the data frames of the time sensitive traffic are transmitted within the protection window. Specifically, the network node adopts a door operation method, and the creation and the ending of the protection window are realized by precisely controlling the door states corresponding to the service types of the output port.
The premise of the door operation start-stop control is the judgment of the availability of time sources in the network node. In the related art, a network node adopts a system management function to identify the availability of a time source. Specifically, the network node determines whether the time source is available by using a timing comparison mechanism through a system management function.
However, the method in the related art judges that there is a defect in availability of a time source, and particularly shows that: the operation of starting the door can be realized only after the time source completes synchronization for a long time, so that the starting speed is too slow; upon detection of a time source failure, the gate operation is immediately closed, resulting in wasted time synchronization performance of the time source.
Disclosure of Invention
To solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a method, an apparatus, a time-sensitive network device, and a storage medium for controlling a door operation.
In one aspect, an embodiment of the present disclosure provides a method for controlling a door operation, including:
obtaining the maximum estimated frequency offset ratio of a time source;
calculating the estimated duration of the time source based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady state synchronization error of the time source and the maximum estimated frequency offset ratio;
a control signal for controlling the gate operation is generated based on the estimated duration.
Optionally, obtaining the maximum estimated frequency offset ratio of the time source includes:
acquiring the frequency deviation uncertainty ratio, the frequency deviation proportion value and the crystal oscillator frequency deviation ratio of the crystal oscillator in the time source;
calculating the sum of the frequency offset uncertainty ratio and the frequency offset proportion value;
responding to the sum value being larger than the crystal oscillator frequency offset ratio, and taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio; or,
and responding to the sum value being smaller than or equal to the crystal oscillator frequency offset ratio, and taking the sum value as the maximum estimated frequency offset ratio.
Optionally, the acquiring the frequency offset uncertainty ratio of the time source includes:
acquiring a clock period of a physical interface of the time source and a statistical duration for frequency offset estimation;
and calculating the ratio of the clock period to the statistical duration as the frequency offset uncertainty ratio.
Optionally, the step of obtaining the maximum estimated frequency offset ratio of the time source is performed in response to receiving a valid synchronization signal, the valid synchronization signal being used to indicate that the time source is valid for time synchronization.
Optionally, the calculating the estimated duration based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady state synchronization error of the time source and the maximum estimated frequency offset ratio includes:
calculating the difference between the absolute value of the time synchronization error and the maximum steady-state synchronization error;
and calculating the ratio of the difference value to the maximum estimated frequency offset ratio as the estimated duration.
Optionally, generating a control signal for controlling the gate operation based on the estimated duration comprises:
determining an instant remaining duration based on the estimated duration;
judging whether the ratio of the remaining duration to the gate queue period is greater than a preset threshold, and generating a control signal for starting the gate operation of the next gate queue period in response to the ratio being greater than the preset threshold; or,
and generating a control signal for closing the next gate queue cycle gate operation in response to the ratio being less than the preset threshold.
Optionally, the preset threshold is greater than or equal to 2.
Optionally, the determining the availability of the time source based on the estimated duration includes:
judging whether the residual duration is longer than an alarm threshold duration or not;
and generating an alarm prompt signal in response to the residual duration being less than the alarm threshold duration, wherein the alarm prompt signal is used for prompting the abnormal running state of the time source.
In another aspect, an embodiment of the present disclosure provides a control apparatus for door operation, including:
the maximum estimated frequency offset ratio acquisition unit is used for acquiring the maximum estimated frequency offset ratio of the time source;
the estimated duration calculation unit is used for calculating the estimated duration based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady-state synchronization error of the time source and the maximum estimated frequency offset ratio;
and a control signal generation unit for generating a control signal for controlling the gate operation based on the estimated duration.
Optionally, the maximum estimated frequency offset ratio obtaining unit includes:
the first acquisition subunit is used for acquiring the frequency deviation uncertainty ratio, the frequency deviation proportion value and the crystal oscillator frequency deviation ratio of the crystal oscillator in the time source;
a sum value calculating subunit, configured to calculate a sum value of the frequency offset uncertainty ratio and the frequency offset proportion value;
the maximum estimated frequency offset ratio selecting subunit is used for taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio under the condition that the sum value is larger than the crystal oscillator frequency offset ratio; and taking the sum value as the maximum estimated frequency offset ratio under the condition that the sum value is smaller than or equal to the crystal oscillator frequency offset ratio.
Optionally, the control signal generating unit includes:
a remaining duration calculation subunit, configured to determine an immediate remaining duration based on the estimated duration;
the judging subunit is used for judging whether the ratio of the residual duration to the gate queue period is greater than a preset threshold value, and the preset threshold value is greater than or equal to 2;
the synchronous signal generation subunit is used for generating a control signal for starting the next gate queue cycle gate operation under the condition that the ratio is larger than the preset threshold value; and generating a control signal for closing the next gate queue cycle gate operation if the ratio is less than the preset threshold.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
according to the availability judgment scheme of the time source, the estimated duration is calculated according to the maximum estimated frequency offset ratio of the time source, the time synchronization error allowed by the time sensitive network and the absolute value of the maximum steady-state synchronization error of the time source, and a control signal for controlling the door operation is generated. Compared with the existing control method of the door operation, the scheme provided by the embodiment of the disclosure can rapidly realize the starting of the door operation. In the case that the time source of the network node fails and time synchronization cannot be achieved, the door operation can still be controlled to be in a usable state within a period of time by adopting the scheme.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the prior art, the drawings that are used in the description of the embodiments or the prior art will be briefly described below. It will be obvious to those skilled in the art that other figures can be obtained from these figures without inventive effort, in which:
FIG. 1 is a flow chart of a method of controlling door operation provided by an embodiment of the present disclosure;
fig. 2 is a flow chart of a method of obtaining a maximum estimated frequency offset ratio provided by some embodiments of the present disclosure;
FIG. 3 is a flow chart of a method of determining availability of a time source provided by some embodiments of the present disclosure;
FIG. 4 is a schematic structural view of a door operation control apparatus provided by some embodiments of the present disclosure;
fig. 5 is a schematic structural diagram of a time-sensitive network device according to an embodiment of the present application.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
The embodiment of the disclosure provides a control method for gate operation, which is used for a network node (namely time sensitive network equipment) of a time sensitive network, so that the network node can judge whether gate operation is started or not.
Fig. 1 is a flowchart of a control method of a door operation provided in an embodiment of the present disclosure. As shown in fig. 1, the method for controlling the gate operation provided in the embodiment of the present disclosure includes steps S101 to S103.
Step S101: the maximum estimated frequency offset ratio of the time source is obtained.
The maximum estimated frequency offset ratio is the ratio of the maximum frequency offset of the estimated time source relative to the nominal frequency. In some embodiments of the present disclosure, the aforementioned nominal frequency may be a nominal frequency of the primary time source, and the maximum frequency offset is a maximum frequency offset determined based on the nominal frequency of the primary time source. In other embodiments of the present disclosure, the aforementioned nominal frequency may be a nominal frequency of the crystal oscillator in the local time source, and the maximum frequency offset is a maximum frequency offset determined based on the local time source crystal oscillator frequency.
The maximum estimated frequency offset ratio may be obtained when the time source performs data update using a maximum frequency offset estimation mechanism. Fig. 2 is a flow chart of a method for obtaining a maximum estimated frequency offset ratio provided by some embodiments of the present disclosure. As shown in fig. 2, in one application of the embodiment of the present application, the method for obtaining the maximum estimated frequency offset ratio of the time source may include steps S1011-S1015.
S1011: and acquiring the frequency deviation uncertainty ratio, the frequency deviation proportion value and the crystal oscillator frequency deviation ratio of the crystal oscillator in the time source.
The frequency offset uncertainty ratio of the time source is a ratio that characterizes the uncertainty of the time source self-derived frequency offset calculation.
In some embodiments of the present disclosure, the frequency offset uncertainty ratio may be calculated based on the clock period of the time source physical interface and the statistical duration used for frequency offset estimation. Specifically, the frequency offset uncertainty ratio can be obtained by calculating f_uncertainty=t_res/t_counter, wherein f_uncertainty is the frequency offset uncertainty ratio, t_res is the clock period of the time source physical interface, and Tcounter is the statistical duration of frequency offset estimation.
The frequency offset ratio value is a frequency offset ratio calculated based on the self frequency offset of the time source. The frequency offset ratio value can be calculated by a time source according to the acquired internal parameters. In the embodiment of the disclosure, the frequency offset ratio value is represented by freq_offset.
The crystal oscillator frequency offset ratio of the crystal oscillator in the time source is the ratio of the frequency error of the characterization crystal oscillator to the nominal frequency. In the embodiment of the disclosure, the crystal oscillator frequency offset ratio can be determined by querying predefined crystal deviation information. In the embodiment of the disclosure, the crystal oscillator frequency offset ratio is expressed by trim_osc_ofs.
S1012: and calculating the sum of the frequency offset uncertainty ratio and the frequency offset proportion value.
S1013: judging whether the sum is larger than the frequency offset ratio of the crystal oscillator; if yes, go to step S1014; if not, execution proceeds to S1015.
S1014: and taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio.
S1015: the sum is taken as the maximum estimated frequency offset ratio.
In the embodiment of the disclosure, if the sum of the frequency deviation uncertainty ratio and the frequency deviation proportion value is larger than the crystal oscillator frequency deviation ratio, taking the crystal oscillator frequency deviation ratio as the maximum estimated frequency deviation ratio of a time source; and if the sum is smaller than the crystal oscillator frequency offset ratio, taking the sum as the maximum estimated frequency offset ratio.
In the embodiment of the disclosure, the sum of the frequency deviation uncertainty ratio and the frequency deviation proportion value is compared with the crystal oscillator frequency deviation ratio to determine the maximum estimated frequency deviation ratio. In other embodiments of the present disclosure, the frequency offset ratio value may also be compared with the crystal oscillator frequency offset ratio to determine whether to use the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio or the frequency offset ratio value as the maximum estimated frequency offset ratio. Specifically, if the frequency offset ratio value is larger than the crystal oscillator frequency offset ratio, taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio; and if the crystal oscillator frequency offset ratio is larger than the frequency offset ratio value, taking the frequency offset ratio value as the maximum estimated frequency offset ratio.
It should be noted that in some embodiments of the present disclosure, the network node performs the step of obtaining the maximum estimated frequency offset ratio of the time source in response to receiving a valid synchronization signal, where the valid synchronization signal is used to indicate that the synchronization source is performing valid time synchronization. After determining the maximum estimated frequency offset ratio for the time source, step S102 may then be performed.
Step S102: and calculating the estimated duration based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady state synchronization error of the time source and the maximum estimated frequency offset ratio.
The time synchronization error allowed by the time sensitive network is the maximum time synchronization error allowed by the data frame of the time sensitive service when the data frame is transmitted in the time sensitive network, and the time synchronization error allowed by the time sensitive network is expressed by spec_et. In the embodiment of the disclosure, the time synchronization error can be obtained by reading the configuration file.
The absolute value of the maximum steady-state synchronization error of the time source is the absolute value of the maximum synchronization error of the time source in a steady-state when the time source performs time synchronization, and the absolute value of the maximum steady-state synchronization error is expressed by as_et. In the embodiment of the disclosure, the absolute value of the maximum steady-state synchronization error of the time source can be obtained by reading the configuration file. In other embodiments of the present disclosure, the maximum steady state synchronization error of the time source may be obtained by counting error information delivered by an instance of the generalized precision clock protocol (GeneralizedPrecision Time Protocol, gPTP) over a period of time.
In some embodiments of the present disclosure, steps S1021-S1022 may be employed to calculate an estimated duration.
S1021: and calculating the difference between the absolute value of the time synchronization error and the maximum steady-state synchronization error.
S1022: and calculating the ratio of the difference value to the maximum estimated frequency offset ratio to be used as the estimated duration.
The estimated duration is a duration that the time synchronization source in the network node can still keep the difference between the output synchronization time and the time of the main time source smaller than the synchronization precision index after the synchronization between the time synchronization source and the main time source is lost.
In the disclosed embodiment, the estimated duration may be calculated using ttl_est_val= (spec_et-as_et)/max_f_offset_ratio.
S103: a control signal for controlling the operation of the gate is generated based on the estimated duration.
In some embodiments of the present disclosure, the estimated stored time period may be compared to a pre-set time period threshold to determine the type of control signal that generated the control gate operation. For example, if the estimated duration is greater than a preset duration threshold, a signal is generated that controls the initiation of the gate operation. And if the estimated duration is less than or equal to a preset duration threshold, determining to generate a signal controlling the gate operation to close.
Fig. 3 is a flow chart of generating a control signal for controlling gate operation based on an estimated duration provided by some embodiments of the present disclosure. As shown in fig. 3, in some embodiments of the present disclosure, a time-to-live countdown method may be employed to generate a control signal for controlling the gate operation, and may specifically include steps S1031-S1034. It should be noted that steps S1031-S1034 are performed periodically after the estimated duration is obtained until the remaining duration is decremented to 0.
S1031: based on the estimated duration, an instant remaining duration is determined.
In the embodiment of the disclosure, after acquiring the new estimated duration, the network node may initialize the down counter according to the estimated duration, and cause the down counter to perform the down operation according to the time frequency provided by the time source, where the current time is the value of the down counter, that is, the remaining duration of the current time.
S1032: judging whether the ratio of the remaining duration to the gate queue period is greater than a preset threshold; if yes, go to step S1033; if not, step S1034 is performed.
S1033: a control signal is generated that initiates the next gate queue cycle gate operation.
S1034: a control signal is generated to close the next gate queue cycle gate operation.
The gate queue period is the duration of time required for the sequence of actions to be fully executed for all gates to form. The preset threshold is a threshold determined based on the gate queue period and the time offset error allowed by the time source. In some embodiments of the present disclosure, the preset threshold may be set to 2; in other embodiments of the present disclosure, the preset threshold may also be set to an integer greater than 2.
In the embodiment of the disclosure, if the ratio of the remaining duration to the gate period is greater than the preset threshold, it is determined that the time offset error of the time source is still smaller than the allowable time offset error when the gate operation is performed in the next gate period, so that a control signal for starting the next gate queue operation is generated, and the gate operation can be performed in the next gate queue period.
If the ratio of the remaining duration to the gate period is smaller than or equal to the preset threshold, it is determined that the time offset error is greater than or equal to the allowable time offset error when the gate operation is performed in the next gate period, and a control signal for closing the gate operation in the next gate queue period is generated, and at this time, the gate operation is not performed in the next gate queue period.
According to the method for controlling the door operation, the estimated duration is calculated according to the maximum estimated frequency offset ratio of the time source, the time synchronization error allowed by the time sensitive network and the absolute value of the maximum steady-state synchronization error of the time source, and a control signal for controlling the door operation is generated based on the estimated duration.
By adopting the method provided by the embodiment of the disclosure, the control signal can be determined directly based on the estimated duration, and the next gate queue period is controlled to execute the gate operation based on the control signal. Compared with the existing door operation control method, the door operation control method provided by the embodiment of the disclosure can quickly realize the start of the door operation.
In addition, by adopting the control method for the gate operation provided by the embodiment of the disclosure, the ratio of the estimated duration to the gate queue period calculated based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady state synchronization error of the time source and the maximum estimated frequency offset ratio is much larger than the preset threshold. Under the condition that the time source of the network node fails and time synchronization cannot be achieved, the method provided by the embodiment of the disclosure can still determine that the gate operation is in the continuous state within a period of time, and then the time-sensitive network can be ensured to maintain the continuous state for a period of time. The method for controlling the door operation has the capability of resisting the synchronization loss in a short time, and can enhance the stability and the safety of the time-sensitive network.
For example, assuming a maximum allowable time synchronization error of 500ns for a time source and a frequency offset ratio of 5ppb (parts per billion) for the time source, a frequency offset ratio of 5ppb would not have a time offset of 500ns until the time source was operated for 100 s. That is, the synchronization time of the time synchronization source output is still available within 100s, where the 100s time sensitive network may be in a persistent state.
In addition, in some embodiments of the present disclosure, when an intermittent synchronization failure occurs in the time synchronization source, the method provided by the embodiments of the present disclosure may determine that the time source still has availability, so as to avoid the problem that the intermittent synchronization failure causes the door operation to be intermittently unavailable.
In some embodiments of the present disclosure, step S103 of determining availability of a time source based on the estimated duration may include steps S1035-S1037 after performing step S1031, in addition to the aforementioned steps S1031-S1034.
S1035: judging whether the residual duration is longer than the alarm threshold duration; if yes, executing S1036; if not, S1037 is executed.
In the embodiment of the disclosure, the alarm threshold time is set according to the length of the gate queue period, so as to ensure that an alarm prompt signal is generated before the gate operation is stopped.
S1036: and generating a normal state signal in response to the remaining duration being longer than the alarm threshold duration, wherein the normal state signal is used for prompting that the time source is in a normal running state.
S1037: and generating an alarm prompt signal in response to the residual duration being less than or equal to the alarm threshold duration, wherein the alarm prompt signal is used for prompting abnormal running state of the time source.
After acquiring the alarm prompt signal, the network node determines that the running state of the time source is abnormal, and can perform the operations of detecting the system fault, switching to the hot standby time source and the like during the duration of the time-sensitive network, so as to quickly repair the time source fault and avoid the problem of overlarge delay or loss of the key data frame data caused by the breakdown of the time-sensitive network.
Fig. 4 is a schematic structural view of a control device for door operation provided in some embodiments of the present disclosure. The control means of the door operation may be understood as part of the functional modules of the network node described above.
As shown in fig. 4, the control apparatus 400 for a gate operation provided by the present disclosure includes a maximum estimated frequency offset ratio acquisition unit 401, an estimated duration calculation unit 402, and a control signal generation unit 403.
The maximum estimated frequency offset ratio obtaining unit 401 is configured to obtain a maximum estimated frequency offset ratio of the time source.
The estimated duration calculation unit 402 is configured to calculate an estimated duration based on a time synchronization error allowed by the time sensitive network, an absolute value of a maximum steady state synchronization error of the time source, and a maximum estimated frequency offset ratio.
The control signal generation unit 403 generates a control signal for controlling the gate operation based on the estimated duration.
In some embodiments of the present disclosure, the maximum estimated frequency offset ratio acquisition unit 401 includes a first acquisition subunit, a sum value calculation subunit, and a maximum estimated frequency offset ratio selection subunit.
The first acquisition subunit is used for acquiring the frequency deviation uncertainty ratio, the frequency deviation proportion value and the crystal oscillator frequency deviation ratio of the crystal oscillator in the time source. The sum value calculating subunit is used for calculating the sum value of the frequency deviation uncertainty ratio and the frequency deviation proportion value. The maximum estimated frequency offset ratio selecting subunit is used for taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio under the condition that the sum value is larger than the crystal oscillator frequency offset ratio; and taking the sum value as the maximum estimated frequency offset ratio under the condition that the sum value is smaller than or equal to the crystal oscillator frequency offset ratio.
In some embodiments of the present disclosure, the first obtaining subunit obtains a frequency offset uncertainty ratio of the time source, including: acquiring a clock period of a physical interface of a time source and a statistical duration for frequency offset estimation; and calculating the ratio of the clock period and the statistical duration as the frequency offset uncertainty ratio.
In some embodiments of the present disclosure, the maximum estimated frequency offset ratio acquisition unit 401 performs the step of acquiring the maximum estimated frequency offset ratio of the time source in response to receiving an effective synchronization signal indicating that the time source is effectively time synchronized.
In some embodiments of the present disclosure, the estimated duration calculation unit 402 calculates an estimated duration, including: calculating the difference between the absolute value of the time synchronization error and the maximum steady-state synchronization error; and calculating the ratio of the difference value to the maximum estimated frequency offset ratio to be used as the estimated duration.
In some embodiments of the present disclosure, the control signal generation unit 403 includes a remaining duration calculation subunit, a judgment subunit, and a synchronization signal generation subunit.
The remaining duration calculation subunit is used for determining the instant remaining duration based on the estimated duration.
The judging subunit is used for judging whether the ratio of the remaining duration to the gate queue period is greater than a preset threshold value, and the preset threshold value is greater than or equal to 2.
The synchronous signal generation subunit is used for generating a control signal for starting the cycle gate operation of the next gate queue under the condition that the ratio is larger than a preset threshold value; and generating a control signal for closing the next gate queue cycle gate operation if the ratio is less than a preset threshold.
In some embodiments of the present disclosure, the control signal generating unit 403 is further configured to determine whether the remaining duration is greater than an alarm threshold duration; and generating an alarm prompt signal in response to the remaining duration being less than the alarm threshold duration, the alarm prompt signal being used to prompt that the time source operating state is abnormal.
Fig. 5 is a schematic structural diagram of a time-sensitive network device according to an embodiment of the present application. The time sensitive network device 500 may perform the control method of the gate operation in the previous embodiment, determining the availability of the time source.
As shown in fig. 5, the time-sensitive network device 500 comprises at least one processor 501, at least one memory 502, at least one communication interface 503, a bus system 504 and at least one time source 505, the processor 501, the memory 503 and the time source 505 being coupled together by the bus system 504, the communication interface 503 being adapted to enable the transfer of information between the various components within the time-sensitive network device and external devices.
The bus system 504 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 504 in fig. 5.
The memory 502 in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. In some implementations, the memory 502 stores the following elements, executable units or data structures, or a subset thereof, or an extended set thereof: an operating system and application programs.
The operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic tasks and processing hardware-based tasks. Applications, including various applications such as media players (mediaplayers), browsers (browses), etc., are used to implement various application tasks. The program for implementing the method for controlling the door operation provided in the embodiment of the present application may be included in the application program.
In the embodiment of the present application, the processor 501 is configured to execute the steps of each embodiment of the control method for the gate operation provided in the embodiment of the present application by calling a program or an instruction stored in the memory 502, specifically, a program or an instruction stored in an application program.
The method for controlling gate operation provided in the embodiments of the present application may be applied to the processor 501 or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry in hardware or instructions in software in the processor 501. The processor 501 may be a general purpose processor, a digital signal processor (DigitalSignalProcessor, DSP), an application specific integrated circuit (application specific IntegratedCircuit, ASIC), an off-the-shelf programmable gate array (FieldProgrammableGateArray, FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of the method for controlling gate operation provided in the embodiments of the present application may be directly embodied and executed by a hardware decoding processor, or may be executed by a combination of hardware and software units in the decoding processor. The software elements may be located in a random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory 502 and the processor 501 reads information in the memory 502 and, in combination with its hardware, performs the steps of the method.
The present application also proposes a computer-readable storage medium storing computer instructions for causing a computer to perform the steps of the embodiments of the control method, such as the gate operation.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely a specific embodiment of the application to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. A method of controlling door operation, comprising:
obtaining the maximum estimated frequency offset ratio of a time source;
calculating the estimated duration of the time source based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady state synchronization error of the time source and the maximum estimated frequency offset ratio;
a control signal for controlling the gate operation is generated based on the estimated duration.
2. The method of claim 1, wherein obtaining a maximum estimated frequency offset ratio for the time source comprises:
acquiring the frequency deviation uncertainty ratio, the frequency deviation proportion value and the crystal oscillator frequency deviation ratio of the crystal oscillator in the time source;
calculating the sum of the frequency offset uncertainty ratio and the frequency offset proportion value;
responding to the sum value being larger than the crystal oscillator frequency offset ratio, and taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio; or,
and responding to the sum value being smaller than or equal to the crystal oscillator frequency offset ratio, and taking the sum value as the maximum estimated frequency offset ratio.
3. The method of claim 2, wherein the obtaining the frequency offset uncertainty ratio of the time source comprises:
acquiring a clock period of a physical interface of the time source and a statistical duration for frequency offset estimation;
and calculating the ratio of the clock period to the statistical duration as the frequency offset uncertainty ratio.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
and in response to receiving a valid synchronization signal, performing the step of obtaining the maximum estimated frequency offset ratio of the time source, wherein the valid synchronization signal is used for indicating that the time source performs valid time synchronization.
5. The method of claim 1, wherein the calculating an estimated duration based on the time synchronization error tolerated by the time sensitive network, the absolute value of the maximum steady state synchronization error of the time source, and the maximum estimated frequency offset ratio comprises:
calculating the difference between the absolute value of the time synchronization error and the maximum steady-state synchronization error;
and calculating the ratio of the difference value to the maximum estimated frequency offset ratio as the estimated duration.
6. The method of any of claims 1-5, wherein generating a control signal for controlling door operation based on the estimated duration comprises:
determining an instant remaining duration based on the estimated duration;
judging whether the ratio of the remaining duration to the gate queue period is greater than a preset threshold, and generating a control signal for starting the gate operation of the next gate queue period in response to the ratio being greater than the preset threshold; or,
and generating a control signal for closing the next gate queue cycle gate operation in response to the ratio being less than the preset threshold.
7. The method of claim 6, wherein the step of providing the first layer comprises,
the preset threshold is greater than or equal to 2.
8. The method of claim 6, wherein the determining the availability of the time source based on the estimated duration comprises:
judging whether the residual duration is longer than an alarm threshold duration or not;
and generating an alarm prompt signal in response to the residual duration being less than the alarm threshold duration, wherein the alarm prompt signal is used for prompting the abnormal running state of the time source.
9. A control device for door operation, comprising:
the maximum estimated frequency offset ratio acquisition unit is used for acquiring the maximum estimated frequency offset ratio of the time source;
the estimated duration calculation unit is used for calculating the estimated duration based on the time synchronization error allowed by the time sensitive network, the absolute value of the maximum steady-state synchronization error of the time source and the maximum estimated frequency offset ratio;
and a control signal generation unit for generating a control signal for controlling the gate operation based on the estimated duration.
10. The apparatus of claim 9, wherein the maximum estimated frequency offset ratio acquisition unit comprises:
the first acquisition subunit is used for acquiring the frequency deviation uncertainty ratio, the frequency deviation proportion value and the crystal oscillator frequency deviation ratio of the crystal oscillator in the time source;
a sum value calculating subunit, configured to calculate a sum value of the frequency offset uncertainty ratio and the frequency offset proportion value;
the maximum estimated frequency offset ratio selecting subunit is used for taking the crystal oscillator frequency offset ratio as the maximum estimated frequency offset ratio under the condition that the sum value is larger than the crystal oscillator frequency offset ratio; and taking the sum value as the maximum estimated frequency offset ratio under the condition that the sum value is smaller than or equal to the crystal oscillator frequency offset ratio.
11. The apparatus according to claim 9, wherein the control signal generating unit includes:
a remaining duration calculation subunit, configured to determine an immediate remaining duration based on the estimated duration;
the judging subunit is used for judging whether the ratio of the residual duration to the gate queue period is greater than a preset threshold value, and the preset threshold value is greater than or equal to 2;
the synchronous signal generation subunit is used for generating a control signal for starting the next gate queue cycle gate operation under the condition that the ratio is larger than the preset threshold value; and generating a control signal for closing the next gate queue cycle gate operation if the ratio is less than the preset threshold.
12. A time sensitive network device, comprising:
a processor; and
a memory in which a program is stored,
wherein the program comprises instructions which, when executed by the processor, cause the processor to perform the method according to any of claims 1-7.
13. A computer readable storage medium, wherein the storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111233094.3A CN116015511A (en) | 2021-10-22 | 2021-10-22 | Door operation control method, device, equipment and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111233094.3A CN116015511A (en) | 2021-10-22 | 2021-10-22 | Door operation control method, device, equipment and storage medium |
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| CN116015511A true CN116015511A (en) | 2023-04-25 |
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| CN202111233094.3A Pending CN116015511A (en) | 2021-10-22 | 2021-10-22 | Door operation control method, device, equipment and storage medium |
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