CN116015293A - Calibration method and device for switch capacitor in pipelined ADC (analog-to-digital converter) - Google Patents
Calibration method and device for switch capacitor in pipelined ADC (analog-to-digital converter) Download PDFInfo
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- CN116015293A CN116015293A CN202310117197.6A CN202310117197A CN116015293A CN 116015293 A CN116015293 A CN 116015293A CN 202310117197 A CN202310117197 A CN 202310117197A CN 116015293 A CN116015293 A CN 116015293A
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Abstract
The application provides a calibration method and device of a switch capacitor in a pipelined ADC, wherein the method comprises the following steps: selecting a subconverter; connecting a reference voltage switch in an ith branch in a DAC module in the sub-converter with a positive reference voltage source, and sending a calibration analog signal to the sub-converter to obtain a first residual signal output by the sub-converter; connecting a reference voltage switch in the ith branch with a negative reference voltage source, and sending an analog signal to the sub-converter to obtain a second residual signal output by the sub-converter; calculating to obtain an actual capacitance value of the switch capacitor in the ith branch based on the first residual signal, the second residual signal, the voltage value of the positive reference voltage source and the capacitance value of the feedback capacitor in the subconverter; based on the actual capacitance value, the switched capacitance in the ith branch is calibrated. The method and the device can calibrate the switch capacitor in the pipeline ADC without introducing a special test circuit and a high-precision auxiliary ADC.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a method and a device for calibrating a switch capacitor in a pipelined ADC.
Background
Analog-to-digital converters (AnalogtoDigitalConverter, ADC) have found widespread use in modern communication systems, with pipelined ADCs being the most popular architecture.
For the pipelined ADC, the ratio of the switch capacitor to the feedback capacitor in the pipelined ADC is a key factor for determining the accuracy of the pipelined ADC, however, since the actual capacitance value of the switch capacitor deviates from the ideal design value, the deviation needs to be calibrated.
The existing calibration method comprises the step of regulating the voltage (i.e. trim) of the switched capacitor in the production process, or introducing an auxiliary ADC with slower speed but higher precision to calibrate conversion errors in real time. However, the former requires additional test circuitry and expensive test equipment, and the latter requires the expense of area and power consumption.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a method and apparatus for calibrating a switch capacitor in a pipelined ADC, which can calibrate the switch capacitor in the pipelined ADC without introducing special test circuits and high-precision auxiliary ADCs.
In a first aspect, an embodiment of the present application provides a method for calibrating a switch capacitor in a pipelined ADC, where the method includes:
S101, selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipelined ADC;
s102, configuring the latest target subconverter into a sampling mode so as to charge each switch capacitor in the latest target subconverter;
s103, after each switch capacitor in the latest target subconverter is charged, configuring the latest target subconverter into a conversion mode, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending a calibration analog signal to the latest target subconverter to obtain a first residual signal output by the latest target subconverter, wherein the initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target subconverter;
s104, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending the calibration analog signal to the latest target subconverter to obtain a second residual signal output by the latest target subconverter, wherein for each reference branch except the ith branch in the DAC module in the latest target subconverter, when the reference voltage switch in the ith branch in the DAC module in the latest target subconverter is respectively connected with a positive reference voltage source and a negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, the reference voltage switches in the reference branches are connected with a positive reference voltage source in the reference branch or are connected with a negative reference voltage source in the reference branch;
S105, calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, a voltage value of a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter and a capacitance value of a feedback capacitor in the latest target subconverter;
s106, calibrating the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter.
In one possible embodiment, the initial value of i is 1; after calibrating the switched capacitor in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switched capacitor in the ith branch in the DAC module in the latest target subconverter, the method further comprises:
judging whether the current i is smaller than n-1;
if the current i is smaller than n-1, i+1 is added, and the step S102 is returned;
if the current i is not less than n-1, judging whether the calibration of the switch capacitance in the DAC module in the latest target subconverter is carried out for n times or not;
If the calibration of the switch capacitance in the DAC module in the latest target subconverter is not performed for n times at present, the switch capacitance in the n-1 th branch in the DAC module in the latest target subconverter and the switch capacitance in the n-th branch in the DAC module in the latest target subconverter are replaced with each other in the circuit connection relationship in the latest target subconverter, and the step S102 is returned.
In one possible implementation, after determining whether calibration of the switched capacitance in the DAC module in the latest target subconverter has been performed n times currently if current i is not less than n-1, the method further comprises:
if the calibration of the switch capacitor in the DAC module in the latest target subconverter is carried out for n times at present, judging whether the latest target subconverter is a subconverter at the first stage in the pipelined ADC;
if the latest target subconverter is not the subconverter at the first stage in the pipeline ADC, taking the subconverter at the stage before the latest target subconverter in the pipeline ADC as the latest target subconverter, setting i as the initial value, and returning to the step S102;
If the latest target subconverter is the subconverter at the first stage in the pipeline ADC, ending the flow.
In one possible implementation manner, calculating the actual capacitance value of the switch capacitor in the ith branch in the DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and the capacitance value of the feedback capacitor in the latest target subconverter includes:
calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter through the following formula;
wherein C is i Actual electricity for the switched capacitor in the ith branch in the DAC module in the most recent target subconverterCapacitance value, V ref C is the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter F For the most recent capacitance value of the feedback capacitance in the target subconverter, V out (T i =1) is the latest first residual signal, V out (T i = -1) is the latest second residual signal.
In a second aspect, an embodiment of the present application provides a calibration apparatus for a switched capacitor in a pipelined ADC, the apparatus including:
A selecting module, configured to select a target sub-converter from a plurality of cascaded sub-converters included in the pipelined ADC;
the first processing module is used for configuring the latest target subconverter into a sampling mode so as to charge each switch capacitor in the latest target subconverter;
the second processing module is used for configuring the latest target subconverter into a conversion mode after each switch capacitor in the latest target subconverter is charged, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending a calibration analog signal to the latest target subconverter to obtain a first residual signal output by the latest target subconverter, wherein the initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target subconverter;
the third processing module is configured to connect the reference voltage switch in the ith branch in the DAC module in the latest target subconverter to the negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, and send the calibration analog signal to the latest target subconverter to obtain a second residual signal output by the latest target subconverter, where, for each reference branch in the DAC module in the latest target subconverter except for the ith branch, when the reference voltage switch in the ith branch in the DAC module in the latest target subconverter is connected to the positive reference voltage source and the negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, the reference voltage switches in the reference branches are connected to the positive reference voltage source in the reference branch, or are connected to the negative reference voltage source in the reference branch;
The calculating module is used for calculating the actual capacitance value of the switch capacitor in the ith branch in the DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter and the capacitance value of the feedback capacitor in the latest target subconverter;
and the calibration module is used for calibrating the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter.
In one possible embodiment, the initial value of i is 1; the apparatus further comprises:
the first judging module is used for judging whether the current i is smaller than n-1 after the calibration module calibrates the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter;
the fourth processing module is used for processing the i+1 if the current i is smaller than n-1 and re-delivering the i+1 to the first processing module;
The second judging module is used for judging whether the calibration of the switch capacitance in the DAC module in the latest target subconverter is carried out for n times or not currently if the current i is not smaller than n-1;
and the fifth processing module is used for replacing the switch capacitance in the n-1 branch in the DAC module in the latest target subconverter with the circuit connection relation of the switch capacitance in the n-th branch in the DAC module in the latest target subconverter and the circuit connection relation of the switch capacitance in the n-th branch in the DAC module in the latest target subconverter in each other and re-delivering the switch capacitance to the first processing module for processing if the calibration of the switch capacitance in the DAC module in the latest target subconverter is not performed for n times at present.
In one possible embodiment, the apparatus further comprises:
a third judging module, configured to judge whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC after the second judging module has currently performed calibration for the switched capacitor in the DAC module in the latest target sub-converter n times if the current i is not less than n-1;
A sixth processing module, configured to, if the latest target subconverter is not the subconverter at the first stage in the pipeline ADC, take the subconverter at the stage preceding the latest target subconverter in the pipeline ADC as the latest target subconverter, set i as the initial value, and re-send the initial value to the first processing module for processing;
and the seventh processing module is used for ending the flow if the latest target subconverter is a subconverter positioned at the first stage in the pipeline ADC.
In a possible implementation manner, the computing module is specifically configured to:
calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter through the following formula;
wherein C is i For the actual capacitance value of the switched capacitor in the ith branch of the DAC module in the latest target subconverter, V ref C is the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter F For the most recent capacitance value of the feedback capacitance in the target subconverter, V out (T i =1) is the latest first residual signal, V out (T i = -1) is the latest second residual signal.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor in communication with the storage medium via the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the steps of the method of calibrating switched capacitance in a pipelined ADC as recited in any one of the first aspects.
In a fourth aspect, embodiments of the present application also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method of calibrating switched capacitance in a pipelined ADC as claimed in any one of the first aspects.
The calibration method and the device for the switch capacitor in the pipeline ADC can calibrate the switch capacitor in the pipeline ADC under the condition that a special test circuit and a high-precision auxiliary ADC are not required to be introduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a flowchart of a method for calibrating a switch capacitor in a pipelined ADC according to an embodiment of the application;
fig. 2 shows a schematic structural diagram of a pipelined ADC according to an embodiment of the present application;
Fig. 3 shows a schematic structural diagram of a pipeline ADC sub-converter according to an embodiment of the present application;
FIG. 4 is a flow chart of another method for calibrating switched capacitors in pipelined ADCs provided in accordance with embodiments of the present application;
FIG. 5 shows a schematic diagram of another pipelined ADC sub-converter according to an embodiment of the present application;
FIG. 6 is a flow chart illustrating a method of calibrating a switched capacitor in another pipelined ADC provided by an embodiment of the present application;
fig. 7 is a schematic structural diagram of a calibrating device for a switch capacitor in a pipelined ADC according to an embodiment of the disclosure;
fig. 8 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.
In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features stated hereinafter, but not to exclude the addition of other features.
For the sake of understanding the present embodiment, a method and a system for calibrating a switch capacitor in a pipelined ADC provided in the present embodiment are described in detail.
Referring to fig. 1, a flowchart of a method for calibrating a switch capacitor in a pipelined ADC according to an embodiment of the application is shown, where the method includes:
illustratively, the pipeline ADC includes a plurality of cascaded sub-converters, for each of the sub-converters, the sub-converter is configured to convert an analog signal received by itself into a digital signal corresponding to a preset bit, for each non-last sub-converter, the non-last sub-converter is configured to obtain a residual signal based on the analog signal received by itself and the digital signal converted by itself, and output the residual signal to a sub-converter at a next stage of itself in the pipeline ADC, the non-last sub-converter includes sub-converters at first stage to last second stage in the pipeline ADC, and the residual signal is an analog signal;
If the preset bit corresponding to a certain sub-converter is m bits, then there are 2 in the DAC module in the sub-converter m The number of branches (i.e. 2 exists m Switched capacitors, 2 m -1 reference voltage switch, the last branch comprising 2 ground switches not comprising a reference voltage switch).
The above is an illustration of an existing pipelined ADC with no modifications.
S101, selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipelined ADC;
since the performance of a pipelined ADC often depends mainly on the capacitance values of the switched capacitors in the ADC modules in the sub-converters of the first few stages in the preceding pipeline, the intermediate sub-converter of a certain stage in the pipelined ADC (i.e. a certain stage between stage 1 and the last stage) can be determined as the target sub-converter.
Referring to fig. 2, a schematic structural diagram of a pipelined ADC provided in an embodiment of the present application is shown, where digital signal outputs output from each stage of sub-converter in fig. 2 are combined by a digital combining block to obtain a combined digital signal output.
S102, configuring the latest target subconverter into a sampling mode so as to charge each switch capacitor in the latest target subconverter.
Referring to fig. 3, a schematic structural diagram of a sub-converter in a pipelined ADC provided in an embodiment of the present application is shown, where Φ1 is a charging switch, Φ2 in a first branch to an n-1 branch is a reference voltage switch, Φ2 in the n-1 branch is a ground switch, +vref is a positive reference voltage source, vref is a negative reference voltage source, and Φ1 in fig. 3 is all closed and Φ2 is all open when in a sampling mode.
S103, after each switch capacitor in the latest target subconverter is charged, configuring the latest target subconverter into a conversion mode, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending a calibration analog signal to the latest target subconverter to obtain a first residual signal output by the latest target subconverter, wherein the initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target subconverter;
the DAC module, namely the digital-to-analog converter (DigitaltoAnalogConverter, DAC) module.
When the subconverter is in conversion mode, phi 2 in figure 3 are all closed and phi 1 is all open.
The calibration analog signal may be generated by a hardware state machine.
S104, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending the calibration analog signal to the latest target subconverter to obtain a second residual signal output by the latest target subconverter, wherein for each reference branch except the ith branch in the DAC module in the latest target subconverter, when the reference voltage switch in the ith branch in the DAC module in the latest target subconverter is respectively connected with a positive reference voltage source and a negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, the reference voltage switches in the reference branches are connected with a positive reference voltage source in the reference branch or are connected with a negative reference voltage source in the reference branch;
the latest target subconverter keeps the conversion mode unchanged in this step.
For example, assuming that there are 4 branches in the DAC module in the latest target subconverter (i.e., the preset bit corresponding to the latest target subconverter is 2), when i is 1, i.e., the reference voltage switch in the DAC module in the latest target subconverter is connected to the positive reference voltage source and the negative reference voltage source in the first branch (in the second stage), the reference voltage switches in the 2 nd to 4 th branches are kept stationary.
S105, calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, a voltage value of a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter and a capacitance value of a feedback capacitor in the latest target subconverter;
s106, calibrating the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter.
The result of the calibration may be stored (programmed) into a digital register.
Referring to fig. 4, a flowchart of a method for calibrating a switch capacitor in a pipeline ADC according to another embodiment of the application is shown, where in one possible implementation, the initial value of i is 1; after calibrating the switched capacitor in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switched capacitor in the ith branch in the DAC module in the latest target subconverter, the method further comprises:
s401, judging whether the current i is smaller than n-1;
If the current i is smaller than n-1, executing step S402;
s402, i+1 is carried out, and the step S102 is returned;
if the current i is not less than n-1, executing step S403;
s403, judging whether the calibration of the switch capacitance in the DAC module in the latest target subconverter is performed for n times at present;
if the calibration of the switched capacitor in the DAC module in the latest target subconverter is not currently performed n times, step S404 is executed;
s404, the switching capacitance in the n-1 branch in the DAC module in the latest target subconverter and the switching capacitance in the n branch in the DAC module in the latest target subconverter are mutually replaced according to the circuit connection relation in the latest target subconverter, and the step S102 is returned.
That is, the switch capacitors from the first branch to the n-1 th branch in the DAC module in the latest target subconverter are calibrated sequentially, and after the calibration of the switch capacitors in the previous n-1 th branch is completed, the reference voltage switch does not exist in the n-1 th branch, so that the switch capacitors in the n-1 th branch and the switch capacitors in the n-th branch need to be replaced with each other in a circuit connection relationship, and the step S102 is returned to complete the calibration of the switch capacitors in the original n-th branch in the DAC module in the latest target subconverter.
Referring to fig. 5, which is a schematic structural diagram of another pipeline ADC sub-converter provided in this embodiment of the present application, fig. 5 corresponds to fig. 3, and shows a situation after a circuit connection relationship between a switch capacitor in an n-1 th branch in a DAC module in the sub-converter and a switch capacitor in an n-th branch in the DAC module in the sub-converter is interchanged, where Φ1 is a charging switch, Φ2 in a first branch to the n-1 th branch is a reference voltage switch, Φ2 in the n-th branch is a ground switch, +vref is a positive reference voltage source, and-Vref is a negative reference voltage source.
Referring to fig. 6, a flowchart of another method for calibrating a switched capacitor in a pipelined ADC according to an embodiment of the present application is shown, in one possible implementation, after determining whether calibration of a switched capacitor in a DAC module in a most recent target sub-converter has been performed n times if current i is not less than n-1, the method further includes:
s601, if calibration of the switch capacitance in the DAC module in the latest target subconverter is carried out for n times at present, judging whether the latest target subconverter is a subconverter at the first stage in the pipelined ADC;
That is, if calibration for each switched capacitor in the DAC module in the most recent target subconverter has been completed, it is determined whether the most recent target subconverter is the subconverter at the first stage in the pipelined ADC.
If the latest target subconverter is not the subconverter at the first stage in the pipelined ADC, step S602 is executed;
s602, taking a sub-converter at the previous stage of the latest target sub-converter in the pipelined ADC as the latest target sub-converter, setting i as the initial value, and returning to the step S102;
if the most recent target subconverter is the subconverter at the first stage in the pipelined ADC, step S603 is performed.
S603, ending the flow.
That is, in the pipelined ADC, the calibration of the switched capacitances is performed sequentially for the initial target subconverter and each stage of subconverter preceding the initial target subconverter, starting from the initial target subconverter.
For example, the pipeline ADC includes 4 cascaded sub-converters, and the first target sub-converter is a sub-converter in the third stage of the pipeline ADC (8 switched capacitors are included in the DAC module in the sub-converter in the third stage, 16 switched capacitors are included in the DAC module in the sub-converter in the second stage, and 4 switched capacitors are included in the DAC module in the sub-converter in the first stage).
Then, after the calibration of all 8 switched capacitances included in the DAC module in the sub-converter at the third stage in the pipeline ADC is completed, the 16 switched capacitances included in the DAC module in the sub-converter at the second stage in the pipeline ADC are calibrated;
after the calibration of all 16 switched capacitors included in the DAC module in the sub-converter at the second stage in the pipeline ADC is completed, the 4 switched capacitors included in the DAC module in the sub-converter at the first stage in the pipeline ADC are calibrated;
after the calibration of all 4 switched capacitances included in the DAC module in the sub-converter at the first stage in the pipelined ADC is completed, the flow ends.
In one possible implementation manner, calculating the actual capacitance value of the switch capacitor in the ith branch in the DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and the capacitance value of the feedback capacitor in the latest target subconverter includes:
calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter through the following formula;
Wherein C is i For the actual capacitance value of the switched capacitor in the ith branch of the DAC module in the latest target subconverter, V ref C is the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter F For the most recent capacitance value of the feedback capacitance in the target subconverter, V out (T i =1) is the latest first residual signal, V out (T i = -1) is the latest second residual signal.
According to the calibration method for the switch capacitor in the pipeline ADC, the switch capacitor in the pipeline ADC can be calibrated under the condition that a special test circuit and a high-precision auxiliary ADC are not required to be introduced.
Based on the same inventive concept, the embodiment of the present application further provides a device for calibrating a switch capacitor in a pipeline ADC, which corresponds to the method for calibrating a switch capacitor in a pipeline ADC in the embodiment, and since the principle of solving the problem by the device in the embodiment of the present application is similar to that of the method for calibrating a switch capacitor in the pipeline ADC in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repetition is omitted.
Referring to fig. 7, a schematic structural diagram of a calibrating device for a switch capacitor in a pipelined ADC according to an embodiment of the present application is shown, where the device includes:
A selecting module 701, configured to select a target sub-converter from a plurality of cascaded sub-converters included in the pipelined ADC;
a first processing module 702, configured to configure the latest target subconverter into a sampling mode to charge each switch capacitor in the latest target subconverter;
a second processing module 703, configured to configure the latest target subconverter into a conversion mode after each switch capacitor in the latest target subconverter completes charging, connect the reference voltage switch in the ith branch in the DAC module in the latest target subconverter to the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and send a calibration analog signal to the latest target subconverter to obtain a first residual signal output by the latest target subconverter, where the initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target subconverter;
a third processing module 704, configured to connect the reference voltage switch in the ith branch in the DAC module in the latest target subconverter to the negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, and send the calibration analog signal to the latest target subconverter to obtain a second residual signal output by the latest target subconverter, where, for each reference branch except the ith branch in the DAC module in the latest target subconverter, when the reference voltage switch in the ith branch in the DAC module in the latest target subconverter is connected to the positive reference voltage source and the negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, the reference voltage switches in the reference branches are connected to the positive reference voltage source in the reference branch, or are connected to the negative reference voltage source in the reference branch;
The calculating module 705 is configured to calculate an actual capacitance value of the switch capacitor in the ith branch in the DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and the capacitance value of the feedback capacitor in the latest target subconverter;
a calibration module 706, configured to calibrate the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter.
In one possible embodiment, the initial value of i is 1; the apparatus further comprises:
the first judging module is used for judging whether the current i is smaller than n-1 after the calibration module calibrates the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter;
a fourth processing module, configured to, if the current i is smaller than n-1, re-send i+1 to the first processing module 702 for processing;
The second judging module is used for judging whether the calibration of the switch capacitance in the DAC module in the latest target subconverter is carried out for n times or not currently if the current i is not smaller than n-1;
and a fifth processing module, configured to replace, if the calibration for the switched capacitor in the DAC module in the latest target subconverter is not performed n times currently, the switched capacitor in the n-1 th branch in the DAC module in the latest target subconverter and the switched capacitor in the n-th branch in the DAC module in the latest target subconverter with each other in the circuit connection relationship in the latest target subconverter, and re-pass the first processing module 702 for processing.
In one possible embodiment, the apparatus further comprises:
a third judging module, configured to judge whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC after the second judging module has currently performed calibration for the switched capacitor in the DAC module in the latest target sub-converter n times if the current i is not less than n-1;
A sixth processing module, configured to take, if the latest target subconverter is not the subconverter at the first stage in the pipelined ADC, the subconverter at the stage preceding the latest target subconverter in the pipelined ADC as the latest target subconverter, set i as the initial value, and re-send the initial value to the first processing module 702 for processing;
and the seventh processing module is used for ending the flow if the latest target subconverter is a subconverter positioned at the first stage in the pipeline ADC.
In one possible implementation, the computing module 704 is specifically configured to:
calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter through the following formula;
wherein C is i For the actual capacitance value of the switched capacitor in the ith branch of the DAC module in the latest target subconverter, V ref C is the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter F For the most recent capacitance value of the feedback capacitance in the target subconverter, V out (T i =1) is the latest first residual signal, V out (T i = -1) is the latestIs a second residual signal of (c).
According to the calibrating device for the switch capacitor in the pipeline ADC, the switch capacitor in the pipeline ADC can be calibrated under the condition that a special test circuit and a high-precision auxiliary ADC are not required to be introduced.
Referring to fig. 8, an electronic device 800 provided in an embodiment of the present application includes: a processor 801, a memory 802 and a bus, the memory 802 storing machine readable instructions executable by the processor 801, the processor 801 and the memory 802 communicating over the bus when the electronic device is running, the processor 801 executing the machine readable instructions to perform the steps of the method of calibrating switched capacitance in a pipelined ADC as described above.
Specifically, the memory 802 and the processor 801 can be general-purpose memories and processors, and are not limited herein, and the method for calibrating the switch capacitance in the pipelined ADC can be performed when the processor 801 runs a computer program stored in the memory 802.
Corresponding to the method for calibrating the switch capacitance in the pipeline ADC, the embodiment of the application also provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to execute the steps of the method for calibrating the switch capacitance in the pipeline ADC.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the method embodiments, which are not described in detail in this application. In the several embodiments provided herein, it should be understood that the disclosed systems, and methods may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, and the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, and for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of calibrating a switched capacitor in a pipelined ADC, the method comprising:
s101, selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipelined ADC;
s102, configuring the latest target subconverter into a sampling mode so as to charge each switch capacitor in the latest target subconverter;
s103, after each switch capacitor in the latest target subconverter is charged, configuring the latest target subconverter into a conversion mode, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending a calibration analog signal to the latest target subconverter to obtain a first residual signal output by the latest target subconverter, wherein the initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target subconverter;
S104, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending the calibration analog signal to the latest target subconverter to obtain a second residual signal output by the latest target subconverter, wherein for each reference branch except the ith branch in the DAC module in the latest target subconverter, when the reference voltage switch in the ith branch in the DAC module in the latest target subconverter is respectively connected with a positive reference voltage source and a negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, the reference voltage switches in the reference branches are connected with a positive reference voltage source in the reference branch or are connected with a negative reference voltage source in the reference branch;
s105, calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, a voltage value of a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter and a capacitance value of a feedback capacitor in the latest target subconverter;
S106, calibrating the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter.
2. The method of calibrating a switched capacitor in a pipelined ADC of claim 1 wherein i has an initial value of 1; after calibrating the switched capacitor in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switched capacitor in the ith branch in the DAC module in the latest target subconverter, the method further comprises:
judging whether the current i is smaller than n-1;
if the current i is smaller than n-1, i+1 is added, and the step S102 is returned;
if the current i is not less than n-1, judging whether the calibration of the switch capacitance in the DAC module in the latest target subconverter is carried out for n times or not;
if the calibration of the switch capacitance in the DAC module in the latest target subconverter is not performed for n times at present, the switch capacitance in the n-1 th branch in the DAC module in the latest target subconverter and the switch capacitance in the n-th branch in the DAC module in the latest target subconverter are replaced with each other in the circuit connection relationship in the latest target subconverter, and the step S102 is returned.
3. The method of calibrating a switched capacitor in a pipelined ADC of claim 2, wherein after determining whether calibration of the switched capacitor in the DAC module in the most recent target subconverter has been performed n times currently if current i is not less than n "1, the method further comprises:
if the calibration of the switch capacitor in the DAC module in the latest target subconverter is carried out for n times at present, judging whether the latest target subconverter is a subconverter at the first stage in the pipelined ADC;
if the latest target subconverter is not the subconverter at the first stage in the pipeline ADC, taking the subconverter at the stage before the latest target subconverter in the pipeline ADC as the latest target subconverter, setting i as the initial value, and returning to the step S102;
if the latest target subconverter is the subconverter at the first stage in the pipeline ADC, ending the flow.
4. The method according to claim 1, wherein calculating the actual capacitance value of the switch capacitor in the ith branch in the DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and the capacitance value of the feedback capacitor in the latest target subconverter, comprises:
Calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter through the following formula;
wherein C is i For the actual capacitance value of the switched capacitor in the ith branch of the DAC module in the latest target subconverter, V ref C is the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter F For the most recent capacitance value of the feedback capacitance in the target subconverter, V out (T i =1) is the latest first residual signal, V out (T i = -1) is the latest second residual signal.
5. A device for calibrating a switched capacitor in a pipelined ADC, the device comprising:
a selecting module for selecting a target sub-converter from a plurality of cascaded sub-converters included in the pipelined ADC;
the first processing module is used for configuring the latest target subconverter into a sampling mode so as to charge each switch capacitor in the latest target subconverter;
the second processing module is used for configuring the latest target subconverter into a conversion mode after each switch capacitor in the latest target subconverter is charged, connecting a reference voltage switch in an ith branch in a DAC module in the latest target subconverter with a positive reference voltage source in the ith branch in the DAC module in the latest target subconverter, and sending a calibration analog signal to the latest target subconverter to obtain a first residual signal output by the latest target subconverter, wherein the initial value of i is any integer from 1 to n-1, and n is the number of branches in the DAC module in the latest target subconverter;
The third processing module is configured to connect the reference voltage switch in the ith branch in the DAC module in the latest target subconverter to the negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, and send the calibration analog signal to the latest target subconverter to obtain a second residual signal output by the latest target subconverter, where, for each reference branch in the DAC module in the latest target subconverter except for the ith branch, when the reference voltage switch in the ith branch in the DAC module in the latest target subconverter is connected to the positive reference voltage source and the negative reference voltage source in the ith branch in the DAC module in the latest target subconverter, the reference voltage switches in the reference branches are connected to the positive reference voltage source in the reference branch, or are connected to the negative reference voltage source in the reference branch;
the calculating module is used for calculating the actual capacitance value of the switch capacitor in the ith branch in the DAC module in the latest target subconverter based on the latest first residual signal, the latest second residual signal, the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter and the capacitance value of the feedback capacitor in the latest target subconverter;
And the calibration module is used for calibrating the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter.
6. The device for calibrating a switch capacitor in a pipelined ADC according to claim 5, wherein the initial value of i is 1; the apparatus further comprises:
the first judging module is used for judging whether the current i is smaller than n-1 after the calibration module calibrates the switch capacitance in the ith branch in the DAC module in the latest target subconverter based on the actual capacitance value of the switch capacitance in the ith branch in the DAC module in the latest target subconverter;
the fourth processing module is used for processing the i+1 if the current i is smaller than n-1 and re-delivering the i+1 to the first processing module;
the second judging module is used for judging whether the calibration of the switch capacitance in the DAC module in the latest target subconverter is carried out for n times or not currently if the current i is not smaller than n-1;
and the fifth processing module is used for replacing the switch capacitance in the n-1 branch in the DAC module in the latest target subconverter with the circuit connection relation of the switch capacitance in the n-th branch in the DAC module in the latest target subconverter and the circuit connection relation of the switch capacitance in the n-th branch in the DAC module in the latest target subconverter in each other and re-delivering the switch capacitance to the first processing module for processing if the calibration of the switch capacitance in the DAC module in the latest target subconverter is not performed for n times at present.
7. The apparatus for calibrating a switched capacitor in a pipelined ADC as recited in claim 6, further comprising:
a third judging module, configured to judge whether the latest target sub-converter is a sub-converter in the first stage of the pipeline ADC after the second judging module has currently performed calibration for the switched capacitor in the DAC module in the latest target sub-converter n times if the current i is not less than n-1;
a sixth processing module, configured to, if the latest target subconverter is not the subconverter at the first stage in the pipeline ADC, take the subconverter at the stage preceding the latest target subconverter in the pipeline ADC as the latest target subconverter, set i as the initial value, and re-send the initial value to the first processing module for processing;
and the seventh processing module is used for ending the flow if the latest target subconverter is a subconverter positioned at the first stage in the pipeline ADC.
8. The device for calibrating a switch capacitor in a pipelined ADC according to claim 5, wherein said calculation module is specifically configured to:
Calculating to obtain an actual capacitance value of a switch capacitor in an ith branch in a DAC module in the latest target subconverter through the following formula;
wherein C is i For the actual capacitance value of the switched capacitor in the ith branch of the DAC module in the latest target subconverter, V ref C is the voltage value of the positive reference voltage source in the ith branch in the DAC module in the latest target subconverter F For the most recent capacitance value of the feedback capacitance in the target subconverter, V out (T i =1) is the latest first residual signal, V out (T i = -1) is the latest second residual signal.
9. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the steps of the method of calibrating switched capacitance in a pipelined ADC as claimed in any one of claims 1 to 4.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the method of calibrating switched capacitors in a pipelined ADC as claimed in any one of claims 1 to 4.
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| CN202310117197.6A CN116015293A (en) | 2023-02-01 | 2023-02-01 | Calibration method and device for switch capacitor in pipelined ADC (analog-to-digital converter) |
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| CN202310117197.6A CN116015293A (en) | 2023-02-01 | 2023-02-01 | Calibration method and device for switch capacitor in pipelined ADC (analog-to-digital converter) |
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