CN116015250A - Improved relaxation oscillator - Google Patents

Improved relaxation oscillator Download PDF

Info

Publication number
CN116015250A
CN116015250A CN202111232764.XA CN202111232764A CN116015250A CN 116015250 A CN116015250 A CN 116015250A CN 202111232764 A CN202111232764 A CN 202111232764A CN 116015250 A CN116015250 A CN 116015250A
Authority
CN
China
Prior art keywords
comparator
input end
phase input
control
cla
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111232764.XA
Other languages
Chinese (zh)
Other versions
CN116015250B (en
Inventor
刘兆哲
满雪成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SG Micro Beijing Co Ltd
Original Assignee
SG Micro Beijing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SG Micro Beijing Co Ltd filed Critical SG Micro Beijing Co Ltd
Priority to CN202111232764.XA priority Critical patent/CN116015250B/en
Priority claimed from CN202111232764.XA external-priority patent/CN116015250B/en
Publication of CN116015250A publication Critical patent/CN116015250A/en
Application granted granted Critical
Publication of CN116015250B publication Critical patent/CN116015250B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

An improved relaxation oscillator, characterized by: the oscillator comprises a comparator; wherein the comparator is connected with a control signal and based on the control signal
Figure DDA0003316503050000011
The input signal in the interval of level switching of the non-overlapping clock signals realizes the recovery of the output voltage of the comparator. The method is simple, few elements are added in the circuit, the control signal is accurate, the output of the comparator can be effectively controlled in the period of unstable output of the comparator, and meanwhile, the working state of the comparator in the normal period is not influenced.

Description

Improved relaxation oscillator
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to an improved relaxation oscillator.
Background
Currently, relaxation oscillators are widely used in various integrated circuits. In general, a relaxation oscillator can be controlled with respect to a comparator inside thereof based on a control signal, and oscillation is achieved by a flipping process performed by the comparator. In the prior art, the negative input voltage of the comparator is a stable reference voltage provided by a resistor, and the positive input voltage is a non-overlapping clock signal
Figure BDA0003316503030000011
And->
Figure BDA0003316503030000012
Provided in combination. According toNon-overlapping clock signal->
Figure BDA0003316503030000013
And->
Figure BDA0003316503030000014
Is of two different amplitude levels V 1 And V 2 Alternately inputted to the non-inverting input terminal of the comparator. Thus, two different levels V 1 、V 2 Respectively with negative phase input terminal voltage V ref The comparison is performed to achieve a constant flip of the comparator.
However, the relaxation oscillator in the prior art has a serious defect. That is, due to the clock signal
Figure BDA0003316503030000015
And
Figure BDA0003316503030000016
is non-overlapping, so that there must be a short non-overlapping time, so that two clock signals +.>
Figure BDA0003316503030000017
And->
Figure BDA0003316503030000018
The values of (2) are all low. And if the clock signal is%>
Figure BDA0003316503030000019
And->
Figure BDA00033165030300000110
When the values of the two PMOS transistors are low, the PMOS transistors at the positive and negative phase input ends of the comparator are in a conducting state, the drain states of the two PMOS transistors in the comparator are not fixed, the drain voltages of the two PMOS transistors are dithered in the period, and the fixed and stable current injection still cannot be maintained after the dithering. This makes the output voltage of the comparator impossible to determine, and therefore, there is a possibility thatResulting in an unnecessary inversion of the output voltage of the comparator and thus an error of the oscillating signal output by the relaxation oscillator.
In order to avoid this, there is a need for an improved relaxation oscillator.
Disclosure of Invention
To solve the deficiencies of the prior art, it is an object of the present invention to provide an improved relaxation oscillator for controlling the output voltage of a comparator in a section where non-overlapping clock signals are level-switched by adding a control signal to the comparator.
The invention adopts the following technical scheme.
An improved relaxation oscillator, wherein the oscillator comprises a comparator; the comparator is connected with the control signal and based on the control signal
Figure BDA00033165030300000111
The input signal in the section where the non-overlapping clock signals are level switched achieves recovery of the comparator output voltage.
Preferably, the recovery of the comparator output voltage includes: output voltage V of comparator CLA Will not be in a low state continuously; output voltage V of comparator CLA In the interval of level switching of non-overlapped clock signals, the control signal is based on
Figure BDA0003316503030000021
The control of (2) is restored to the stable voltage of the non-overlapping clock signal before the level switching is performed.
Preferably, the control signal
Figure BDA0003316503030000022
Non-overlapping clock signal based on relaxation oscillator>
Figure BDA0003316503030000023
And->
Figure BDA0003316503030000024
By passing throughOr-operation.
Preferably, the comparator comprises a control current source, a first control end, a second control end and a third control end; one end of the control current source is connected with the power supply voltage, and the other end of the control current source is connected with the grid electrode and the drain electrode of the NMOS tube of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator through the first control end; one end of the second control end is connected with the drain electrode of the PMOS tube at the negative phase input end in the comparator, and the other end of the second control end is grounded; a third control end, one end of which is connected with the power supply voltage and the other end of which is respectively connected with the input end of the inverter and the output current source I in the comparator CLA Is connected to one end of the connecting rod.
Preferably, the comparator comprises an input current source I CMP Positive phase input end PMOS tube and NMOS tube, negative phase input end PMOS tube and NMOS tube, output current source I CLA Output power tube M CLA And an inverter; wherein the input current source I CMP One end of the positive phase input end PMOS tube is connected with the source electrode of the positive phase input end PMOS tube, and the other end of the positive phase input end PMOS tube is connected with the source electrode of the negative phase input end PMOS tube respectively; the grid electrode of the positive phase input end PMOS tube is used as the positive phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the positive phase input end NMOS tube, the grid electrode of the negative phase input end NMOS tube, and the source electrode of the positive phase input end NMOS tube is grounded; the grid electrode of the PMOS tube at the negative phase input end is used as the negative phase input end of the comparator, and the drain electrode of the PMOS tube at the negative phase input end and the drain electrode of the NMOS tube at the negative phase input end are used as the output power tube M CLA The grid electrodes of the NMOS transistors at the negative phase input end are respectively connected, and the source electrodes of the NMOS transistors at the negative phase input end are grounded; output current source I CLA One end of the power supply is connected with the power supply voltage, and the other end is connected with the input end of the phase inverter and the output power tube M CLA Drain electrode connection of output power tube M CLA The source of the inverter is grounded and the output of the comparator is the output of the inverter.
Preferably, when the control signal
Figure BDA0003316503030000025
When the voltage is in a high level state, the control current source and the first control end stabilize the grid voltages of NMOS tubes of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator.
Preferably, the secondA control end for controlling signals
Figure BDA0003316503030000026
When the power supply is in a high level state, the output power tube M is controlled CLA Is in a low state.
Preferably, the third control terminal is connected with the control signal
Figure BDA0003316503030000027
When the voltage is in a high level state, the input end voltage of the control inverter is the power supply voltage.
Preferably, when the control signal
Figure BDA0003316503030000028
In the low state, the first to third control terminals disconnect the control of the comparator.
Preferably, the first to third control terminals are closed when the non-overlapping clock signals are in the level-switching interval; when the non-overlapping clock signals are not in the level switching interval, the first to third control terminals are disconnected.
Compared with the prior art, the improved relaxation oscillator has the advantages that the control signal can be added into the comparator to control the output voltage of the comparator in the interval of level switching of non-overlapping clock signals. The method is simple, few elements are added in the circuit, the control signal is accurate, the output of the comparator can be effectively controlled in the period of unstable output of the comparator, and meanwhile, the working state of the comparator in the normal period is not influenced.
The beneficial effects of the invention also include:
1. the method effectively controls the output voltage of the comparator, thereby preventing the unnecessary overturn of the output voltage of the comparator in an unstable interval and ensuring the reliability and the accuracy of the output signal of the relaxation oscillator.
2. The method of the invention can quickly recover the output voltage, reduce the recovery time of the output voltage and ensure that the output voltage is more stable.
Drawings
FIG. 1 is a schematic diagram of a prior art relaxation oscillator;
FIG. 2 is a schematic diagram showing a circuit structure of a comparator in a relaxation oscillator according to the prior art;
FIG. 3 is a schematic diagram of a voltage curve of a comparator circuit of the prior art under normal operation of a relaxation oscillator;
FIG. 4 is a schematic diagram of a voltage curve of a comparator in case of false inversion under abnormal operation of a relaxation oscillator in the prior art;
FIG. 5 is a schematic diagram of a circuit configuration of an improved relaxation oscillator of the present invention;
FIG. 6 is a schematic diagram of the voltage curve of the comparator circuit of the improved relaxation oscillator under normal operation;
fig. 7 is a schematic diagram of a voltage curve of a comparator circuit under non-overlapping clock intervals for normal operation of an improved relaxation oscillator according to the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solutions of the present invention and are not intended to limit the scope of protection of the present application.
Fig. 1 is a schematic circuit diagram of a relaxation oscillator in the prior art. As shown in fig. 1, a relaxation oscillator commonly used in the prior art generally includes a comparator, a control circuit at an input of the comparator, and a logic circuit at an output of the comparator. The circuit signal at the non-inverting input of the comparator input can be based on two different voltages V 1 And V 2 And (3) controlling the alternate switching.
Specifically, current source I 1 Capacitance C 1 Control switch
Figure BDA0003316503030000041
And->
Figure BDA0003316503030000042
A first branch is formed for providing a first voltage V for the comparator 1 And a current source I 2 Capacitance C 2 And control switch->
Figure BDA0003316503030000043
And->
Figure BDA0003316503030000044
A second branch is formed for providing a second voltage V for the comparator 2 。
In the invention, the first and second voltages V 1 And V 2 Can be respectively based on a control switch
Figure BDA0003316503030000045
And->
Figure BDA0003316503030000046
Realizing alternate input to the comparator and voltage V at the negative phase input end of the comparator mn A comparison is made.
It can be seen that the comparator plays an essential role in the overall oscillator and can be used to determine the difference between the voltages at the inputs and to determine the switching time of the oscillator output.
Fig. 2 is a schematic circuit diagram of a comparator in a relaxation oscillator according to the prior art. As shown in fig. 2, the comparator is operated with the current source I supplied by the amplifier current cmp While the current source I is provided by the part of Class-A in the amplifier cla Is set in the above-described range). When two non-overlapping clock signals
Figure BDA0003316503030000047
And->
Figure BDA0003316503030000048
While in low state, V in circuit cnp Obvious jitter occurs and stable current injection is not maintained after jitter. Thus, in the state where clocks are not overlapped, V np And V is equal to nn The voltage at both points is unstable.
The non-overlapping clock signals in the present invention refer to overlapping states in which two clock signals are not at the same time high level in order to avoid an output error of the comparator. That is, in order to prevent this from happening, the falling edge of one clock signal is positioned before the rising edge of the other clock signal, so that the two signals do not overlap at a high level by providing a very short non-overlapping period between the falling edge of one signal and the rising edge of the other signal. Hereinafter, for this very short non-overlapping period, a non-overlapping section is simply used for description.
Fig. 3 is a schematic diagram of a voltage curve of a comparator circuit of the prior art under normal operation of a relaxation oscillator. As shown in FIG. 3, V is likely to be caused due to the unstable state of the two voltages np During climbing, the output power tube M is reached or exceeded again CLA Is set to a threshold starting voltage of (1). When V is np After the threshold starting voltage of the power tube is larger than the threshold starting voltage of the power tube, the output power tube is conducted to enable the voltage V to be CLA The energy of (2) is led out to the ground through the source leakage current of the power tube, and the voltage V CLA Is set to 0 and after passing through the inverter, outputs a voltage V o A rising edge occurs and a flip of the high and low levels occurs. At the end of the non-overlapping interval, when V mp After the voltage switching is completed, the voltage is stabilized at V 1 Or V 2 At this time, V np Will gradually decrease with the conduction of the two mirror NMOS transistors, and output the power tube M cla No longer conduct at this time V CLA Restoring to the voltage state of Class-A and outputting V o A falling edge is generated.
Generally, the clock signal is at the end of one or half period, following V, before entering the non-overlapping region by the falling edge mp Rise of voltage signal, when V mp Voltage higher than V mn V in the comparator np Will gradually rise from a low state, thereby making M CLA The tube is conducted and the voltage V CLA And (3) lowering.
Fig. 4 is a schematic diagram of a voltage curve when a comparator is turned over by mistake under an abnormal operation condition of a relaxation oscillator in the prior art. As shown in FIG. 4, after two clock signals enter the non-overlapping interval, V np Is in an indeterminate jitter state, at this time, if V np Is continuously in a higher state, M CLA The tube is always on, resulting in a voltage V CLA Always in a low state, cannot rise. Even when the clock signal is switched so that V mp The voltage of the power tube M rises again CLA Also, a certain time is required to recover the off state and the voltage V cla And raised again.
In addition, since V is within the non-overlapping section np And V nn Is not determinable if during this period of time, V is caused by possible uncertainty factors such as clock feedthrough np Excessive jitter, V np May occur below the output power tube M CLA In the case of the threshold voltage of (2), the output power tube may be turned from the on state to the off state, voltage V CLA Rise and output voltage V o And (5) overturning. In this case due to V np Is unstable and outputs voltage V o Multiple unnecessary upsets may occur, greatly reducing the stability and accuracy of the oscillator output signal.
In view of the above problems, the present invention provides an improved relaxation oscillator capable of reducing V by improving the operation state of a comparator in a non-overlapping section CLA Degree of instability of output state, and will V CLA The time at low level is greatly reduced.
Fig. 5 is a schematic circuit diagram of an improved relaxation oscillator according to the present invention. As shown in fig. 5, an improved relaxation oscillator, wherein the oscillator includes a comparator; the comparator is connected with the control signal and based on the control signal
Figure BDA0003316503030000051
In non-overlapping clock signalsThe input signal in the section where the level switching is performed realizes the recovery of the output voltage of the comparator.
It will be appreciated that in the present invention, the oscillator is generally similar in structure to the prior art by providing a voltage V to the non-inverting input of the comparator that is alternately switched over with clock cycles 1 And V 2 Providing a stable reference voltage V to the negative phase input of the comparator ref Thereby realizing V 1 、V 2 And V is equal to ref And generates an oscillating output signal.
Unlike the oscillator in the prior art, the internal structure of the comparator is improved, and the prior comparator cannot realize stable output in a non-overlapping interval, so that the state of an output signal is uncontrollable, and the output signal of the oscillator is unstable. The comparator is improved, so that the comparator can realize stable output in a non-overlapping interval and quickly restore the output voltage to an original state.
Preferably, the recovery of the comparator output voltage comprises: output voltage V of comparator CLA Will not be in a low state continuously; output voltage V of comparator CLA In the interval of level switching of non-overlapped clock signals, the control signal is based on
Figure BDA0003316503030000061
The control of (2) is restored to the stable voltage of the non-overlapping clock signal before the level switching is performed.
Fig. 6 is a schematic diagram of the voltage curve of the comparator circuit of the improved relaxation oscillator under normal operation. As shown in FIG. 6, V in the figure CLA The voltage state of (2) is quickly restored to high level in non-overlapping interval, thereby enabling the output voltage V o And (5) resetting to zero again. Compared with the content shown in fig. 3 in the prior art, V CLA Compared with the state that the voltage is recovered to the high level after the non-overlapping interval is ended for a long time, the circuit provided by the invention effectively ensures that the output voltage is recovered rapidly, and the accuracy of the output clock pulse is greatly improved.
Preferably, the control signal
Figure BDA0003316503030000062
Non-overlapping clock signal based on relaxation oscillator>
Figure BDA0003316503030000063
And->
Figure BDA0003316503030000064
Obtained by nor operation.
It can be understood that in the present invention, since the improved partial circuit only controls the output state of the comparator in the non-overlapping interval, and in other signal period intervals, the normal working state of the comparator is not disturbed, therefore, in the present invention, a control signal is adopted
Figure BDA0003316503030000065
The identification of non-overlapping intervals is achieved.
Specifically, control signals
Figure BDA0003316503030000066
Is based on nor gate implementation. In an embodiment of the invention, two non-overlapping clock signals of the relaxation oscillator can be used>
Figure BDA0003316503030000067
And->
Figure BDA0003316503030000068
And performing NOR operation. It will be readily appreciated that the non-overlapping interval is simply two signals
Figure BDA0003316503030000069
And->
Figure BDA00033165030300000610
The sections, which are all in a low state, thus obtained control signal +.>
Figure BDA00033165030300000611
Only at +.>
Figure BDA00033165030300000612
And->
Figure BDA00033165030300000613
Can be high only in the low state, and in other times the control signal +.>
Figure BDA00033165030300000614
The values of (2) are all 0. By the method, the identification of the non-overlapping interval is effectively realized.
Preferably, the comparator comprises a control current source, a first control terminal, a second control terminal and a third control terminal; one end of the control current source is connected with the power supply voltage, and the other end of the control current source is connected with the grid electrode and the drain electrode of the NMOS tube of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator through the first control end; one end of the second control end is connected with the drain electrode of the PMOS tube at the negative phase input end in the comparator, and the other end of the second control end is grounded; a third control end, one end of which is connected with the power supply voltage and the other end of which is respectively connected with the input end of the inverter and the output current source I in the comparator CLA Is connected to one end of the connecting rod.
In the present invention, the control signal described above can be used
Figure BDA0003316503030000071
To achieve improved and controlled internal circuitry of the comparator. The specific connection mode of the control signal is shown in fig. 5.
Preferably, the comparator comprises an input current source I CMP Positive phase input end PMOS tube and NMOS tube, negative phase input end PMOS tube and NMOS tube, output current source I CLA Output power tube M CLA And an inverter; wherein the input current source I CMP One end of the positive phase input end PMOS tube is connected with the source electrode of the positive phase input end PMOS tube, and the other end of the positive phase input end PMOS tube is connected with the source electrode of the negative phase input end PMOS tube respectively; the grid electrode of the PMOS tube at the positive input end is used as the positive input of the comparatorThe drain electrode of the positive phase input end NMOS tube is respectively connected with the drain electrode, the grid electrode and the grid electrode of the negative phase input end NMOS tube, and the source electrode of the positive phase input end NMOS tube is grounded; the grid electrode of the PMOS tube at the negative phase input end is used as the negative phase input end of the comparator, and the drain electrode of the PMOS tube at the negative phase input end and the drain electrode of the NMOS tube at the negative phase input end are used as the output power tube M CLA The grid electrodes of the NMOS transistors at the negative phase input end are respectively connected, and the source electrodes of the NMOS transistors at the negative phase input end are grounded; output current source I CLA One end of the power supply is connected with the power supply voltage, and the other end is connected with the input end of the phase inverter and the output power tube M CLA The drain electrode of the output power tube MCLA is grounded, and the output end of the inverter is used as the output end of the comparator.
It will be appreciated that the circuit configuration of the other parts of the comparator of the present invention is similar to that of the prior art.
Preferably, when the control signal
Figure BDA0003316503030000072
When the voltage is in a high level state, the control current source and the first control end stabilize the grid voltages of NMOS tubes of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator.
It will be appreciated that after increasing the control of the control signal to the internal circuitry of the comparator, when the comparator is operating in the non-overlapping region, V nn The voltage can be controlled by a control current source to ensure the stable state, when the grid voltage V of the NMOS tube nn After being in a stable state, V np The voltage state of (c) can be kept stable.
Preferably, the second control terminal is connected with the control signal
Figure BDA0003316503030000073
When the power supply is in a high level state, the output power tube M is controlled CLA Is in a low state.
It can be understood that the second control terminal in the present invention, when the comparator is in the non-overlapping region, the control signal can enable V in the circuit np Is connected to ground level so that V np The voltage of (2) decreases rapidly to 0V. At the same time due to V np After the voltage of (2) is reduced to 0, the output power tube V CLA Can be rapidly closed from the on state, thereby raising V CLA Is set in the above-described voltage range.
Preferably, the third control terminal is connected with the control signal
Figure BDA0003316503030000081
When the voltage is in a high level state, the input end voltage of the control inverter is the power supply voltage.
The invention also comprises a third control end which can control V in a non-overlapping interval CLA To a state of the power supply voltage, thereby causing an output voltage V output through the inverter o Is kept at 0V.
Fig. 7 is a schematic diagram of a voltage curve of a comparator circuit under non-overlapping clock intervals for normal operation of an improved relaxation oscillator according to the present invention. As shown in fig. 7, the improved comparator, after a very short time in the non-overlapping region, V np Will decrease to 0 and at the same time be subjected to V np Controlled voltage V CLA The recovery is rapid so that the clock pulse is accurate and brief.
Preferably, when the control signal
Figure BDA0003316503030000082
In the low state, the first to third control terminals disconnect the control of the comparator.
It can be appreciated that the control signal in the present invention is based on the output characteristics of the nor gate
Figure BDA0003316503030000083
The high level is output only in the non-overlapping section, and is in the low level state in the other sections, so that the switch or the like, such as a switching tube, controlled by the control signal is in the low level state. In this state, the plurality of control terminals remain disconnected, and the comparator is not different from the comparator in the prior art.
Preferably, the first to third control terminals are closed when the non-overlapping clock signals are in the interval of level switching; when the non-overlapping clock signals are not in the level switching interval, the first to third control terminals are disconnected.
The control signal can be switched by a switching element such as a MOS tube, so that the control signal has sensitive response capability and no or less time delay.
Compared with the prior art, the improved relaxation oscillator has the advantages that the control signal can be added into the comparator to control the output voltage of the comparator in the interval of level switching of non-overlapping clock signals. The method is simple, few elements are added in the circuit, the control signal is accurate, the output of the comparator can be effectively controlled in the period of unstable output of the comparator, and meanwhile, the working state of the comparator in the normal period is not influenced.
While the applicant has described and illustrated the embodiments of the present invention in detail with reference to the drawings, it should be understood by those skilled in the art that the above embodiments are only preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not to limit the scope of the present invention, but any improvements or modifications based on the spirit of the present invention should fall within the scope of the present invention.

Claims (10)

1. An improved relaxation oscillator, characterized by:
the oscillator comprises a comparator; wherein, the liquid crystal display device comprises a liquid crystal display device,
the comparator is connected with the control signal and based on the control signal
Figure FDA0003316503020000011
The input signal in the interval of level switching of the non-overlapping clock signals realizes the recovery of the output voltage of the comparator.
2. An improved relaxation oscillator as claimed in claim 1, wherein:
the recovery of the comparator output voltage includes: the output voltage V of the comparator CLA Will not be in a low state continuously;
the output voltage V of the comparator CLA In the interval of level switching of non-overlapped clock signals, the control signal is based on
Figure FDA0003316503020000012
Is restored to a stable voltage of the non-overlapping clock signal before level switching is performed.
3. An improved relaxation oscillator as claimed in claim 2, wherein:
the control signal
Figure FDA0003316503020000013
Non-overlapping clock signal based on the relaxation oscillator +.>
Figure FDA0003316503020000014
And->
Figure FDA0003316503020000015
Obtained by nor operation.
4. An improved relaxation oscillator according to claim 3, wherein:
the comparator comprises a control current source, a first control end, a second control end and a third control end; wherein, the liquid crystal display device comprises a liquid crystal display device,
one end of the control current source is connected with the power supply voltage, and the other end of the control current source is connected with the grid electrode and the drain electrode of the NMOS tube of the positive phase input end and the negative phase input end which are mirror images of each other in the comparator through the first control end;
one end of the second control end is connected with the drain electrode of the PMOS tube at the negative phase input end in the comparator, and the other end of the second control end is grounded;
said firstThree control ends, one end is connected with power supply voltage, and the other end is respectively connected with input end of the reverser in the comparator and output current source I CLA Is connected to one end of the connecting rod.
5. An improved relaxation oscillator as claimed in claim 4, wherein:
the comparator comprises an input current source I CMP Positive phase input end PMOS tube and NMOS tube, negative phase input end PMOS tube and NMOS tube, output current source I CLA Output power tube M CLA And an inverter; wherein, the liquid crystal display device comprises a liquid crystal display device,
the input current source I CMP One end of the positive phase input end PMOS tube is connected with the source electrode of the positive phase input end PMOS tube, and the other end of the positive phase input end PMOS tube is connected with the source electrode of the negative phase input end PMOS tube respectively;
the grid electrode of the positive phase input end PMOS tube is used as the positive phase input end of the comparator, the drain electrode is respectively connected with the drain electrode of the positive phase input end NMOS tube, the grid electrode of the negative phase input end NMOS tube, and the source electrode of the positive phase input end NMOS tube is grounded;
the grid electrode of the PMOS tube at the negative phase input end is used as the negative phase input end of the comparator, and the drain electrode of the NMOS tube at the negative phase input end and the output power tube M CLA The grid electrodes of the NMOS transistors at the negative phase input end are respectively connected, and the source electrodes of the NMOS transistors at the negative phase input end are grounded;
the output current source I CLA One end of the power supply is connected with the power supply voltage, and the other end is connected with the input end of the phase inverter and the output power tube M CLA Drain electrode connection of the output power tube M CLA The source of the inverter is grounded and the output of the inverter is used as the output of the comparator.
6. An improved relaxation oscillator as claimed in claim 5, wherein:
when the control signal
Figure FDA0003316503020000021
When the comparator is in a high level state, the control current source and the first control end stabilize the mutual mirror image in the comparatorThe gate voltages of the NMOS transistors at the positive phase input end and the negative phase input end.
7. An improved relaxation oscillator as claimed in claim 6, wherein:
the second control end is arranged on the control signal
Figure FDA0003316503020000022
When the power supply is in a high level state, the output power tube M is controlled CLA Is in a low state.
8. An improved relaxation oscillator as claimed in claim 7, wherein:
the third control end is arranged on the control signal
Figure FDA0003316503020000023
And when the voltage is in a high level state, controlling the voltage of the input end of the inverter to be a power supply voltage.
9. An improved relaxation oscillator as claimed in claim 8, wherein:
when the control signal
Figure FDA0003316503020000024
In the low level state, the first to third control terminals disconnect the control of the comparator.
10. An improved relaxation oscillator as claimed in claim 9, wherein:
when the non-overlapping clock signals are in a level switching interval, the first control end to the third control end are closed;
the first to third control terminals are turned off when the non-overlapping clock signals are not within a level-switching interval.
CN202111232764.XA 2021-10-22 Improved relaxation oscillator Active CN116015250B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111232764.XA CN116015250B (en) 2021-10-22 Improved relaxation oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111232764.XA CN116015250B (en) 2021-10-22 Improved relaxation oscillator

Publications (2)

Publication Number Publication Date
CN116015250A true CN116015250A (en) 2023-04-25
CN116015250B CN116015250B (en) 2024-04-30

Family

ID=

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110228572A1 (en) * 2010-03-16 2011-09-22 Chin-Yen Lin Oscillator having time-variant frequency deviation and related power supply
US20130162230A1 (en) * 2011-12-22 2013-06-27 Fujitsu Semiconductor Limited Dc-dc converter and method of controlling dc-dc converter
CN103546123A (en) * 2013-11-01 2014-01-29 东南大学 High-linearity relaxation oscillator
US20140062596A1 (en) * 2012-08-29 2014-03-06 Analog Devices Technology Chopped oscillator
CN105634445A (en) * 2015-12-28 2016-06-01 北京时代民芯科技有限公司 Frequency-configurable oscillator circuit applied to switching power supply
US20180069531A1 (en) * 2016-09-08 2018-03-08 Nxp Usa, Inc. Low temperature coefficient clock signal generator
WO2018068700A1 (en) * 2016-10-11 2018-04-19 卓捷创芯科技（深圳）有限公司 Half-duplex rfid oscillation maintaining circuit for generating pulse by comparator

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110228572A1 (en) * 2010-03-16 2011-09-22 Chin-Yen Lin Oscillator having time-variant frequency deviation and related power supply
US20130162230A1 (en) * 2011-12-22 2013-06-27 Fujitsu Semiconductor Limited Dc-dc converter and method of controlling dc-dc converter
US20140062596A1 (en) * 2012-08-29 2014-03-06 Analog Devices Technology Chopped oscillator
CN103546123A (en) * 2013-11-01 2014-01-29 东南大学 High-linearity relaxation oscillator
CN105634445A (en) * 2015-12-28 2016-06-01 北京时代民芯科技有限公司 Frequency-configurable oscillator circuit applied to switching power supply
US20180069531A1 (en) * 2016-09-08 2018-03-08 Nxp Usa, Inc. Low temperature coefficient clock signal generator
WO2018068700A1 (en) * 2016-10-11 2018-04-19 卓捷创芯科技（深圳）有限公司 Half-duplex rfid oscillation maintaining circuit for generating pulse by comparator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MATTIA CICALINI: "A 10 MHz Relaxation Oscillator with a novel Jitter Suppression Comparator Autozeroing technique", 2020 27TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 28 December 2020 (2020-12-28) *

Similar Documents

Publication Publication Date Title
KR940005506B1 (en) Flip flop circuit
US11245360B2 (en) Oscillator circuit, chip and electronic device
CN108768363B (en) Tristate zero-crossing comparison circuit and power management chip
TWI650942B (en) Level shifter
CN107425829B (en) Limited duty cycle correction circuit
US20090066385A1 (en) Latch device having low-power data retention
EP0193901B1 (en) Comparator circuit having improved output characteristics
US6583629B1 (en) Magnetic digital signal coupler monitor
TW202006493A (en) Voltage control device
US6449191B1 (en) Current-mode sense amplifier with low power consumption
CN116015250A (en) Improved relaxation oscillator
CN116015250B (en) Improved relaxation oscillator
CN112073050B (en) Power supply power-on reset circuit for semiconductor integrated circuit
US10879858B2 (en) Oscillator circuit using comparator
CN205249155U (en) Cmos crystal oscillator
US10693423B2 (en) Dynamic amplification circuit
CN107947742B (en) Time sequence protection circuit for controlling depletion type power device
JPH0440112A (en) Voltage controlled oscillator
KR20000022620A (en) Amplification circuit and integrated circuit having such and controlling method of the amplification circuit
CN111277261A (en) Level conversion circuit
CN217238254U (en) Clock oscillator's logic signal detection circuitry, MCU chip and BMS chip
CN112511134B (en) Clock signal circuit for correcting high duty ratio
CN113507281B (en) Ring oscillator
CN216794968U (en) Reset circuit
US20230327671A1 (en) Voltage level shifter and operation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant