CN116013976A - Spin field effect transistor and method of manufacturing the same - Google Patents
Spin field effect transistor and method of manufacturing the same Download PDFInfo
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- CN116013976A CN116013976A CN202310182711.4A CN202310182711A CN116013976A CN 116013976 A CN116013976 A CN 116013976A CN 202310182711 A CN202310182711 A CN 202310182711A CN 116013976 A CN116013976 A CN 116013976A
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Abstract
The invention provides a spin field effect transistor and a preparation method thereof, wherein the spin field effect transistor comprises a substrate layer, a semiconductor layer arranged on the substrate layer, a source electrode, a drain electrode, a dielectric layer and a gate electrode arranged on the dielectric layer, wherein the source electrode and the drain electrode are respectively arranged at two ends of the semiconductor layer; the spin field effect transistor utilizes the advantage that the applied grid voltage carries out 'nondestructive' regulation and control on the two-dimensional ferromagnetic semiconductor material, and the two-dimensional ferromagnetic semiconductor material serving as a spin electron conduction channel has atomic-level material thickness and has more sensitive response to an external electric field perpendicular to an atomic layer plane; therefore, the two-dimensional ferromagnetic semiconductor material has a higher magnetoresistance ratio and switching ratio than the three-dimensional magnetic material, thereby making the performance of the magnetic logic device thereof more excellent.
Description
Technical Field
The invention relates to the technical field of semiconductor materials and devices, in particular to a spin field effect transistor and a preparation method thereof.
Background
Modern electronic technology is rapidly developed, and the traditional devices based on electronic charge properties cannot meet the requirements of integration level and operation speed. In the latter molar age, spintronics is the most promising technology to replace traditional semiconductor transistors at technology nodes below 5 nanometers. The advent of spintronics, which combines the spin characteristics of electrons with the charge characteristics, has generally been studied in devices for spin injection, spin transport, spin detection, spin regulation, and the like of electrons. Thus, the characteristics of the device in the aspects of optics, electricity, magnetism and the like are combined together, and the novel spin electronic device is obtained.
In the prior art, a three-dimensional magnetic material is generally selected to prepare the spin field effect transistor, however, the spin field effect transistor prepared based on the three-dimensional magnetic material has the defects of low switching ratio and low magnetoresistance ratio and poor logic device performance, and the development of the spin field effect transistor is greatly limited.
Therefore, there is a need to provide a new spin field effect transistor and a method for manufacturing the same, which are used for solving the above-mentioned shortcomings of the existing spin field effect transistor.
Disclosure of Invention
The invention aims to provide a spin field effect transistor and a preparation method thereof, which are used for solving the technical problems of low magnetic resistance and low switch ratio of the spin field effect transistor in the prior art.
In order to solve the technical problems, the first solution provided by the present invention is as follows: a spin field effect transistor comprising: the semiconductor device comprises a substrate layer, a semiconductor layer arranged on the substrate layer, a source electrode and a drain electrode respectively arranged at two ends of the semiconductor layer, a dielectric layer arranged between the source electrode and the drain electrode and covering the source electrode and the drain electrode, and a dielectric layer arranged on the dielectric layer;
wherein the semiconductor layer is a monoatomic layer of two-dimensional ferromagnetic semiconductor material.
In the spin field effect transistor provided by the embodiment of the invention, the material of the semiconductor layer is CrCl 3 、CrBr 3 、CrI 3 、Cr 2 Ge 2 Te 6 、Fe 3 GeTe 2 、VI 3 、VSe 2 、MnSe 2 、MnSi、FePS 3 And VTe 2 Any one of the following.
In the spin field effect transistor provided by the embodiment of the invention, the length of the semiconductor layer ranges from 10nm to 200 nm; the thickness of the semiconductor layer ranges between 0.5nm and 10 nm.
In the spin field effect transistor provided by the embodiment of the invention, the source electrode and the drain electrode are made of any one of Fe, co, niFe, coFe, coFeB, laSrMnO, gaMnAs, coFeAl, YFeO and CoFeO.
In the spin field effect transistor provided by the embodiment of the invention, the material of the dielectric layer is any one of SiOx, alOx, siC, hfOx, tiOx and h-BN.
In the spin field effect transistor provided by the embodiment of the invention, the length range of the dielectric layer is between 10nm and 200 nm; the thickness of the dielectric layer ranges between 0.5nm and 10 nm.
In the spin field effect transistor provided by the embodiment of the invention, the material of the gate electrode is at least one of Au, cu, ti, cr, ag, pt and graphene.
In the spin field effect transistor provided by the embodiment of the invention, the substrate layer comprises a first substrate and a second substrate arranged on the first substrate, and the second substrate is in contact with the semiconductor layer;
wherein the material of the first substrate is Si, and the material of the second substrate is SiO 2 。
In order to solve the technical problems, a second solution provided by the present invention is: the preparation method of the spin field effect transistor specifically comprises the following steps:
preparing a semiconductor layer on the surface of the substrate layer;
preparing source electrodes and drain electrodes which are arranged at intervals on the surface of the semiconductor layer;
preparing a dielectric layer on the surfaces of the source electrode and the drain electrode;
and preparing a gate electrode on the surface of the dielectric layer.
In the method for manufacturing a spin field effect transistor according to the embodiment of the present invention, in the step of depositing the semiconductor layer on the surface of the substrate layer, the method for manufacturing the semiconductor layer is selected from at least one of a mechanical lift-off process, a chemical vapor deposition process, a wet transfer process, and a dry transfer process.
The beneficial effects of the invention are as follows: the invention provides a spin field effect transistor and a preparation method thereof, which are different from the prior art in that the spin field effect transistor comprises a substrate layer, a semiconductor layer arranged on the substrate layer, a source electrode and a drain electrode respectively arranged at two ends of the semiconductor layer, a dielectric layer arranged between the source electrode and the drain electrode and covering the source electrode and the drain electrode, and a two-dimensional ferromagnetic semiconductor material arranged on the dielectric layer, wherein the semiconductor layer is a monoatomic layer; the spin field effect transistor uses the two-dimensional ferromagnetic semiconductor material as a two-dimensional electron gas channel of the spin field effect transistor, and utilizes the advantage of 'non-damage' regulation and control of the two-dimensional ferromagnetic semiconductor material by the applied gate voltage, and the two-dimensional ferromagnetic semiconductor material as a spin electron conduction channel has atomic-level material thickness and has more sensitive response to an external electric field perpendicular to an atomic layer plane; therefore, the two-dimensional ferromagnetic semiconductor material has a higher magnetoresistance ratio and switching ratio than the three-dimensional magnetic material, thereby making the performance of the magnetic logic device thereof more excellent.
Drawings
FIG. 1 is a schematic cross-sectional view of an embodiment of a spin field effect transistor according to the present invention;
FIG. 2 is a schematic flow chart of a method of fabricating a spin field effect transistor according to the present invention;
FIG. 3 is a graph of the characteristics of a spin field effect transistor according to the present invention between source and drain voltages and spin up and spin down currents for numerical modeling under different biases;
FIG. 4 is a graph of the magnetic resistance characteristics of the spin field effect transistor according to the present invention for numerical simulation at different source drain voltages.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
Referring to FIG. 1, a schematic cross-sectional structure of a spin field effect transistor 100 according to an embodiment of the invention is shown; the spin field effect transistor 100 includes: a substrate layer 11, a semiconductor layer 12 provided on the substrate layer 11, a source electrode 13 and a drain electrode 14 provided at both ends on the semiconductor layer 12, respectively, a dielectric layer 15 provided between the source electrode 13 and the drain electrode 14 and covering the source electrode 13 and the drain electrode 14, and a gate electrode 16 provided on the dielectric layer 15;
wherein the semiconductor layer 12 is a monoatomic layer of two-dimensional ferromagnetic semiconductor material.
It will be appreciated that the source and drain electrodes 13, 14 above are provided with a channel having a length in the range of 10nm to 150nm, the source and drain electrodes 13, 14 respectively being in contact with respective metal conductive electrodes to provide a bias voltage V applied between the drain and source electrodes 14, 13 DS 。
The spin field effect transistor 100 is biased at V DS By which spin electrons are supplied by the ferromagnetic source electrode 13 and drain electrode 14, thereby allowing a spin-polarized current to flow through the semiconductor layer 12 serving as a two-dimensional electron gas channel. The spin precession effect caused by spin orbit coupling can be effectively regulated by applying a voltage to the gate electrode 16 terminal, so that when spin electrons are diffused from the source electrode 13 to the drain electrode 14, the spin polarization direction is the same as or opposite to the magnetization direction of the drain electrode 14, thereby realizing the conduction and closing of the channel. Thereby effectively adjusting spin polarization and magnetoresistance.
Specifically, in the embodiment of the present invention, the substrate layer 11 includes a first substrateA substrate 111 and a second substrate 112 provided on the first substrate 111, the second substrate 112 being in contact with the semiconductor layer 12; wherein the material of the first substrate 111 is Si, and the material of the second substrate 112 is SiO 2 . The substrate layer 11 is preferably a single-sided thermally oxidized Si/SiOx substrate, more preferably a single-sided highly doped single-sided thermally oxidized Si/SiOx substrate. The main purpose of the substrate layer 11 is to act as a carrier for the spin field effect transistor 100, and the gate voltage can be applied using a highly doped substrate as a back gate, as necessary. The thickness and size of the substrate layer 11 are not particularly limited in this application.
In the embodiment of the present invention, the material of the semiconductor layer 12 is CrCl 3 、CrBr 3 、CrI 3 、Cr 2 Ge 2 Te 6 、Fe 3 GeTe 2 、VI 3 、VSe 2 、MnSe 2 、MnSi、FePS 3 And VTe 2 Any one of them; the semiconductor layer 12 has a length ranging from 10nm to 200nm and the semiconductor layer 12 has a thickness ranging from 0.5nm to 10 nm. Since the semiconductor layer 12 has a certain carrier concentration, the efficiency of spin carrier injection of the spin field effect transistor 100 can be effectively improved by forming a first PN junction or a first built-in electric field between the semiconductor layer 12 and the source electrode 13 and forming a second PN junction or a second built-in electric field between the semiconductor layer 12 and the drain electrode 14.
Further, the two-dimensional ferromagnetic semiconductor material can be electrostatically doped under the action of a gate voltage, and a large number of cruising spin electrons are generated in the material, and the cruising spin electrons can strengthen the exchange action among magnetic ions. After the concentration of the tour spin electrons reaches a threshold value, stokes ferromagnetism can be generated.
In the embodiment of the invention, the Curie temperature of the two-dimensional ferromagnetic semiconductor material can be increased to above room temperature under the action of gate voltage; thus, the spin field effect transistor 100 based on the two-dimensional ferromagnetic semiconductor material can also stably operate at room temperature.
In the embodiment of the present invention, the source electrode 13 and the drain electrode 14 are provided at both ends on the semiconductor layer 12. The region between the source electrode 13 and the drain electrode 14 is a channel; the source electrode 13 and the drain electrode 14 are made of any one of Fe, co, niFe, coFe, coFeB, laSrMnO, gaMnAs, coFeAl, YFeO and CoFeO.
The invention can make the coercive fields of the source electrode 13 and the drain electrode 14 different by setting the shapes and the thicknesses of the source electrode 13 and the drain electrode 14 to be different.
When the spin field effect transistor 100 provided in the embodiment of the present invention works, a current is introduced between the source electrode 13 and the drain electrode 14, spin carriers are effectively injected into the first PN junction formed adjacent to the semiconductor layer 12 through the source electrode 13, and under the effect of spin orbit coupling and spin precession, spin parallel and non-parallel states can be detected at the drain electrode 14 by the electron spin under the control of the gate voltage, corresponding to different resistance states.
When the magnetization directions of the source electrode 13 and the drain electrode 14 are the same, the spin field effect transistor 100 is in a low resistance state, and the spin field effect transistor 100 is turned on; when the magnetization directions of the source and the drain are different, the spin field effect transistor 100 is in a high resistance state, and the spin field effect transistor 100 is turned off.
In the embodiment of the invention, the material of the dielectric layer 15 is any one of SiOx, alOx, siC, hfOx, tiOx and h-BN; wherein the length of the dielectric layer 15 ranges between 10nm and 200 nm; the thickness of the dielectric layer 15 ranges between 0.5nm and 10 nm.
In the embodiment of the present invention, the material of the gate electrode 16 may be selected from one or more of Au, cu, ti, cr, ag and Pt, or an alloy material formed by the material or a semi-metal material such as graphene, and the material is used as a top gate, and the voltage of the top gate is adjusted to change the spin direction of the spin electrons in the conductive channel, so as to adjust the magnitude of spin current between the source electrode 13 and the drain electrode 14 in the device. In the embodiment of the invention, a certain gate voltage is applied to the gate electrode 16, and the magnitude of the gate electric field is controlled to enable the spin orientation of polarized carriers in the channel to precess and turn, so that the resistance state between the source electrode 13 and the drain electrode 14 can be adjusted.
Referring to fig. 1 and 2, fig. 2 is a flow chart of a method for manufacturing a spin field effect transistor 100 according to the present invention; the method specifically comprises the following steps:
s10, preparing a semiconductor layer 12 on the surface of the substrate layer 11.
Specifically, S10 further includes:
the semiconductor layer 12 is first formed on the silicon dioxide surface of the substrate layer 11 using a two-dimensional ferromagnetic semiconductor material of a monoatomic layer using at least one of a mechanical lift-off process, a chemical vapor deposition process, a wet transfer process, and a dry transfer process.
S20, source electrode 13 and drain electrode 14 are provided on the surface of semiconductor layer 12 at intervals.
Specifically, S20 further includes:
a ferromagnetic source electrode 13 and a ferromagnetic drain electrode 14 are formed on both ends of the semiconductor layer 12 by means of one or more of magnetron sputtering, electron beam evaporation or chemical vapor deposition by means of a mask or a photolithography.
And S30, preparing a dielectric layer 15 on the surfaces of the source electrode 13 and the drain electrode 14.
Specifically, S30 further includes:
the dielectric layer 15 is formed by atomic layer deposition techniques overlying the device upper side with dielectric layer 15 material.
And S40, preparing the gate electrode 16 on the surface of the dielectric layer 15.
Specifically, S40 further includes:
a gate electrode 16 is formed on the dielectric layer 15 material using one or more of magnetron sputtering, electron beam evaporation, or chemical vapor deposition methods.
Referring to fig. 3, fig. 3 is a graph showing the characteristics of the spin field effect transistor 100 according to the present invention between the source-drain voltage and the spin-up and spin-down currents under different biases; in the spin field effect transistor 100, the first substrate 111 is Si, and the second substrate 112 is SiO 2 The semiconductor layer 12 is CrI of monoatomic layer 3 Co/Fe alloy is selected as the source electrode 13 and the drain electrode 14, and Al is selected as the dielectric layer 15 2 O 3 The gate electrode 16 is made of Ti/Au alloy.
In the case of the view of figure 3,the abscissa is the bias voltage V between the drain electrode 14 and the source electrode 13 ds On the ordinate is the different bias voltage V ds The corresponding current is lower; specifically, when the voltage of the gate electrode 16 is constant, the bias voltage V is different by testing ds The current-voltage curves of the following different currents are obtained:
the current 1 is a majority of spin electron currents in which the magnetization directions of the source electrode 13 and the drain electrode 14 are parallel; the current 2 is a minority spin-electron current in which the magnetization directions of the source electrode 13 and the drain electrode 14 are parallel; the current 3 is a majority of spin electron current in which the magnetization directions of the source electrode 13 and the drain electrode 14 are antiparallel; the current 4 is a minority spin-electron current in which the magnetization directions of the source electrode 13 and the drain electrode 14 are antiparallel.
Wherein, most spin electrons are electrons with upward spin, and few spin electrons are electrons with downward spin.
Comparing the current 1 with the current 2, it can be seen that the spin field effect transistor 100 exhibits a low resistance state when the magnetization directions of the source electrode 13 and the drain electrode 14 are parallel, and the bias voltage V between the drain electrode 14 and the source electrode 13 is then ds The effect on the majority and minority spintrons is not great. Electrons in the spin direction (majority spin electrons) can penetrate the semiconductor layer 12, and the majority spin electron current is larger than the on current (100A or more), and the spin field effect transistor 100 exhibits an on state; meanwhile, electrons (minority spin electrons) having downward spin hardly penetrate the semiconductor layer 12, and the minority spin current is relatively small (about 0.01A).
Comparing the current 3 with the current 4, it is known that the spin field effect transistor 100 exhibits a high resistance state when the magnetization directions of the source electrode 13 and the drain electrode 14 are antiparallel, and the bias voltage V between the drain electrode 14 and the source electrode 13 ds The influence on most spintrons is large. When the bias voltage V between the drain electrode 14 and the source electrode 13 ds When the spin-up electrons (most spin electrons) can penetrate the semiconductor layer 12 and most spin electron currents (more than 100A) are much larger than the on-current, the spin field effect transistor 100 is in an on state; when the bias voltage V between the drain electrode 14 and the source electrode 13 DS At 0, electrons in the spin direction (most spin electrons) cannot penetrate the semiconductor layer 12, and most spin electron currents approach 0, and the spin field effect transistor 100 exhibits an off state; meanwhile, electrons (minority spin electrons) having downward spin are difficult to penetrate the semiconductor layer 12 at all times, and thus the bias voltage V between the drain electrode 14 and the source electrode 13 ds The influence on the minority spin current is relatively small (about 0.01A).
Referring to fig. 4, a diagram of a characteristic of magnetic resistance of the spin field effect transistor 100 according to the present invention under different source/drain voltages is shown; wherein the abscissa is the bias voltage V between the drain electrode 14 and the source electrode 13 DS (in volts), the ordinate is the magnetoresistance ratio (henry, c) of the spin field effect transistor 100; the experimental test method comprises the following steps:
first, the source electrode 13 and the drain electrode 14 made of Co/Fe material are magnetized by a magnetic field generator in the same direction. The general procedure of field effect transistor performance measurement is then carried out: at a gate voltage of 0, a bias voltage V is applied DS Testing to obtain a current-voltage curve; thereafter, a voltage V is applied to the gate electrode 16 GS In 5 measurements, V GS Sequentially 1V, 2V, 3V, 4V and 5V to obtain different current-voltage curves; then, a bias voltage V is applied between the source electrode 13 and the drain electrode 14 while a certain gate electrode 16 voltage is fixed DS Increasing with 0.1V, which is 0.1V, 0.2V, 0.3V … … 2.8.2.8V, 2.9V and 3V in sequence; measurement for each gate voltage, bias was applied to test a first current bias curve (I PC )。
Simultaneously, the source electrode 13 and the drain electrode 14 which are made of Co/Fe materials are magnetized by using a magnetic field generator, and the magnetization directions are opposite. The general procedure of field effect transistor performance measurement is then carried out: at a gate voltage of 0, a bias voltage V is applied ds Testing to obtain a current-voltage curve; thereafter, a voltage V is applied to the gate electrode 16 GS In 5 measurements, V GS Sequentially 1V, 2V, 3V, 4V and 5V to obtain different current-voltage curves; then, a bias voltage V is applied between the source electrode 13 and the drain electrode 14 while a certain gate electrode 16 voltage is fixed DS Increasing by 0.1V, in turn0.1V, 0.2V, 0.3V … … 2.8.2.8V, 2.9V, 3V; measurement for each gate voltage, bias was applied to test a second current bias curve (I APC ). Finally, a calculation is made for the magnetoresistance ratio curve at the voltage of each gate electrode 16: MR (%) = (I PC -I APC )/I APC 100% and a magnetoresistance ratio characteristic map shown in fig. four was obtained.
As can be seen from FIG. 4, when the bias voltage V between the drain electrode 14 and the source electrode 13 DS With negative voltage, with bias V DS The increase in value, the magnetoresistance ratio of the spin field effect transistor 100 also increases linearly; when the bias voltage V between the source electrode 13 and the drain electrode 14 DS At 0, the magnetoresistance ratio of the spin field effect transistor 100 is maximum; when the bias voltage V between the drain electrode 14 and the source electrode 13 DS With forward voltage, with bias voltage V DS The increase in value also linearly decreases the magnetoresistance ratio of the spin field effect transistor 100.
Unlike the prior art, the present invention provides a spin field effect transistor 100 and a method of fabricating the same, the spin field effect transistor 100 comprising a substrate layer 11, a semiconductor layer 12 disposed on the substrate layer 11, a source electrode 13 and a drain electrode 14 disposed on both ends of the semiconductor layer 12, respectively, a dielectric layer 15 disposed between the source electrode 13 and the drain electrode 14 and covering the source electrode 13 and the drain electrode 14, and disposed on the dielectric layer 15, wherein the semiconductor layer 12 is a two-dimensional ferromagnetic semiconductor material of a single atomic layer; the spin field effect transistor 100 uses the two-dimensional ferromagnetic semiconductor material as a two-dimensional electron gas channel of the spin field effect transistor 100, and utilizes the advantage of 'non-damage' regulation and control of the two-dimensional ferromagnetic semiconductor material by the applied gate voltage, wherein the two-dimensional ferromagnetic semiconductor material as a spin electron conduction channel has atomic-level material thickness and has more sensitive response to an external electric field perpendicular to an atomic layer plane; therefore, the two-dimensional ferromagnetic semiconductor material has a higher magnetoresistance ratio and switching ratio than the three-dimensional magnetic material, thereby making the performance of the magnetic logic device thereof more excellent.
It should be noted that, the foregoing embodiments all belong to the same inventive concept, and the descriptions of the embodiments have emphasis, and where the descriptions of the individual embodiments are not exhaustive, reference may be made to the descriptions of the other embodiments.
The foregoing examples merely illustrate embodiments of the invention and are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A spin field effect transistor, comprising:
a substrate layer;
a semiconductor layer disposed on the substrate layer;
a source electrode and a drain electrode respectively disposed at both ends of the semiconductor layer;
a dielectric layer disposed between and overlying the source and drain electrodes; and
a gate electrode disposed on the dielectric layer;
wherein the semiconductor layer is a two-dimensional ferromagnetic semiconductor material of a monoatomic layer.
2. The spin field effect transistor of claim 1 wherein the semiconductor layer is of CrCl 3 、CrBr 3 、CrI 3 、Cr 2 Ge 2 Te 6 、Fe 3 GeTe 2 、VI 3 、VSe 2 、MnSe 2 、MnSi、FePS 3 And VTe 2 Any one of the following.
3. The spin field effect transistor of claim 2 wherein the semiconductor layer has a length in the range of 10nm to 200 nm; the thickness of the semiconductor layer ranges between 0.5nm and 10 nm.
4. The spin field effect transistor according to claim 1, wherein the source electrode and the drain electrode are each any one of Fe, co, niFe, coFe, coFeB, laSrMnO, gaMnAs, coFeAl, YFeO and CoFeO.
5. The spin field effect transistor of claim 1, wherein the material of the dielectric layer is any one of SiOx, alOx, siC, hfOx, tiOx and h-BN.
6. The spin field effect transistor of claim 5 wherein the length of the dielectric layer ranges between 10nm and 200 nm; the thickness of the dielectric layer ranges between 0.5nm and 10 nm.
7. The spin field effect transistor of claim 1, wherein the gate electrode is at least one of Au, cu, ti, cr, ag, pt and graphene.
8. The spin field effect transistor of claim 1, wherein the substrate layer comprises a first substrate and a second substrate disposed on the first substrate, the second substrate being in contact with the semiconductor layer;
wherein the material of the first substrate is Si, and the material of the second substrate is SiO 2 。
9. A method of manufacturing a spin field effect transistor according to any one of claims 1 to 8, comprising the steps of:
preparing a semiconductor layer on the surface of the substrate layer;
preparing source electrodes and drain electrodes which are arranged at intervals on the surface of the semiconductor layer;
preparing dielectric layers on the surfaces of the source electrode and the drain electrode;
and preparing a gate electrode on the surface of the dielectric layer.
10. The method of manufacturing a spin field effect transistor according to claim 9, wherein in the step of depositing a semiconductor layer on the surface of the substrate layer, the method of manufacturing the semiconductor layer is selected from at least one of a mechanical lift-off process, a chemical vapor deposition process, a wet transfer process, and a dry transfer process.
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