CN115884602A - Dual-mode voltage-regulated MRAM (magnetic random Access memory) storage unit based on ferroelectric/ferromagnetic material coupling, and regulation method and preparation method thereof - Google Patents

Abstract

The invention relates to a dual-mode voltage regulation MRAM memory unit based on ferroelectric/ferromagnetic material coupling and a regulation method thereof, wherein a voltage is applied between a free layer and a bottom electrode in a tunnel junction by a voltage regulation unit, and a ferroelectric layer is regulated and controlled by applying the voltage, so that the ferroelectric layer can be switched between a non-breakdown state and a breakdown state; when the ferroelectric layer is in a non-breakdown state, the magnetic anisotropy energy influencing the free layer can be reversibly changed; when the ferroelectric layer is in a breakdown state, the permanent magnetic moment affecting the free layer increases, so that the magnetic anisotropy of the free layer can undergo a nonvolatile change.

Description

Dual-mode voltage-regulated MRAM (magnetic random Access memory) storage unit based on ferroelectric/ferromagnetic material coupling, and regulation method and preparation method thereof

Technical Field

The invention relates to the field of semiconductors, in particular to a dual-mode voltage regulation MRAM memory unit based on ferroelectric/ferromagnetic material coupling, a regulation method and a preparation method thereof.

Background

A magnetic random access memory (MARM) accomplishes the storage of data by changing the magnetization direction of the free magnetic layer relative to the pinned layer to create different magneto-resistive states corresponding to the parallel and anti-parallel states, respectively. MARMs have the advantages of high speed read/write, high integration, low power consumption, and nearly unlimited number of erasures, and are therefore considered as candidates for next generation memory devices.

The magnetic tunnel junction is the core of the MRAM memory cell, the magnetic moment direction of the upper layer is pinned in the fixed direction by a pinning layer, which is called as the pinned layer, the material is selected to have stronger exchange bias effect with the pinning layer, and the more suitable material is CoFeB; the magnetic moment direction of the lower layer can be freely reversed under external excitation, the lower layer is called a free layer, soft ferromagnetic materials are generally adopted, the coercivity is low, for example, coFeB materials are set to be 1 nm-1.5 nm in thickness, and the lower layer is ensured to be in perpendicular magnetic anisotropy. The pinned layer and the free layer also include a spacer layer therebetween, which is a nonmagnetic thin film, typically MgO. When the pinned layer and the free layer have magnetic moment directions parallel, the magnetic tunnel junction exhibits a lowest resistance state; on the contrary, when the magnetic moments of the pinned layer and the free layer are in opposite directions, the highest resistance state is represented; the resistance of the magnetic tunnel junction also appears to be between the lowest resistance and the highest resistance when the magnetic moments of the pinned and free layers are in other states. With the continuous development of moore's law, the feature size of integrated circuits is continuously shrinking, and for MRAM memory, the size of core memory cells has been shrinking from 100nm to 30nm, and even to below 10nm in the scientific research community. However, at such a small size, how to maintain the data storage stability of the memory cell has been a hot research focus in the industry and academia.

At present, some solutions have been proposed internationally, such as making the memory cell cylindrical and maintaining its magnetic properties by in-plane magnetic anisotropy; or more interfaces of the insulating layer/magnetic layer are added in the memory cell structure, and the magnetism of the memory cell structure is maintained through interface magnetic anisotropy; or the method of regulating and controlling the magnetic anisotropy of the CoFeB/MgO interface in the memory cell and dynamically regulating and controlling the magnetism of the memory cell plays a certain role by applying voltage to the memory cell, but on one hand, the complexity of the integration process is increased, and other electrical characteristics of the memory cell are influenced, on the other hand, the traditional voltage regulation and control effect is volatile, and in order to maintain the magnetism of the memory cell, voltage needs to be continuously provided, which is not beneficial to the continuous micro-shrinkage of the MRAM.

Disclosure of Invention

In order to solve the technical problems, the invention provides a dual-mode nonvolatile voltage regulation MRAM memory cell based on ferroelectric/ferromagnetic material coupling, a regulation method and a preparation method thereof.

The invention adopts the following technical scheme: a dual mode voltage regulated MRAM memory cell based on ferroelectric/ferromagnetic material coupling, comprising in order from bottom to top: the device comprises a substrate, a bottom electrode layer, a ferroelectric layer, a magnetic tunnel junction and a pinning layer; the device also comprises a voltage regulation and control unit; wherein, the pinning layer is an antiferromagnetic structure layer and is magnetic anisotropy in a vertical plane;

the magnetic tunnel junction includes from bottom to top in proper order: a free layer, an isolation layer, and a pinned layer, the pinned layer pinning a magnetic moment of the pinned layer in one fixed direction;

the ferroelectric layer applies an electric field to influence the magnetic moment direction of the free layer through voltage regulation and control voltage;

the voltage regulating unit applies voltage between the free layer and the bottom electrode layer in the tunnel junction, and regulates the ferroelectric layer by applying the voltage, so that the ferroelectric layer can be switched between a non-breakdown state and a breakdown state; when the ferroelectric layer is in a non-breakdown state, the magnetic anisotropy energy influencing the free layer can be reversibly changed; when the ferroelectric layer is in a breakdown state, the permanent magnetic moment affecting the free layer is increased, so that the magnetic anisotropy of the free layer can be subjected to nonvolatile change.

A regulation and control method of the MARM memory unit is characterized in that a voltage is applied between a free layer and a bottom electrode layer in a tunnel junction by a voltage regulation and control unit, and when a non-breakdown voltage is applied, the magnetic anisotropy energy of the free layer influenced by a ferroelectric layer is reversibly changed; when a breakdown voltage is applied, the permanent magnetic moment affecting the free layer increases, enabling a non-volatile change in the magnetic anisotropy of the free layer.

A method for manufacturing a memory cell as described above, characterized by: the method comprises the following steps:

sequentially growing a bottom electrode layer and a ferroelectric layer on a substrate;

sequentially growing a magnetic tunnel junction and a top electrode layer on the ferroelectric layer; the magnetic tunnel junction comprises a free layer, an isolation layer and a pinned layer from bottom to top in sequence, and the pinned layer pins the magnetic moment of the pinned layer in a fixed direction;

sequentially etching the magnetic tunnel junctions from top to bottom to form a cylinder until the upper surface of the free layer is exposed, and applying a voltage V to the free layer and the bottom electrode layer respectively ₁ Applying a voltage V to the free layer and the top electrode layer ₂ 。

The ferroelectric layer is regulated and controlled by applying voltage, so that the ferroelectric layer can be switched between a non-breakdown state and a breakdown state; when the ferroelectric layer is in a non-breakdown state, the magnetic anisotropy energy influencing the free layer can be reversibly changed; when the ferroelectric layer is in a breakdown state, the permanent magnetic moment affecting the free layer increases, so that the magnetic anisotropy of the free layer can undergo a nonvolatile change.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.

In FIG. 1, (a) - (c) are respectively substrate preparation, tiN magnetron sputtering and HfZrO deposition by ALD;

in FIG. 2, (d) - (f) are magnetron sputtering growth of MTJ, annealing, PVD deposition of TiN hard mask respectively;

in FIG. 3, (g) - (i) are DUV exposure, tiN hard mask etching and MTJ first etching, respectively;

FIGS. 4 (j) - (l) are PECVD growth SiN, second DUV exposure and etching, and third exposure and etching, respectively;

in FIG. 5, (m) - (o) are PECVD growth TEOS, CMP, DUV exposure to form holes, respectively;

in fig. 6, (p) - (q) are respectively a step of etching the PIE to form an electrode hole, a step of filling metal, and a step of patterning to form a dual-mode modulation mram device.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

In this embodiment, a fabrication method for fabricating a high performance MRAM memory cell based on ferroelectric/ferromagnetic material coupling is provided. With reference to fig. 1 to 6, the process for manufacturing the MRAM memory cell specifically includes:

first, referring to fig. 1 (a), a standard cleaning process using Buffered Oxide etching solution (BOE) is used to remove a native Oxide layer on the surface of a silicon wafer.

In fig. 1 (b), a bottom electrode layer 102 is first grown on a substrate 101 by a magnetron sputtering process. In this embodiment, tiN is used for the bottom electrode layer 102, and the thickness is 10nm.

FIG. 1 (c) shows the reaction solution of deionized water and Hf (NCH) ₃ C ₂ H ₅ ) ₄ And Zr (NCH) ₃ CH ₅ ) ₄ As a precursor, a layer of metal oxide Hf with ferroelectric polarization characteristics is grown on the bottom electrode layer 102 by Atomic Layer Deposition (ALD) _0.5 Zr _0.5 O ₂ (HfZrO) which has standard ferroelectric properties, is a ferroelectric layer 103 with a thickness of 10nm, and HfZrO is used as the metal oxide 103 having ferroelectric polarization properties in this embodiment.

Referring to fig. 2 (d), a transition layer 104 is deposited on the ferroelectric layer 103 by magnetron sputtering, in this embodiment, a metal tungsten W with a thickness of 0-0.6nm is used, and mainly functions as a transition layer between the ferroelectric layer 103 and the free layer in the magnetic tunnel junction, so that the free layer exhibits perpendicular magnetic anisotropy.

Next, at the transition layer 104, a core-magnetic tunnel junction of the MRAM memory cell is deposited by magnetron sputtering, followed by deposition of a free layer 105-1, in one embodiment Co is used for the free layer 105-1 ₂₀ Fe ₆₀ B ₂₀ (CoFeB) with the thickness of 1nm, and can be freely turned over under external excitation; then depositing an isolation layer 105-2, in one embodiment MgO is used for the isolation layer 105-2, with a thickness in the range of 2nm; finally, the pinned layer 105-3 is deposited, in one embodiment Co is used for the pinned layer 105-3 ₂₀ Fe ₆₀ B ₂₀ (CoFeB) with a thickness of 1nm, the direction of magnetic moment is pinned in a fixed direction by an artificial antiferromagnetic structure. Then, the pinning layer 106 was grown by magnetron sputtering over the pinned layer 105-3, and in this example, an artificial antiferromagnetic structure layer was used as the pinning layer 106, and the artificial antiferromagnetic structure layer 106 had a structure of a (Co/Pt) n layer 106-1, a Ru layer 106-2, and a (Co/Pt) m layer 106-3 in this order from bottom to top, where the Co layer was 0.3nm, the Pt layer was 0.8nm, and the Ru layer 106-2 was 0.5nm in thickness, where n =3, m =4.

As shown in FIG. 2 (e), the prepared film sample was placed in N at 700Torr ₂ Fast annealing of film samples at 400 ℃ for 30s in the environmentFire induces HfZrO in the ferroelectric layer 103 to form a ferroelectric phase and the free layer 105-1 to form perpendicular magnetic anisotropy.

Wherein (Co/Pt) n/Ru/(Co/Pt) m 106 constitutes an artificial antiferromagnetic structure having perpendicular magnetic anisotropy, and functions to pin the magnetic moment of CoFeB as the pinned layer 105-3 in a fixed direction by an interface coupling action; a tunnel junction formed by CoFeB/MgO/CoFeB and composed of the free layer 105-1, the isolating layer 105-2 and the pinned layer 105-3 is the core of the memory cell, and when the magnetic moment directions of the two CoFeB layers are parallel, the tunnel junction is in a low resistance state; otherwise, it is expressed as a high resistance state.

Referring to fig. 2 (f), the annealed film sample was subjected to PVD growth of a top electrode layer 107 with a thickness of 100nm, in this example the top electrode layer 107 is a TiN layer.

FIG. 3 (g) shows the exposure of a top electrode layer 107 to form a cylinder 108 with a diameter of 180nm in conjunction with a DUV photolithography process. Etching by ICP etching system, etching top electrode layer 107, transferring photoresist pattern 108 to top electrode layer 107, typically Cl ₂ Gas is the main etching gas, see fig. 3 (h). Thereafter, using Ar gas to etch (Co/Pt) m layer 106-3, ru layer 106-2, (Co/Pt) n layer 106-1, pinned layer 105-3, spacer layer 105-2, using the top electrode layer 107 as a hard mask, the etching stops at the surface of the free layer 105-1 or transition layer 104, in this case the free layer 105-1, by observing the OES signal in real time, as shown in FIG. 3 (i).

FIG. 4 (j) shows a thin film sample with a SiN layer 109 grown on the surface by PECVD process to a thickness of 30nm, the SiN layer 109 covering the etched exposed surface of the free layer 115-1, the etched (Co/Pt) m layer 106-3, the Ru layer 106-2, the (Co/Pt) n layer 106-1, the pinned layer 105-3, the spacer layer 105-2, and the etched upper surface of the (Co/Pt) m layer 106-3. The wafer is cleaned using anji.

And (3) combining a DUV photoetching process, and using a cylinder with the exposure diameter of 300nm as a mask to carry out alignment on the etched structure. Using an ICP etching system, using Ar as a main etching gas, the SiN109 is etched, and both sides of the free layer 105-1, the transition layer 104, and the ferroelectric layer 103 are etched, so that a mesa structure as shown in fig. 4 (k) is formed. Again, DUV lithography and etching processes are used, a cylinder with an exposure diameter of 500nm is used as a mask to overlay the etched structure, and both sides of the bottom electrode layer 102 are etched to form a mesa structure as shown in fig. 4 (l).

Then, a PECVD process and Tetraethoxysilane (TEOS) are used as a source to deposit a TEOS layer 110 for the film sample, the TEOS layer 110 wraps the film sample, the thickness of the TEOS layer 110 is 300nm, better step coverage is provided for the film sample, and metal electrode wires at the later stage are insulated and isolated from each other, so that an insulating protective layer is provided, and the reference figure 5 (m) shows.

Next, as shown in fig. 5 (n), the TEOS layer 110 and the SiN layer 109 on the top of the device are polished chemically and mechanically by a CMP process, so that the TEOS layer 110 and the SiN layer 109 are flush with the upper surface of the (Co/Pt) m layer 106-3.

A photoresist layer 111 is coated on the upper surface of the device and three via holes 112 are formed through the photoresist layer 111 by a DUV exposure process, see fig. 5 (o). By RIE etching, the TEOS layer 110 is etched with the photoresist mask formed in fig. 5 (o), three through holes are formed therein, and the through holes respectively reach the upper surface of the bottom electrode layer 102 and the upper surfaces of the two sides of the free layer 105, and then the photoresist layer 111 is etched to expose the top electrode 107, as shown in fig. 6 (p).

Then, the three through holes are filled with metal through a deposition process, so as to form three electrodes 113-1, 113-2, 113-4 respectively connecting the bottom electrode layer 102 and the free layer 105, and form an electrode 113-3 on the upper surface of the (Co/Pt) m layer 116-3, and finally form a dual-mode voltage-controlled MRAM memory cell based on ferroelectric/ferromagnetic material coupling as shown in fig. 6 (q).

As shown in fig. 6 (q). A voltage V is applied between the electrodes 113-1, 113-2 ₁ I.e. applying a voltage V between the bottom electrode layer 102 and the free layer 105-1 ₁ A voltage V is applied between the electrodes 113-3, 113-4 ₂ I.e., applying a voltage V between the (Co/Pt) m layer 106-3 and the free layer 105-1 ₂ 。

Voltage V ₁ Voltage manipulation of ferroelectric material properties is used to change the properties of MRAM memory cells. According to different set voltage amplitudes, the common mode can be realizedA dual-mode regulation of a voltage regulation mode and a permanent voltage regulation mode; while the voltage V ₂ For testing the properties of the MTJ.

The common voltage regulation mode comprises the following steps: the voltage is applied to the HfZrO layer of the ferroelectric layer 103 through the TiN layer of the bottom electrode 102 and the CoFeB layer of the free layer 105-1, and the voltage range is generally controlled to be between-3V and 3V, which is smaller than the breakdown voltage of the HfZrO layer of the ferroelectric layer 103, and under the voltage, the ferroelectric polarization of the HfZrO layer of the ferroelectric layer 103 can be turned over in a nonvolatile manner, i.e., it is ferroelectric. The ferroelectric polarization and the magnetization of the free layer interact through a magnetoelectric coupling effect, so that the magnetic anisotropy energy of the free layer can be reversibly changed. The principle is as follows: when the direction of electric polarization strength points downwards, electrons are accumulated at the interface of the HfZrO layer of the ferroelectric layer 103 and the CoFeB layer of the free layer 105-1, so that the interface magnetic anisotropy energy coefficient of the CoFeB layer of the free layer 105-1 becomes smaller, and the magnetic anisotropy energy is reduced; on the contrary, the magnetic anisotropy energy is increased, and the regulation mode has no influence on other physical characteristics of the CoFeB layer of the free layer 105-1.

Under this effect, the memory cell as a whole behaves as follows: when a positive voltage is applied, the coercivity of the memory cell becomes small, which means that the dynamic switching current becomes small, and the data storage stability is reduced; on the contrary, the dynamic flip current becomes larger, and the data storage stability is increased. Therefore, the method is a regulation and control mode with mutually restricted internal parameters, and different voltages can be configured according to different application requirements.

Breakdown voltage mode: in this breakdown mode, regardless of the direction of the applied voltage, when the HfZrO layer of the ferroelectric layer 103 is broken down, the internal oxygen vacancies are reduced under the action of the electric field, the electric barrier is lowered, and the vacancy ions escape from the bound state, and at this time, the oxygen ion concentration in the free layer 105-1 and the ferroelectric layer 103 is different, and under the action of the chemical potential, the oxygen ions migrate into the free layer 105-1 and react with the boron ions (B) in the CoFeB of the free layer 105-1 to generate stable BOx, so that more CoFe is released in the "magnetic moment of the magnetic dead layer", and the saturation permanence of the CoFeB layer of the free layer 105-1 becomes larger, and the relative variation amount of the CoFeB layer of the free layer 105-1 becomes 60%. Under this effect, an increase in the saturation magnetic moment of the CoFeB layer of the free layer 105-1 results in an increase in its magnetic anisotropy energy, an increase in spin polarizability, and an increase in tunneling magnetoresistance ratio. This will improve the data storage stability of the memory cell, while keeping the dynamic inversion current variation small and improving the read window of the memory cell.

Compared with a common voltage regulation mechanism, the breakdown voltage mode can not affect other electrical characteristics and even improve partial electrical characteristics on the premise of improving the storage stability of the data of the memory cell, and is one of potential solutions for overcoming performance degradation caused by the size shrinkage of the MRAM memory cell in the future.

The mram memory cell of the present invention is shown in fig. 2, with a pinning layer 106 on top of the device, the pinning layer 106 being an artificial antiferromagnetic structure with perpendicular magnetic anisotropy, and in one embodiment being a (Co/Pt) n/Ru/(Co/Pt) m structure from bottom to top, which acts to pin the magnetic moment of the pinned layer 105-3 in the magnetic tunnel junction in a fixed direction by interfacial coupling, the pinning layer being typically selected to have a strong exchange biasing material structure with the pinned layer.

The middle part of the device is a core-Magnetic Tunnel Junction (MTJ) of a MARM memory unit, a magnetic tunnel junction consisting of CoFeB/MgO/CoFeB is adopted in the embodiment, and when the magnetic moment directions of two CoFeB layers are parallel, the tunnel junction is in a low resistance state; and conversely, the magnetic tunnel junction shows a high resistance state, and when the magnetic moments of the two CoFeB layers are in other states, the resistance of the magnetic tunnel junction also shows a state between the lowest resistance and the highest resistance. The thickness of CoFeB is set to 1nm to 1.5nm to ensure that it exhibits perpendicular magnetic anisotropy. The magnetic moment direction of the upper CoFeB layer is pinned in a fixed direction by an artificial antiferromagnetic structure, referred to as the pinned layer 105-3, and may also have a self-pinned structure, which may be formed of a material or structure having a higher coercivity; the magnetic moment orientation of the underlying CoFeB layer can be freely switched under external excitation, referred to as free layer 105-3. The spacer layer 105-2 may comprise a non-magnetic, electrically conductive material or a non-magnetic, insulating material. When the spacer layer 105-2 is formed of a non-magnetically conductive material, its thickness is preferably no greater than the spin-electron mean free path of the material. When the spacer layer 105-2 is formed of a non-magnetically insulating material, it is also commonly referred to as a barrier layer through which electrons can flow between the pinned layer 105-3 and the free layer 105-1 by tunneling.

The lower portion of the device is a ferroelectric layer 103. The ferroelectric layer 103 may be formed of an insulating or semiconducting ferroelectric material. In the embodiment, the ferroelectric layer is formed by HfZrO, the HfZrO has standard ferroelectric characteristics, and the direction of electric dipole moment is changed due to an external electric field, so that the vertical magnetic moment direction of CoFeB in the magnetic tunnel junction is influenced. Between the ferroelectric layer 103 and the free layer 105-1, there is a transition layer 104, W, with a thickness of up to 1nm, which mainly functions as a transition layer between the ferroelectric layer 103 and the free layer 105-1, thereby allowing the free layer 105-1 to exhibit perpendicular magnetic anisotropy.

Below the ferroelectric layer 103 is the bottom electrode 102 of the memory cell, in this embodiment TiN is used as the bottom electrode of the MARM. An electrode is led out between the CoFeB and the TiN and used for voltage regulation and control of the characteristics of the ferroelectric material, so that the characteristics of the MRAM memory unit are changed. According to different set voltage amplitudes, dual-mode regulation of a common voltage regulation mode and permanent voltage regulation can be realized.

Since the ferroelectric material has a polarization maintaining property, different voltages are applied to the bottom electrodes 102 and 36 on the ferroelectric layer 103 to adjust the polarization of the ferroelectric layer 103.

The common voltage regulation mode comprises the following steps: the voltage is applied to the HfZrO layer of the ferroelectric layer 103 through the TiN layer of the bottom electrode 102 and the CoFeB layer of the free layer 105 — and the range of the voltage is generally controlled between-3V and 3V, which is smaller than the breakdown voltage of HfZrO, and under the voltage, the ferroelectric polarization of HfZrO may undergo nonvolatile reversal, i.e., exhibit ferroelectricity. The ferroelectric polarization and the magnetization of the free layer interact through a magnetoelectric coupling effect, so that the magnetic anisotropy energy of the free layer can be reversibly changed. The principle is as follows: when the direction of electric polarization strength points downwards, electrons are accumulated on the interface of the ferroelectric layer 103 and the free layer 105-1, so that the magnetic anisotropy energy coefficient of the interface of the free layer 105-1 becomes smaller, and the magnetic anisotropy energy is reduced; conversely, the magnetic anisotropy energy is increased in a manner that does not affect other physical characteristics of the free layer 105-1.

Under this effect, the memory cell as a whole exhibits behavior that when a positive voltage is applied, the coercivity of the memory cell becomes small, meaning that the dynamic switching current becomes small, and the data storage stability is lowered; on the contrary, when a negative voltage is applied, the dynamic reverse current increases, and the data storage stability increases. Therefore, the voltage regulation method is a regulation and control mode with mutually restricted internal parameters, and different voltages can be configured according to different application requirements.

Breakdown voltage mode: in the breakdown mode, no matter how the direction of the applied voltage is, when the HfZrO layer is broken down, the electric potential barrier of oxygen vacancies inside the HfZrO layer is reduced under the action of an electric field, and vacancy ions escape from a bound state, at the moment, the oxygen ion concentration in the free layer 105-1CoFeB and the HfZrO layer is different, and under the action of chemical potential, the oxygen ions migrate into the CoFeB and react with boron ions (B) therein to generate stable BOx, so that more CoFe is released in the 'magnetic dead layer', and the saturation magnetic moment of the free layer is permanently enlarged, and the relative variation can reach 60%. Under this effect, the free layer saturation magnetic moment increases, which results in an increase in its magnetic anisotropy energy, an increase in spin polarizability, and an increase in tunneling magnetoresistance ratio. This will improve the data storage stability of the memory cell, while keeping the dynamic inversion current variation small and improving the read window of the memory cell.

Compared with a common voltage regulation mechanism, in a breakdown voltage mode, the magnetic anisotropy energy, the spin polarization rate and the tunneling magneto-resistance ratio of the free layer are increased due to the increase of the saturation magnetic moment of the free layer, so that other electrical characteristics are not influenced and even part of the electrical characteristics are improved on the premise of improving the storage stability of the data of the storage unit, and the free layer is one of potential solutions for overcoming performance degradation caused by the size shrinkage of the MRAM storage unit in the future.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims (8)

1. A dual mode voltage regulated MRAM memory cell based on ferroelectric/ferromagnetic material coupling, characterized in that:

from supreme including in proper order down: the device comprises a substrate, a bottom electrode layer, a ferroelectric layer, a magnetic tunnel junction and a pinning layer; the device also comprises a voltage regulation and control unit;

wherein, the first and the second end of the pipe are connected with each other,

the pinning layer is an antiferromagnetic structure layer and is magnetic anisotropy in a vertical plane;

the magnetic tunnel junction includes from bottom to top in proper order: a free layer, an isolation layer, and a pinned layer, the pinned layer pinning a magnetic moment of the pinned layer in one fixed direction;

the ferroelectric layer applies an electric field to influence the magnetic moment direction of the free layer through voltage regulation and control voltage;

the voltage regulating unit applies voltage between the free layer and the bottom electrode layer in the tunnel junction, and regulates the ferroelectric layer by applying the voltage, so that the ferroelectric layer can be switched between a non-breakdown state and a breakdown state; when the ferroelectric layer is in a non-breakdown state, the magnetic anisotropy energy influencing the free layer can be reversibly changed; when the ferroelectric layer is in a breakdown state, the permanent magnetic moment affecting the free layer is increased, so that the magnetic anisotropy of the free layer can be subjected to nonvolatile change.

2. The dual-mode voltage-regulated MRAM memory cell of claim 1, wherein: a transition layer is arranged between the ferroelectric layer and the free layer, and the thickness of the transition layer is 0.5nm.

3. The memory cell of claim 1, wherein: the perpendicular magnetic anisotropy antiferromagnetic structure layer is (Co/Pt) n/Ru/(Co/Pt) m.

4. The memory cell of claim 1, wherein: the magnetic tunnel junction is CoFeB/MgO/CoFeB.

5. The memory cell of claim 1, wherein: the ferroelectric layer is HfZrO.

6. The memory cell of claim 1, wherein: the bottom electrode layer is made of TiN.

7. A method of regulating a memory cell according to claims 1-6, characterized in that: the voltage regulating unit applies a voltage between the free layer and the bottom electrode layer in the tunnel junction, and when a non-breakdown voltage is applied, the ferroelectric layer influences the magnetic anisotropy energy of the free layer to change reversibly; when a breakdown voltage is applied, the permanent magnetic moment affecting the free layer increases, causing a non-volatile change in the magnetic anisotropy energy of the free layer.

8. A method of manufacturing a memory cell according to claims 1-6, characterized in that: the method comprises the following steps:

sequentially growing a bottom electrode layer and a ferroelectric layer on a substrate;

sequentially growing a magnetic tunnel junction and a top electrode layer on the ferroelectric layer; the magnetic tunnel junction comprises a free layer, an isolation layer and a pinned layer from bottom to top in sequence, and the pinned layer pins the magnetic moment of the pinned layer in a fixed direction;

sequentially etching the magnetic tunnel junction from top to bottom to form a cylinder until the upper surface of the free layer is exposed, and applying a voltage V to the free layer and the bottom electrode layer respectively ₁ Applying a voltage V to the free layer and the top electrode layer ₂ 。

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