CN116013939A - Display panel, display device and manufacturing method of display panel - Google Patents

Abstract

The present disclosure relates to the field of display panels, and more particularly, to a display panel, a display device, and a method for manufacturing the display panel. The display panel comprises a substrate, a display area and a peripheral area, wherein the display area and the peripheral area are arranged on one side of the substrate, and the peripheral area is arranged around the display area. The display area is internally provided with a grid line, a data line, a thin film transistor and a pixel electrode, wherein the thin film transistor comprises a substrate, a grid electrode arranged on one side of the substrate, a first grid insulating layer, a first active layer, a source electrode and a drain electrode; the periphery district is equipped with crossing first signal of different layers and walks the line with the second signal and walks the line, and first signal walks the line and set up with the grid line homolayer, and the second signal walks one side towards the basement and is equipped with second active layer and second grid insulating layer in proper order, and second active layer and second signal walk the line one-to-one setting. A layer of second active layer is added between the second signal wiring and the first signal wiring, and the downward or upward diffusion of copper ions can be effectively blocked, so that poor short circuit between the first signal wiring and the second signal wiring caused by copper ion diffusion is avoided.

Description

Display panel, display device and manufacturing method of display panel

Technical Field

The present disclosure relates to the field of display panels, and more particularly, to a display panel, a display device, and a method for manufacturing the display panel.

Background

In the display panel manufacturing process, various signal traces are increasingly selected as the display area and the peripheral area due to the high conductivity of copper metal. The peripheral area and the display area of the display panel are provided with a large number of signal wiring different layers in an overlapping mode, copper ions are easy to migrate and diffuse under high-temperature and high-humidity environments and strong cross-pressure excitation, and particularly at the overlapping climbing positions of the signal wiring, the copper ions gradually permeate and penetrate through insulating layers among the signal wiring, so that the different-layer signal wiring is conducted to cause short circuit. Particularly, in the clock signal transmission area of the peripheral area, there is a denser signal wiring arrangement, and a larger cross voltage exists between the different-layer signal wirings, so that the signal wiring conduction short circuit caused by copper diffusion is more likely to occur, and the display screen is abnormal, namely the clock signal transmission area is bad (CLK AD, clock Abnormal Display) due to CT lighting (bad detection of the Cell Test on the rear panel of the box).

Disclosure of Invention

An objective of the embodiments of the present application is to provide a display panel, a display device and a method for manufacturing the display panel, which are used for solving the problem of poor signals caused by copper ion diffusion in an overlapping arrangement area of signal traces. The specific technical scheme is as follows:

a first aspect of an embodiment of the present application provides a display panel, including: the display device comprises a substrate, a display area and a peripheral area, wherein the display area and the peripheral area are arranged on one side of the substrate, the peripheral area surrounds the display area, a grid line, a data line, a thin film transistor and a pixel electrode are arranged in the display area, and the thin film transistor comprises the substrate, a grid electrode, a first grid electrode insulating layer, a first active layer, a source electrode and a drain electrode, wherein the grid electrode, the first grid electrode insulating layer, the first active layer and the source electrode and the drain electrode are arranged on one side of the substrate; the substrate extends to the peripheral area, the peripheral area is provided with a first signal wiring and a second signal wiring which are intersected by different layers, the first signal wiring and the grid lines are arranged on the same layer, one side of the second signal wiring, which faces the substrate, is sequentially provided with a second active layer and a second grid insulating layer, and the second active layer extends along the extending direction of the second signal wiring and is arranged in one-to-one correspondence with the second signal wiring.

In addition, the display panel provided according to the embodiment of the application may further have the following technical features:

in some embodiments of the present application, an orthographic projection of the second signal trace on the substrate is located within an orthographic projection of the second active layer on the substrate along an extending direction perpendicular to the second signal trace.

In some embodiments of the present application, along the extending direction perpendicular to the second signal trace, the first distance between at least one side edge of the second active layer corresponding to the second signal trace and the same side edge of the second signal trace is 1 micrometer to 1.5 micrometers.

In some embodiments of the present application, the second distance between adjacent second signal traces is 5 microns or more.

In some embodiments of the present application, a different-layer overlapping region and a different-layer non-overlapping region are provided between the first signal trace and the second signal trace, and a width of the first signal trace in the different-layer overlapping region is smaller than a width of the first signal trace in the different-layer non-overlapping region.

In some embodiments of the present application, the second gate insulating layer is disposed in the same layer as the first gate insulating layer, and the second active layer is disposed in the same layer as the first active layer; the second active layer has a thickness of 700 angstroms to 1000 angstroms.

In some embodiments of the present application, the second signal trace is disposed at the same layer as the data line.

In some embodiments of the present application, the second signal trace is electrically connected to the first signal trace through at least one via, the first signal trace is electrically connected to the driving chip, and the second signal trace is electrically connected to the GOA driving circuit.

A second aspect of embodiments of the present application provides a display device including the display panel described above.

A third aspect of the embodiments of the present application provides a method for manufacturing a display panel, which is used for manufacturing the display panel, where the display panel includes a display area and a peripheral area disposed around the display area, and the method for manufacturing the display panel at least includes the following steps:

providing the substrate, wherein the substrate covers the display area and the peripheral area; manufacturing the grid electrode, the first grid electrode insulating layer, the first active layer, the source electrode, the drain electrode, the grid line connected with the grid electrode of the thin film transistor in the same row, the data line connected with the source electrode and the drain electrode of the thin film transistor in the same column and the pixel electrode on one side of the substrate positioned in the display area; and manufacturing the first signal wiring and the second signal wiring which are intersected in different layers on one side of the substrate in the peripheral region, wherein the first signal wiring and the grid line are arranged on the same layer, the second signal wiring is sequentially provided with the second active layer and the second grid insulating layer on one side of the substrate facing the substrate, and the second active layer and the second signal wiring are arranged in one-to-one correspondence.

The embodiment of the invention has the beneficial effects that: the display panel that this embodiment provided, display panel include the display region and around the peripheral district that the display region set up, and the peripheral district is equipped with the crossing first signal wiring of different layers and second signal wiring, and first signal wiring and gate line homolayer setting, the second signal wiring orientation one side of basement is equipped with second active layer and second grid insulating layer in proper order, and second active layer and second signal wiring one-to-one set up, and the below of every second signal wiring all is equipped with a second active layer promptly for when second signal wiring copper ion down diffusion or first signal wiring copper ion up diffusion, one deck second active layer more, the second active layer is as the barrier layer, can effectively block copper ion down or ascending diffusion to avoid first signal wiring and second signal wiring short circuit bad because of copper ion diffusion leads to.

Of course, not all of the above-described advantages need be achieved simultaneously in practicing any one of the products or methods of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other embodiments may also be obtained according to these drawings to those skilled in the art.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the specific structure of the portion I in FIG. 1;

FIG. 3a is a cross-sectional view taken along the direction B-B in FIG. 2;

FIG. 3b is a schematic diagram of the copper ion diffusion principle in FIG. 3 a;

FIG. 4base:Sub>A isbase:Sub>A cross-sectional view taken along the direction A-A in FIG. 2;

FIG. 4b is a schematic diagram of the copper ion diffusion principle in FIG. 4 a;

FIG. 5 is a top view of the wiring of section I of FIG. 1;

fig. 6 is a cross-sectional view taken along the direction C-C in fig. 2.

The reference numerals are: a display area 10; a substrate 110; a peripheral region 20; a first signal trace 21; a second signal trace 22; a via 221; a first via 221a; a second via 221b; a second gate insulating layer 23; a first sub-layer 231; a second sub-layer 232; a second active layer 24; a pixel electrode 25; a first distance L1; a second distance L2; base angle α; a different layer overlapping area A1; the non-overlapping area A2 of the different layers.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. Based on the embodiments herein, a person of ordinary skill in the art would be able to obtain all other embodiments based on the disclosure herein, which are within the scope of the disclosure herein.

A first aspect of the present application provides a display panel, as shown in fig. 1, fig. 2, fig. 3a, fig. 4a, including: the display device comprises a substrate 110, a display area 10 and a peripheral area 20, wherein the display area 10 and the peripheral area 20 are arranged on one side of the substrate 110, the peripheral area 20 surrounds the display area 10, a grid line, a data line, a thin film transistor and a pixel electrode 25 are arranged in the display area 10, and the thin film transistor comprises the substrate 110, a grid electrode, a first grid insulating layer, a first active layer, a source electrode and a drain electrode, wherein the grid electrode and the first grid insulating layer are arranged on one side of the substrate 110; as shown in fig. 2, 3a and 4a, the substrate 110 extends to the peripheral area 20, the peripheral area 20 is provided with a first signal wire 21 and a second signal wire 22 intersecting in different layers, the first signal wire 21 and the gate wire are arranged in the same layer, one side of the second signal wire 22 facing the substrate 110 is sequentially provided with a second active layer 24 and a second gate insulating layer 23, and the second active layer 24 extends along the extending direction of the second signal wire 22 and is arranged in one-to-one correspondence with the second signal wire 22.

In this embodiment, the gate line is used to electrically connect to the gates of the same row of thin film transistors, the data line is used to electrically connect to the sources and drains of the same column of thin film transistors, and in this application, the row or column does not actually indicate a certain direction, that is, the gate line may also be used to electrically connect to the gates of the same column of thin film transistors, and the data line may also be used to electrically connect to the sources and drains of the same row of thin film transistors. The second signal wires 22 are sequentially provided with a second active layer 24 and a second gate insulating layer 23 on a side facing the substrate 110, and the second active layers 24 are disposed in one-to-one correspondence with the second signal wires 22, that is, a second active layer 24 is disposed below each second signal wire 22, and an extending direction of the second active layer 24 is consistent with an extending direction of the second signal wire 22. That is, there is one more second active layer 24 between the first signal trace 21 and the second signal trace 22, as shown in fig. 3b and fig. 4b, when copper ions of the second signal trace 22 diffuse downward or copper ions of the first signal trace 21 diffuse upward, there is one more second active layer 24, and the second active layer 24 serves as a blocking layer, so that copper ions diffuse downward or upward can be effectively blocked, and bad short circuit between the first signal trace 21 and the second signal trace 22 caused by copper ion diffusion is avoided. The second gate insulating layer 23 may be disposed entirely to cover the display region 10 and the peripheral region 20.

In order to improve the short circuit between the first signal trace 21 and the second signal trace 22 caused by copper ion diffusion in the prior art, generally, the thickness of the insulating layer SiNx/SiO between the first signal trace 21 and the second signal trace 22 is increased or the compactness of the insulating film is improved, but two problems are brought about: 1. greatly reduces the CVD (Chemical Vapor Deposition ) and dry etching productivity; 2. the thickness of the whole insulating layer is increased, which can lead to on-state current I _on Greatly reduces and weakens the advantage of large on-state current of the oxide process.

It should be noted that, as shown in fig. 5, the extending directions of the first signal trace 21 and the second signal trace 22 are generally perpendicular to each other, so as to reduce the overlapping position and overlapping area of the first signal trace 21 and the second signal trace 22 as much as possible, reduce the probability of short-circuiting between the first signal trace 21 and the second signal trace 22 caused by copper ion diffusion, and standardize the arrangement mode of the first signal trace 21 and the second signal trace 22.

In some embodiments, as shown in fig. 5, the orthographic projection of the second signal trace 22 on the substrate 110 is located within the orthographic projection of the second active layer 24 on the substrate 110 along the extending direction perpendicular to the second signal trace 22.

In this embodiment, the orthographic projection of the second signal trace 22 on the substrate 110 is located in the orthographic projection of the second active layer 24 on the substrate 110, and there may be a side overlapping or two sides not overlapping between the orthographic projections of the second signal trace 22 and the second active layer 24, that is, along the extending direction perpendicular to the second signal trace 22, the width of the second active layer 24 is greater than the width of the second signal trace 22, and the second active layer 24 can play a role in blocking on the upward or downward diffusion path of copper ions, so as to effectively block the upward or downward diffusion of copper ions.

Further, as shown in fig. 5, along the extending direction perpendicular to the second signal trace 22, the first distance L1 between at least one side edge of the second active layer 24 corresponding to the second signal trace 22 and the same side edge of the second signal trace 22 is 1 micrometer-1.5 micrometers, for example, the distance between the first side edge and the second side edge may be 1 micrometer, 1.2 micrometers, 1.3 micrometers, 1.4 micrometers, 1.5 micrometers, etc.

In the present embodiment, the at least one side edge beyond the same side edge of the second signal trace 22 includes: the case where one side exceeds the same side as the second signal trace 22, and the case where both sides exceed the same side as the second signal trace 22 are shown in fig. 5, which is a schematic diagram of both sides exceeding the same side as the second signal trace 22. The probability of copper ion diffusion is greater at a position closer to the side of the second signal wiring 22 due to the influence of copper ion diffusion capability, and is smaller at a position farther from the side of the second signal wiring 22. Therefore, there is a preferred design range of the first distance L1 between at least one side of the second active layer 24 and the same side of the second signal trace 22, that is, the first distance L1 between at least one side of the second active layer 24 and the same side of the second signal trace 22 is 1 micrometer-1.5 micrometers, and in this range, the diffusion of copper ions upwards or downwards can be effectively prevented, and the installation area of the second active layer 24 is not greatly increased, so as to reduce the manufacturing cost of the display panel.

When the first distance L1 between at least one side edge of the second active layer 24 and the side edge of the same side of the second signal trace 22 is 1 micrometers to 1.5 micrometers, the process is easy to realize, the problem of overlapping failure caused by smaller width difference is avoided, the overlapping range of the second active layer 24 and the second signal trace 22 can be controlled by +/-1 micrometer in actual production, and the risk of conducting between the second active layers 24 caused by too narrow interval between adjacent second active layers 24 due to larger width difference is avoided.

In some embodiments, as shown in fig. 5, the second distance L2 between adjacent second signal traces 22 is greater than or equal to 5 microns, such as the distance may be 5 microns, 5.5 microns, 6 microns, 6.5 microns, 7 microns, 8 microns, etc.

In the present embodiment, the second distance L2 between the adjacent second signal traces 22 is more than 5 micrometers, so that when two sides of the second active layer 24 exceed 1 micrometer to 1.5 micrometers of the second signal traces, there is still at least 2 micrometers of space between the adjacent second active layers 24, and the resolution of the exposure machine is typically 2 micrometers to 3 micrometers within the allowable range of the resolution of the exposure machine. Therefore, the second distance L2 between the adjacent second signal traces 22 is greater than or equal to 5 μm, which does not increase the difficulty of the manufacturing process of the second active layer 24. In addition, the second distance L2 between the adjacent second signal traces 22 is greater than or equal to 5 micrometers, so that the risk of conducting the adjacent second active layer 24 or the risk of conducting the adjacent second signal traces 22 due to poor exposure patterns caused by exceeding the resolution limit of the exposure machine does not occur.

It will be appreciated that, in order to reasonably utilize the wiring space of the peripheral region 20 to increase the number of wirings of the second signal traces 22, the second distance L2 between adjacent second signal traces 22 is not too large, for example, may be smaller than 8 microns or smaller than 9 microns, and the like, so that the number of second signal traces 22 that can be arranged in the peripheral region 20 can be increased while ensuring a range allowed by the resolution of the exposure machine.

In some embodiments, as shown in fig. 2, the first signal trace 21 and the second signal trace 22 have a different-layer overlapping region A1 and a different-layer non-overlapping region A2 therebetween, and the width of the first signal trace 21 in the different-layer overlapping region A1 is smaller than the width of the first signal trace 21 in the different-layer non-overlapping region A2.

In this embodiment, the width of the first signal trace 21 in the different-layer overlapping region A1 is designed to be narrower, so that the overlapping area between the first signal trace 21 and the second signal trace 22 can be further reduced, and the risk of short-circuiting between the first signal trace 21 and the second signal trace 22 is reduced.

Of course, the width of the first signal trace 21 in the different-layer overlapping region A1 may also be consistent with the width of the different-layer non-overlapping region A2, as shown in fig. 5, where the width of the first signal trace 21 in the different-layer overlapping region A1 and the different-layer non-overlapping region A2 may be consistent.

In some embodiments, as shown in fig. 4a, the first signal trace 21 has a trapezoid shape in a cross section perpendicular to the extending direction of the first signal trace 21, and a base angle α of the trapezoid is 45 ° -60 °, for example, the base angle α may be 45 °, 50 °, 55 °, 60 °, etc.

In this embodiment, the base angle α of the trapezoid is 45 ° -60 °, i.e. the slopes (legs) of the two waists of the trapezoid are relatively gentle, so that when the second gate insulating layer 23 is continuously deposited on the first signal trace 21, the difficulty of climbing up the second gate insulating layer 23 can be reduced, and the risk of poor deposition at the two base angles α of the trapezoid is reduced. The deposition defect here means that the second gate insulating layer 23 is partially missing outside the two base angles α.

It can be appreciated that the first distance L1 between two sides of the second active layer 24 and beyond two sides of the second signal trace 22 may be 1 micron to 1.5 microns, that is, when the width difference between two sides of the second active layer 24 and the second signal trace 22 is in the range of 1 micron to 1.5 microns, copper ion diffusion of the first signal trace 21 and the second signal trace 22 at the super can be effectively prevented, so that the risk of poor shorting caused by copper ion diffusion is further reduced.

In some embodiments, the second gate insulating layer 23 is disposed in the same layer as the first gate insulating layer, the second active layer 24 is disposed in the same layer as the first active layer, and the thickness of the second active layer 24 is 700 angstroms to 1000 angstroms.

In this embodiment, the second gate insulating layer 23 and the first gate insulating layer are arranged in the same layer, so that the process steps can be reduced, and the production efficiency can be improved. The first gate insulating layer and the second gate insulating layer 23 may have a single layer structure or a double layer structure, and when the first gate insulating layer and the second gate insulating layer 23 have a double layer structure, i.e. the first gate insulating layer and the second gate insulating layer 23 each include a first sub-layer 231 and a second sub-layer 232, wherein the first sub-layer 231 may be SiN _X The layer, second sublayer 232, may be a SiO layer. The gate insulating layer is designed to be two layers because of SiN _X The second active layer 24 is not in direct contact with the silicon oxide layer, but the SiO layer alone may result in poor water barrier capability of the gate insulating layer, thus SiN _X A layer as a first sublayer 231 and a SiO layer as a second sublayer 232, such that SiN _X The layer is not in direct contact with the second active layer 24, siN can be avoided _X The combination of hydrogen in (a) and oxygen in the second active layer 24 affectsThe electrical properties of the second active layer 24 and the underlying second sub-layer 232 can improve the water blocking capability of the gate insulating layer. The second active layer 24 and the first active layer are arranged in the same layer, so that the active layer under the second signal trace 22 of the peripheral area 20, namely the second active layer 24, can be reserved by optimizing the mask design of the first active layer, and the process steps are not required to be added, so that the method is simple and feasible, and the productivity is not influenced. In addition, the second gate insulating layer 23 and the first gate insulating layer are arranged in the same layer, and the second active layer 24 and the first active layer are arranged in the same layer, which is also beneficial to reducing the thickness of the display panel.

The first active layer and the second active layer 24 are of the same material, and may be an oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide ), or may be a polysilicon semiconductor.

In some embodiments, the second signal trace 22 is disposed at the same layer as the data line.

In this embodiment, the second signal trace 22 and the data line are arranged in the same layer, so that the second signal trace 22 and the data line can share one mask plate for manufacturing, the process steps are simplified, and the production efficiency is improved. The data line can be arranged on the same layer as the source electrode and the drain electrode.

In some embodiments, as shown in fig. 2 and 6, the second signal trace 22 is electrically connected to the first signal trace 21 through at least one via 221, the first signal trace 21 is electrically connected to the driving chip, and the second signal trace 22 is electrically connected to the GOA driving circuit.

In this embodiment, the second signal trace 22 and the first signal trace 21 may be clock signal traces, which are electrically connected through at least one via 221, and the first signal trace 21 is used for transmitting a driving signal of the driving chip to the second signal trace 22 and transmitting the driving signal to the GOA driving circuit through the second signal trace 22, so as to drive the gate signal traces of the display area 10 to perform row-by-row or column-by-column scanning. As shown in fig. 2 and 6, only one of the second signal wires 22 is taken as an example, and the electrical connection structure of the second signal wire 22 and the first signal wire 21 is illustrated, and the positions of the other second signal wires 22 electrically connected to the first signal wire 21 are not illustrated in the range shown in fig. 2. The first signal trace 21 and the second signal trace 22 may be electrically connected through one via 221, or may be electrically connected through two or three vias 221, and by increasing the number of vias 221, the bridge area between the first signal trace 21 and the second signal trace 22 may be increased, thereby increasing the stability of the electrical connection between the two.

As shown in fig. 6, the first signal trace 21 and the second signal trace 22 are electrically connected by bridging the pixel electrode 25, that is, the first signal trace 21 is electrically connected to the pixel electrode 25 through the first via 221a, and the pixel electrode 25 is electrically connected to the second signal trace 22 through the second via 221b, where one via means that the number of the first via 221a and the second via 221b is one. At the electrical connection between the pixel electrode 25 and the first signal trace 21 and at the electrical connection between the pixel electrode 25 and the second signal trace 22, the width of the first signal trace 21 and the width of the second signal trace 22 may be made wider to increase the bridge area, and the width of the second active layer 24 located under the second signal trace 22 may be correspondingly made wider.

A second aspect of the embodiments of the present application provides a display device, including the display panel described above.

The display device provided by the embodiment of the application includes a display panel, the display panel includes a display area 10 and a peripheral area 20 surrounding the display area 10, the peripheral area 20 is provided with a first signal wiring 21 and a second signal wiring 22 intersecting in different layers, the first signal wiring 21 and the gate wiring are arranged on the same layer, one side of the second signal wiring 22 facing the substrate 110 is sequentially provided with a second active layer 24 and a second gate insulating layer 23, the second active layer 24 and the second signal wiring 22 are arranged in one-to-one correspondence, namely, one second active layer 24 is arranged below each second signal wiring 22, and the extending direction of the second active layer 24 is consistent with that of the second signal wiring 22. That is, there is one more second active layer 24 between the first signal trace 21 and the second signal trace 22, as shown in fig. 3b and fig. 4b, when copper ions of the second signal trace 22 diffuse downward or copper ions of the first signal trace 21 diffuse upward, there is one more second active layer 24, and the second active layer 24 serves as a blocking layer, so that copper ions diffuse downward or upward can be effectively blocked, and bad short circuit between the first signal trace 21 and the second signal trace 22 caused by copper ion diffusion is avoided.

A third aspect of the embodiments of the present application provides a method for manufacturing a display panel, which is used for manufacturing the display panel, where the method for manufacturing a display panel at least includes the following steps:

s1: a substrate 110 is provided, the substrate 110 covering the display region 10 and the peripheral region 20.

S2: on the side of the substrate 110 in the display area 10, a gate electrode, a first gate insulating layer, a first active layer, a source electrode, a drain electrode, a gate line connected to the gate electrodes of the same row of thin film transistors, a data line connected to the source electrode and the drain electrode of the same column of thin film transistors, and a pixel electrode 25 are fabricated; and on one side of the substrate 110 in the peripheral region 20, a first signal wire 21 and a second signal wire 22 intersecting with each other in different layers are simultaneously manufactured, the first signal wire 21 and the gate wire are arranged on the same layer, a second active layer 24 and a second gate insulating layer 23 are sequentially arranged on one side of the second signal wire 22 facing the substrate 110, and the second active layer 24 and the second signal wire 22 are arranged in one-to-one correspondence.

In this embodiment, the gate line and the gate electrode are formed on the same layer, and the first signal line 21 and the gate line are formed on the same layer, so that the process for manufacturing the display panel can be reduced. As shown in fig. 3a and fig. 4a, a second active layer 24 and a second gate insulating layer 23 are sequentially disposed on a side of the second signal trace 22 facing the substrate 110, that is, a second active layer 24 is disposed below each second signal trace 22, and an extending direction of the second active layer 24 is consistent with that of the second signal trace 22. As shown in fig. 3b and fig. 4b, a layer of second active layer 24 is added between the first signal trace 21 and the second signal trace 22, so that when copper ions of the second signal trace 22 diffuse downwards or copper ions of the first signal trace 21 diffuse upwards, a layer of second active layer 24 is added, and the second active layer 24 serves as a blocking layer, so that copper ions diffuse downwards or upwards, and poor short circuit between the first signal trace 21 and the second signal trace 22 caused by copper ion diffusion is avoided.

Further, the second gate insulating layer 23 and the first gate insulating layer are provided in the same layer, and the second active layer 24 and the first active layer are provided in the same layer. The second gate insulating layer 23 and the first gate insulating layer are arranged on the same layer, so that the process steps can be reduced, and the production efficiency can be improved. The second active layer 24 and the first active layer are arranged in the same layer, so that the active layer under the second signal trace 22 of the peripheral area 20, namely the second active layer 24, can be reserved by optimizing the mask design of the first active layer, and the process steps are not required to be added, so that the method is simple and feasible, and the productivity is not influenced. In addition, the second gate insulating layer 23 and the first gate insulating layer are arranged in the same layer, and the second active layer 24 and the first active layer are arranged in the same layer, which is also beneficial to reducing the thickness of the display panel.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (10)

1. A display panel, comprising: the display device comprises a substrate, a display area and a peripheral area, wherein the display area and the peripheral area are arranged on one side of the substrate, the peripheral area surrounds the display area, a grid line, a data line, a thin film transistor and a pixel electrode are arranged in the display area, and the thin film transistor comprises the substrate, a grid electrode, a first grid electrode insulating layer, a first active layer, a source electrode and a drain electrode, wherein the grid electrode, the first grid electrode insulating layer, the first active layer and the source electrode and the drain electrode are arranged on one side of the substrate;

the periphery district is equipped with crossing first signal wiring and the second signal wiring of different layers, first signal wiring with the grid line sets up with the layer, the second signal wiring towards one side of basement is equipped with second active layer and second grid insulating layer in proper order, the second active layer is followed the extending direction of second signal wiring extends, and with the setting of second signal wiring one-to-one.

2. The display panel of claim 1, wherein an orthographic projection of the second signal trace onto the substrate is located within an orthographic projection of the second active layer onto the substrate along a direction perpendicular to an extension direction of the second signal trace.

3. The display panel according to claim 2, wherein, along the extending direction perpendicular to the second signal trace, the first distance between at least one side edge of the second active layer corresponding to the second signal trace and the same side edge of the second signal trace is 1 micrometer to 1.5 micrometers.

4. The display panel of claim 1, wherein a second distance between adjacent second signal traces is 5 microns or more.

5. The display panel of claim 1, wherein the first signal trace and the second signal trace have a non-overlapping region and a non-overlapping region therebetween, the first signal trace in the non-overlapping region having a smaller width than the first signal trace in the non-overlapping region.

6. The display panel according to any one of claims 1 to 5, wherein the second gate insulating layer is provided in the same layer as the first gate insulating layer, and the second active layer is provided in the same layer as the first active layer;

the second active layer has a thickness of 700 angstroms to 1000 angstroms.

7. The display panel of any one of claims 1-5, wherein the second signal trace is disposed on a same layer as the data line.

8. The display panel of any one of claims 1-5, wherein the second signal trace is electrically connected to the first signal trace through at least one via, the first signal trace is electrically connected to the driver chip, and the second signal trace is electrically connected to a GOA driver circuit.

9. A display device, characterized in that the display device comprises the display panel of any one of claims 1-8.

10. A method for manufacturing a display panel according to any one of claims 1 to 8, wherein the display panel comprises a display area and a peripheral area arranged around the display area, the method comprising at least the steps of:

providing the substrate, wherein the substrate covers the display area and the peripheral area;

manufacturing the grid electrode, the first grid electrode insulating layer, the first active layer, the source electrode, the drain electrode, the grid line connected with the grid electrode of the thin film transistor in the same row, the data line connected with the source electrode and the drain electrode of the thin film transistor in the same column and the pixel electrode on one side of the substrate positioned in the display area;

and manufacturing the first signal wiring and the second signal wiring which are intersected in different layers on one side of the substrate in the peripheral region, wherein the first signal wiring and the grid line are arranged on the same layer, the second signal wiring is sequentially provided with the second active layer and the second grid insulating layer on one side of the substrate facing the substrate, and the second active layer and the second signal wiring are arranged in one-to-one correspondence.

Images