CN116010293A - Data request processing circuit and method, cache circuit and processor thereof - Google Patents
Data request processing circuit and method, cache circuit and processor thereof Download PDFInfo
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Abstract
The application provides a data request processing circuit, a data request processing method, a cache circuit and a processor thereof, wherein the circuit comprises: a downstream data processing module, a data request management module and an upstream management module; the downstream data processing module is used for transmitting the acquired target downstream data to the upstream management module; the target downstream data is obtained by reading a target data request of cache miss in a downstream memory; the data request management module is used for transmitting target data request information associated with target downstream data to the upstream management module; the upstream management module is used for transmitting the target downstream data and the associated target data request information to the upstream equipment so as to respond to the target data request.
Description
Technical Field
The present disclosure relates to the field of processor technologies, and in particular, to a data request processing circuit and method, and a cache circuit and a processor thereof.
Background
In order to prevent the upstream from being blocked for continuous operation under the condition of a cache miss, a cache circuit of the current processor introduces a miss state processing register (Miss status Handling Registers, MSHR) circuit to complete the realization of non-blocking cache.
In a conventional MSHR circuit, when downstream Data is returned, the MSHR circuit first writes the downstream Data into a cached Data random access memory (Data RAM), and then reads the stored downstream Data from the Data RAM and returns the Data to the upstream, so as to implement a response corresponding to the Data request.
However, the foregoing method needs to write the returned downstream Data into the Data RAM and read the Data RAM, and the read-write needs to take a lot of time, which causes a problem of low Data request efficiency.
Disclosure of Invention
An objective of the embodiments of the present application is to provide a data request processing circuit, a data request processing method, a cache circuit and a processor thereof, which are used for solving the problem of low efficiency of the conventional MSHR circuit.
In a first aspect, the present invention provides a data request processing circuit comprising: a downstream data processing module, a data request management module and an upstream management module; the downstream data processing module is used for transmitting the acquired target downstream data to the upstream management module; the target downstream data is obtained by reading a target data request of cache miss in a downstream memory; the data request management module is used for transmitting target data request information associated with target downstream data to the upstream management module; the upstream management module is used for transmitting the target downstream data and the associated target data request information to the upstream device to respond to the target data request.
According to the Data request processing circuit, when the target downstream Data is obtained through the downstream Data processing module, the obtained target downstream Data is directly transmitted to the upstream management module, target Data request information related to the target downstream Data is transmitted to the upstream management module through the Data request management module, the obtained target downstream Data and the related target Data request information are transmitted to the upstream equipment through the upstream management module, and accordingly, the target Data request is responded.
In an alternative implementation of the first aspect, the downstream data processing module is electrically connected to an upstream management module, the data request management module is electrically connected to the upstream management module, and the upstream management module is configured to be electrically connected to the upstream device.
In an optional implementation manner of the first aspect, the circuit further includes a buffer module, and the downstream data processing module is electrically connected to the buffer module; the downstream data processing module is further configured to write the target downstream data into the cache module. The present embodiment writes the target downstream data into the cache module 40 for storage, so that the target data request achieves cache hit in the next access, thereby directly reading from the cache, improving access efficiency and reducing power consumption.
In an alternative implementation of the first aspect, the data request management module stores a plurality of cache miss data requests; the data request module is further configured to determine, among a plurality of cache miss data requests, a target data request associated with the target downstream data, so as to obtain target data request information of the target data request.
In an alternative implementation of the first aspect, the downstream data processing module is electrically connected to the data request management module; the downstream data processing module is also used for transmitting a target request identifier corresponding to the acquired target downstream data to the data request management module; the data request management module is further used for searching the data requests with the same request identifier from the data requests with the cache miss according to the target request identifier corresponding to the target downstream data transmitted by the downstream data processing module, and obtaining the target data request associated with the target downstream data. According to the method and the device, the data request management module is used for sending information of all target data requests related to target downstream data to the upstream management module, so that all data requests related to target downstream data are processed at one time, access is not needed for multiple times, and access power consumption is reduced.
In an optional implementation manner of the first aspect, the downstream data processing module is further configured to obtain target data request information of the cache miss transmitted by the data request management module; reading corresponding data in a downstream memory according to the target identifier to obtain target downstream data; wherein the target data request information includes a target request identification.
In an optional implementation manner of the first aspect, the destination request identifier includes at least one of a destination request address and a unique identifier carried by the destination request.
In a second aspect, the present invention provides a buffer circuit, where the buffer circuit includes a data request processing circuit according to any one of the embodiments of the first aspect.
The cache circuit of the design comprises the Data request processing circuit of any optional embodiment, so that the cache circuit directly transmits target downstream Data and target Data request information related to the target downstream Data to the upstream under the condition of Data request cache miss, and writing and reading of a Data RAM are not needed, thereby improving response time and power consumption of the Data request with the cache miss.
In a third aspect, the present invention provides a processor comprising the cache circuit of the second aspect.
The processor with the design comprises the cache circuit, so that the processor directly transmits target downstream Data and target Data request information related to the target downstream Data to the upstream under the condition that the Data request cache misses, and does not need to write and read the Data RAM, thereby improving the response time and the power consumption of the Data request with the cache miss.
In a fourth aspect, the present invention provides a data request processing method, the method including: when the target downstream data is obtained by reading in the downstream memory according to the target data request information, the target downstream data and the target data request information associated with the target downstream data are directly transmitted to the upstream device so as to respond to the target data request.
According to the Data request processing method, the returned downstream Data is directly transmitted to the upstream, and the target Data request information related to the downstream Data is also returned to the upstream, so that the response to the target Data request with the cache miss is performed, writing and reading of the Data RAM are not needed, and the response time and the power consumption of the Data request with the cache miss are further improved.
In an alternative embodiment of the fourth aspect, before transmitting the target downstream data and the target data request information associated with the target downstream data to the upstream device, the method further comprises: searching data requests with the same request identifier in a plurality of cache miss data requests according to the target request identifier corresponding to the target downstream data, and obtaining the target data request associated with the target downstream data.
In an alternative embodiment of the fourth aspect, the method further comprises: and writing the target downstream data into the cache module.
The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.
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In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first architecture of a data request processing circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a second structure of a data request processing circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a third configuration of a data request processing circuit according to an embodiment of the present disclosure;
fig. 4 is a flow chart of a data request processing method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Icon: 10-a downstream data processing module; 20-a data request management module; 30-an upstream management module; a 40-cache module; a-upstream device; 5-an electronic device; 501-a processor; 502-memory; 503-communication bus.
Detailed Description
Embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solutions of the present application, and thus are only examples, and are not intended to limit the scope of protection of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions.
In the description of the embodiments of the present application, the technical terms "first," "second," etc. are used merely to distinguish between different objects and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, a particular order or a primary or secondary relationship. In the description of the embodiments of the present application, the meaning of "plurality" is two or more unless explicitly defined otherwise.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, which means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the embodiments of the present application, the term "plurality" refers to two or more (including two), and similarly, "plural sets" refers to two or more (including two), and "plural sheets" refers to two or more (including two).
In the description of the embodiments of the present application, the orientation or positional relationship indicated by the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of describing the embodiments of the present application and for simplifying the description, rather than indicating or implying that the apparatus or element referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present application.
In the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; or may be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to the specific circumstances.
The data access mode of the current processor generally refers to that firstly, data of a corresponding address is found in a cache according to an access address, if the corresponding address and specific data corresponding to the address exist in the cache, the data is called cache hit, and under the condition of the cache hit, the data request/data access response can be realized by generally directly reading the corresponding specific data in the cache; if there is no corresponding address and specific data in the cache (hereinafter referred to as primary miss) or there is no corresponding address but no specific data in the cache (secondary miss), then the specific data of the corresponding address needs to be fetched into the memory, which is referred to as cache miss.
In the case of a cache miss, the cache circuit needs to read specific data of a corresponding address from the memory, and the time taken for reading from the upstream memory to the downstream memory is long and a large amount of power consumption is required, and meanwhile, the next access request is blocked in the long-time data reading process, so that a large overhead exists in the case of a cache miss.
In order to avoid blocking the upstream operation in case of a cache miss, the cache circuit currently introduces a miss status handling register (Miss status Handling Registers, MSHR) circuit to complete the implementation of the non-blocking cache.
In a conventional MSHR circuit, when downstream Data is returned, the MSHR circuit first writes the downstream Data into a cached Data random access memory (Data RAM), and then reads the stored downstream Data from the Data RAM and returns the Data to the upstream, so as to implement a response corresponding to the Data request.
The inventor discovers that the traditional MSHR circuit needs to write the downstream Data into the Data RAM firstly and then read the Data from the Data RAM, and the Data read-write can consume longer time and a great deal of power consumption, thereby causing lower response efficiency of the Data request and increase of the power consumption; furthermore, under the condition that all cache miss requests corresponding to a certain address access the cache, the address is not allowed to be replaced in the cache, so that the cache consumes extra capacity to record the states of all requests corresponding to the address, and the capacity of the cache in the period of time is reduced; in addition, when the Data of the same address is accessed by different devices at the same time, namely, when a plurality of requests of the same address exist in the MSHR circuit, the traditional mode needs to access the Data RAM for a plurality of times, thereby bringing about waste of power consumption; finally, the existing MSHR circuit is separately managed for primary and secondary classes, for example, 3 primary classes and 7 secondary classes of hardware resources are set in the MSHR circuit, which may cause performance loss in some scenarios due to inflexibility of hardware resources.
Based on the above problems, the present inventors devised a Data request processing circuit, method, and cache circuit and processor thereof, and when downstream Data is returned, the present solution directly transmits the returned downstream Data to the upstream, and returns the target Data request information associated with the downstream Data to the upstream, so as to respond to the target Data request with a cache miss, thereby eliminating the need to write and read the Data RAM, and further improving the response time and power consumption of the Data request with a cache miss; because the downstream Data does not need to be written into the cached Data RAM in the response process to the target Data request, the extra capacity of the cache is not consumed; because the target data request information associated with the downstream data is returned to the upstream, all data requests associated with the downstream data are processed at one time, access is not needed for multiple times, and access power consumption is reduced; in addition, the scheme does not need to separately manage primary and secondary mix, so that the flexibility of hardware can be better utilized.
Based on the foregoing, as shown in fig. 1, the present application provides a data request processing circuit, where the data request processing circuit includes a downstream data processing module 10, a data request management module 20, and an upstream management module 30, and referring to a circuit connection manner of the present embodiment illustrated in fig. 1, the downstream data processing module 10 is electrically connected to the upstream management module 30, the data request management module 20 is electrically connected to the upstream management module 30, and the upstream management module 30 can be electrically connected to the upstream device a. The upstream and downstream devices are distinguished based on information flow, for example, in a data request process, the upstream device initiates a data request, then accesses a cache according to the data request, if the cache misses, accesses a memory, the memory returns data corresponding to the data request, in the process, the memory is called downstream based on the data returned by the data request/data access, and the device initiating the data request/data access is called upstream device, where the upstream device may specifically be: user terminals, servers, computers, etc.
In the data request processing circuit of the above design, the downstream data processing module 10 is configured to directly transmit, when obtaining target downstream data, the obtained target downstream data to the upstream management module 30, where the target downstream data is data corresponding to a target data request obtained from a memory in a case of a cache miss, where the target data request may be a target address access request or the like.
In the above case, the data request management module 20 is configured to transmit the target data request information associated with the target downstream data to the upstream management module 30, where in general, there may be multiple data requests with cache misses in the data request management module 20 at the same time, so when the target downstream data returns, the data request management module 20 needs to find a data request corresponding to the target downstream data in the multiple data requests with cache misses based on the returned target downstream data, thereby obtaining the target data request information associated with the target downstream data, and then transmit the target data request information associated with the target downstream data to the upstream management module 30. For example, there are multiple cache miss data requests in the data request management module 20: request 1, request 2, request 3, and request 4, provided that the corresponding data request is found as request 4 in the plurality of cache miss data requests based on the returned target downstream data, then the relevant request information for request 4 is sent to the upstream management module 30.
The upstream management module 30 transmits the resulting target downstream data and associated target data request information to the upstream device a in response to the target data request initiated by the upstream device. As a possible implementation manner, the target downstream data and the target data request information associated with the target downstream data may be sent to the upstream management module 30 at the same time, and the upstream management module 30 may transmit the target downstream data and the target data request information associated with the target downstream data to the upstream device a after receiving the target downstream data and the target data request information associated with the target downstream data; as yet another possible implementation, since the data request management module 20 needs to determine the target data request first and then send the target data request information, the target downstream data may be received by the upstream management module 30 first, in which case, the upstream management module 30 may temporarily store the target downstream data, wait for receiving the target data request information associated with the target downstream data, and then transmit the target downstream data and the target data request information associated with the target downstream data to the upstream device a together.
In the Data request processing circuit designed in the above manner, when the downstream Data processing module 10 obtains the target downstream Data, the obtained target downstream Data is directly transmitted to the upstream management module 30, the target Data request information related to the target downstream Data is transmitted to the upstream management module 30 through the Data request management module 20, and the obtained target downstream Data and the related target Data request information are transmitted to the upstream device a through the upstream management module 30, so that the target Data request is responded.
In an alternative implementation of the present embodiment, the foregoing description to the data request management module 20 may determine the target data request associated with the target downstream data from among the data requests in the plurality of cache misses (cache misses). As a possible implementation manner, as shown in fig. 2, the downstream data processing module 10 may be electrically connected to the data request management module 20, on the basis that the downstream data processing module 10 may transmit the obtained target request identifier of the target downstream data to the data request management module 20, and the data request management module 20 may search for a data request with the same request identifier from multiple cache miss data requests according to the target request identifier of the target downstream data, so as to obtain a target data request associated with the target downstream data.
For example, according to the foregoing example, assuming that the request identifier corresponding to the request 1 is A1, the request identifier corresponding to the request 2 is A2, the request identifier corresponding to the request 3 is A3, the request identifier corresponding to the request 4 is A4, and the target request identifier of the target downstream data acquired by the downstream data processing module 10 is A4, the data request management module 20 may find the request 4 with the same request identifier A4 according to the target request identifier A4, thereby obtaining the request 4 associated with the target downstream data.
As one possible implementation, the target request identifier may include a unique identifier carried by the target request, for example, A1, A2, A3, and A4 described above may be unique identifiers of corresponding requests; as a further possible implementation manner, since the access data has the characteristic information of the corresponding access address, the destination request identifier may also be the destination request address, and the data request management module 20 may search the data requests with the same request address in the multiple cache miss data requests according to the destination request address of the destination downstream data, so as to obtain the destination data request associated with the destination downstream data.
Further, in some cases, the data at the same address may be accessed by different devices at the same time, where there may be multiple requests with the same request address in the data request management module 20 at the same time, the data request management module 20 may search for multiple data requests with the same request address in multiple cache miss data requests according to the target request address of the target downstream data, and on this basis, the data request management module 20 may send the multiple data requests with the same request address as the target downstream data to the upstream management module 30. For example, in the data request management module 20, there are a request 1, a request 2, a request 3 and a request 4, where the address corresponding to the request 1 is 00, the addresses corresponding to the requests 2 and 3 are both 11, the address corresponding to the request 4 is 01, and the target request address corresponding to the acquired target downstream data is 11, then it may be determined that the target data request associated with the target downstream data is the request 2 and the request 3.
In the above designed embodiment, the data request management module 20 sends the information of all the target data requests related to the target downstream data to the upstream management module 30, so that all the data requests related to the target downstream data are processed once, and therefore access is not needed for multiple times, and access power consumption is further reduced.
It should be noted that, after the data request management module 20 transmits the target data request information associated with the target downstream data to the upstream management module 30, the data request management module 20 may perform a status update on the data request stored by itself, for example, the data request management module 20 may delete the target data request information stored by itself, thereby releasing the capacity of the data request management module 20, and preparing for receiving the data request with another cache miss.
In an alternative implementation manner of this embodiment, as a possible implementation manner, the target downstream data may be accessed and read by a dedicated memory access module based on the target request address of the target downstream data, and then sent to the downstream data processing module 10, where the downstream data processing module 10 directly sends the target downstream data to the upstream management module 30.
As yet another possible implementation, the downstream data processing module 10 may access the memory by itself, so as to read the memory to obtain the target downstream data. Specifically, the data request management module 20 may send a target request identifier (e.g. a target request address) of target downstream data to be read to the downstream data processing module 10, and the downstream data processing module 10 may read the corresponding target downstream data in the memory according to the target request identifier (e.g. the target request address), and after the downstream data processing module 10 reads the target downstream data, send the target downstream data directly to the upstream management module 30.
It should be noted that, when the target downstream data is read from the memory by the downstream data processing module 10 to obtain the target downstream data, the downstream data processing module 10 will still feed back the target request identifier of the target downstream data to the data request management module 20, so as to trigger the data request management module 20 to find the target data request associated with the target downstream data.
In an alternative implementation of the present embodiment, as shown in fig. 3, the data request processing circuit may further include a buffer module 40, where the buffer module 40 is electrically connected to the downstream data processing module 10.
The downstream data processing module 10 may also write the target downstream data into the cache module 40. The buffer module 40 may be a Data random access memory (Data RAM).
As one possible implementation, the downstream data processing module 10 may write the target downstream data into the cache module 40 after sending the target downstream data to the upstream management module 30. As yet another possible implementation, the downstream data processing module 10 may write the target downstream data into the cache module 40 while sending the target downstream data to the upstream management module 30. The specific writing time is not limited, and the scheme can be adaptively adjusted according to the actual scene requirement.
It should be noted that, although the target downstream data is written into the cache module 40 in this embodiment, in the case of a cache miss, the target downstream data acquired by the upstream management module 30 is not obtained by reading from the cache module 40, but is directly transmitted by the downstream data processing module 10. The downstream data processing module 10 is adopted to write the target downstream data into the cache module 40 for storage, and the purpose is to consider the condition that the target corresponding to the target downstream data requests for next access, so as to avoid the condition that the target data requests are missed again, and thus the memory reading power consumption and the low efficiency are brought.
In addition, since the target downstream data does not need to be acquired by accessing the buffer module 40, after the target downstream data is written into the buffer module 40, the buffer module 40 does not need to occupy capacity to record whether the corresponding data can be replaced, thereby reducing the capacity loss of the buffer module 40.
In the data request processing circuit designed as above, the downstream data processing module 10 sends the target downstream data to the upstream management module 30, and the downstream data processing module 10 transmits the target request identifier corresponding to the target downstream data to the data request management module 20, so that the data request management module 20 searches the data requests with the same target request identifier in the data requests with a plurality of cache misses to obtain the target data request associated with the target downstream data, and then the data request management module 20 transmits the target data request information associated with the target downstream data to the upstream management module 30, so that the target downstream data and the target data request information are returned to the upstream device A through the upstream management module 30, and the target request of the upstream device A is responded, so that the upstream device A can obtain the access data corresponding to the target data request.
The Data request processing circuit designed based on the scheme directly transmits the target downstream Data to the upstream, so that the Data request processing circuit designed according to the scheme does not need to write and read the Data RAM, and further response time and power consumption of the Data request with cache miss are improved; furthermore, the data request management module 20 sends the information of all the target data requests related to the target downstream data to the upstream management module 30, so that all the data requests related to the target downstream data are processed once, access is not needed for a plurality of times, and access power consumption is reduced; in addition, since the target downstream data does not need to be acquired by accessing the buffer module 40, after the target downstream data is written into the buffer module 40, the buffer module 40 does not need to occupy capacity to record whether the corresponding data can be replaced, thereby reducing the capacity loss of the buffer module 40.
In an optional implementation manner of this embodiment, the present application further provides a buffer circuit, where the buffer circuit includes the data request processing circuit described in any one of the foregoing optional implementation manners.
The cache circuit of the design comprises the Data request processing circuit of any optional embodiment, so that the cache circuit directly transmits target downstream Data and target Data request information related to the target downstream Data to the upstream under the condition of Data request cache miss, and writing and reading of a Data RAM are not needed, thereby improving response time and power consumption of the Data request with the cache miss.
In an alternative implementation of this embodiment, the present application further provides a processor, where the processor includes the foregoing buffer circuit.
The processor with the design comprises the cache circuit, so that the processor directly transmits target downstream Data and target Data request information related to the target downstream Data to the upstream under the condition that the Data request cache misses, and does not need to write and read the Data RAM, thereby improving the response time and the power consumption of the Data request with the cache miss.
In an optional implementation manner of this embodiment, the present application further provides a data request processing method, where the data request processing method may be applied to a computing device, where the computing device includes, but is not limited to, a cache circuit described above, a processor including the cache circuit, a chip including the processor, a computer, a server, and so on, and as shown in fig. 4, the data request processing method may be implemented by including:
step S400: when target downstream data is obtained by reading in a downstream memory according to the target data request information, the target downstream data and the target data request information associated with the target downstream data are directly transmitted to upstream equipment.
In the above embodiment, the target data request information may include an access address, an access identifier, and the like of a target data request, where the target data request refers to a data request that is not hit in a cache, and in the case of a cache miss, the access data required by the data request needs to be read from a downstream memory, where the manner of reading from the downstream memory may be obtained according to the foregoing reading based on a dedicated memory reading module, or may be obtained by reading from the foregoing downstream data processing module.
When the target downstream data is read and obtained in the downstream memory according to the target data request information, the target downstream data obtained from the downstream memory and the target data request information related to the target downstream data are directly transmitted to the upstream equipment, so that the target data request of the corresponding upstream equipment is achieved. It is directly indicated that, when the target downstream data is obtained from the downstream memory, the target downstream data is immediately transmitted to the upstream device, and is not cached or stored.
According to the Data request processing method, the returned downstream Data is directly transmitted to the upstream, and the target Data request information related to the downstream Data is also returned to the upstream, so that the response to the target Data request with the cache miss is performed, writing and reading of the Data RAM are not needed, and the response time and the power consumption of the Data request with the cache miss are further improved.
In an optional implementation manner of this embodiment, before directly transmitting the target downstream data and the target data request information associated with the target downstream data to the upstream device, the present solution may obtain a target request identifier corresponding to the target downstream data, and then search, according to the target request identifier, a data request with the same target request identifier from a plurality of data requests that miss in a cache, so as to determine a target data request, and further obtain the target data request information. Wherein the target data request information may include a target data request address, a target data requestor, and the like.
In an optional implementation manner of this embodiment, the present solution may further store the target downstream data in the cache module.
According to some embodiments of the present application, as shown in fig. 5, the present application provides an electronic device 5, including: the processor 501 and the memory 502, the processor 501 and the memory 502 are interconnected and communicate with each other by a communication bus 503 and/or other form of connection mechanism (not shown), the memory 502 stores a computer program executable by the processor 501, which when the computing device is running, is executed by the processor 501 to perform the method performed in the foregoing implementation, for example step S400: when target downstream data is obtained by reading in a downstream memory according to target data request information, the target downstream data and target data request information associated with the target downstream data are directly transmitted to upstream equipment so as to respond to the target data request.
The present application provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the method of the preceding implementation.
The storage medium may be implemented by any type of volatile or nonvolatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
The present application provides a computer program product which, when run on a computer, causes the computer to perform the aforementioned method.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the embodiments, and are intended to be included within the scope of the claims and description. In particular, the technical features mentioned in the respective embodiments may be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions falling within the scope of the claims.
Claims (12)
1. A data request processing circuit, the circuit comprising: a downstream data processing module, a data request management module and an upstream management module;
the downstream data processing module is used for transmitting the acquired target downstream data to the upstream management module; the target downstream data is obtained by reading a target data request of cache miss in a downstream memory;
the data request management module is used for transmitting the target data request information associated with the target downstream data to the upstream management module;
the upstream management module is used for transmitting the target downstream data and associated target data request information to upstream equipment so as to respond to the target data request.
2. The circuit of claim 1, wherein the downstream data processing module is electrically connected to the upstream management module, the data request management module is electrically connected to the upstream management module, and the upstream management module is configured to be electrically connected to an upstream device.
3. The circuit of claim 1, further comprising a buffer module, the downstream data processing module being electrically connected to the buffer module;
the downstream data processing module is further configured to write the target downstream data into the cache module.
4. The circuit of claim 1, wherein the data request management module stores a plurality of cache miss data requests;
the data request management module is further configured to determine, among a plurality of cache miss data requests, a target data request associated with the target downstream data, so as to obtain target data request information of the target data request.
5. The circuit of claim 4, wherein the downstream data processing module is electrically connected to the data request management module;
the downstream data processing module is further used for transmitting a target request identifier corresponding to the acquired target downstream data to the data request management module;
the data request management module is further configured to search for a data request with the same request identifier from the plurality of cache miss data requests according to the target request identifier corresponding to the target downstream data transmitted by the downstream data processing module, and obtain a target data request associated with the target downstream data.
6. The circuit of claim 4, wherein the downstream data processing module is further configured to obtain cache miss target data request information transmitted by the data request management module; reading corresponding data in a downstream memory according to a target request identifier to obtain target downstream data;
wherein the target data request information includes a target request identification.
7. The circuit of claim 5 or 6, wherein the destination request identification comprises at least one of a destination request address and a unique identification carried by the destination request.
8. A cache circuit comprising the data request processing circuit of any one of claims 1-7.
9. A processor comprising the cache circuit of claim 8.
10. A method of processing a data request, the method comprising:
when target downstream data is obtained by reading in a downstream memory according to target data request information, the target downstream data and target data request information associated with the target downstream data are directly transmitted to upstream equipment so as to respond to the target data request.
11. The method of claim 10, wherein prior to said transmitting the target downstream data and the target data request information associated with the target downstream data to an upstream device, the method further comprises:
searching data requests with the same request identification from a plurality of cache miss data requests according to the target request identification corresponding to the target downstream data, and obtaining the target data request associated with the target downstream data.
12. The method according to claim 10, wherein the method further comprises: and writing the target downstream data into a cache module.
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