CN114579478A - Method for processing message in 5G network multi-core, electronic equipment and storage medium - Google Patents
Method for processing message in 5G network multi-core, electronic equipment and storage medium Download PDFInfo
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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Abstract
The invention discloses a method for processing a message by multiple cores of a 5G network, electronic equipment and a storage medium, wherein the method for processing the message by the multiple cores of the 5G network is applied to a processor, the processor comprises a first kernel and a second kernel, and the method comprises the following steps: receiving a service message and determining description information of the service message; obtaining address information of the service message according to the description information, and reading the address information into a cache of the first kernel; reading the content of the service message, determining that the service message needs to be processed by the first kernel and the second kernel concurrently, and reading the address information into the cache of the second kernel. The invention has smaller time delay when the multi-core processes the message, improves the concurrent rate of the message and finally improves the performance of the processor.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a method, an electronic device, and a storage medium for processing a packet in a 5G network with multiple cores.
Background
The current Central Processing Unit (CPU), also called a processor, mostly adopts a multi-core technology, that is, multiple cores exist in one physical processor, and each core can work concurrently and execute respective codes. In the related art, after an ethernet packet is received from a network port hardware, the ethernet packet is generally processed by one kernel, and if a plurality of kernels process the same packet, inconsistency of multi-core packet cache (cache) occurs, so that the content needs to be read from the memory to the cache again, delay of the packet in multi-core processing is increased, the kernel triggers a page fault, and slows down the concurrency rate of the packet, which finally affects the performance of the processor.
Disclosure of Invention
In view of this, the present invention provides a method, an electronic device, and a storage medium for processing a packet in a multi-core 5G network, which are used to solve the problem in the prior art that a multi-core processor is poor in performance when processing. To achieve one or a part or all of the above or other objects, the following embodiments are provided:
an embodiment of a first aspect of the present invention provides a method for processing a packet in a 5G network with multiple cores, where the method is applied to a processor, where the processor includes a first core and a second core, and the method includes: receiving a service message and determining description information of the service message; obtaining address information of the service message according to the description information, and reading the address information into a cache of the first kernel; reading the content of the service message, determining that the service message needs to be processed by the first kernel and the second kernel concurrently, and reading the address information into the cache of the second kernel.
Preferably, the obtaining address information of the service packet according to the description information and reading the address information into the cache of the first kernel includes: obtaining the physical address of the service message according to the description information; obtaining a virtual address corresponding to the service message according to the physical address; and determining to obtain the address information according to the virtual address, and reading the address information into a cache of the first kernel.
Preferably, the describing information includes length information of the service packet, and the determining to obtain the address information according to the virtual address and reading the address information into the cache of the first core includes: invalidating the cache of the first core; determining to obtain the address information according to the virtual address, and determining that the address information is an initial address of the cache of the first kernel; determining the length information as the length of the cache of the first kernel; and triggering a cache and memory synchronization mechanism in the processor, and reading the address information and the length information into the cache of the first kernel.
Preferably, the reading the address information into the cache of the second core includes: invalidating the cache of the second core; determining that the address information is a starting address of the cache of the second core; determining the length information as the length of the cache of the second kernel; and reading the address information and the length information into a cache of the second kernel.
Preferably, the determining that the address information is a start address of a cache of the second core includes: obtaining a physical address of the service message according to the description information; obtaining a virtual address corresponding to the service message according to the physical address; and determining to obtain the address information according to the virtual address, and determining that the address information is the initial address of the cache of the second kernel.
Preferably, the reading the address information and the length information into the cache of the second core includes: obtaining the storage time cached in the second kernel; acquiring a preset time threshold, and determining the cache in the second kernel, of which the storage time is greater than the preset time threshold, as a target cache; and eliminating the target cache in the second kernel through internal cache management of the processor, and reading the address information and the length information into the cache of the second kernel after elimination.
Preferably, before the receiving the service packet and determining the description information of the service packet, the method further includes: acquiring an initialization setting instruction of the processor, and setting a network port driving packet receiving thread of the processor according to the initialization setting instruction so that the processor receives the service message; creating a first service processing thread of the first kernel, and enabling the first service processing thread to be compatible with the first kernel, wherein the first service processing thread is used for processing the service message; creating a second service processing thread of the second kernel, and making the second service processing thread compatible with the second kernel, wherein the second service processing thread is used for processing the service message; and the service message is attached to the first kernel for execution.
Preferably, after reading the address information into the cache of the second core, the method further includes: acquiring a memory pointer corresponding to the processor; and transmitting the address information corresponding to the memory pointer to the first service processing thread and the second service processing thread so that the first kernel and the second kernel can concurrently process the service message.
An embodiment of a second aspect of the present invention provides an electronic device, including: the memory, the processor, and the computer program stored in the memory and executable on the processor are characterized in that the processor, when executing the computer program, implements the method for processing packets in a 5G network multi-core as described in any one of the embodiments of the first aspect of the present invention.
A third embodiment of the present invention provides a computer-readable storage medium, where computer-executable instructions are stored, and the computer-executable instructions are configured to execute the method for processing a packet in a 5G network with multiple cores according to any one of the embodiments of the first aspect of the present invention.
The embodiment of the invention has the following beneficial effects:
by the method, the electronic device and the storage medium for processing the message by the 5G network multi-core in the embodiment of the invention, when the processor processes the service message by the multi-core, the description information of the service message can be determined after receiving the service message, the address information of the service message is obtained according to the description information, and the address information is read into the cache of the first core, so that the service message is concurrently processed by the first core and the second core in order to reduce the problem of page fault when the second core processes the service message, and therefore, the address information is also read into the cache of the second core, so that the first core and the second core concurrently process the service without mutual conflict.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
FIG. 1 is a diagram of a processor processing traffic in one embodiment;
FIG. 2 is a schematic diagram of a processor processing traffic in another embodiment;
fig. 3 is a flowchart illustrating a method for processing a packet in a 5G network multi-core in an embodiment;
fig. 4 is a flowchart illustrating a method for processing a packet in a 5G network multi-core in an embodiment;
fig. 5 is a flowchart illustrating a method for processing a packet in a multi-core 5G network in an embodiment;
fig. 6 is a flowchart illustrating a method for processing a packet in a 5G network multi-core in an embodiment;
fig. 7 is a flowchart illustrating a method for processing a packet in a multi-core 5G network according to an embodiment;
fig. 8 is a flowchart illustrating a method for processing a packet in a 5G network multi-core in an embodiment;
fig. 9 is a flowchart illustrating a method for processing a packet in a multi-core 5G network according to an embodiment;
fig. 10 is a flowchart illustrating a method for processing a packet in a multi-core of a 5G network according to an embodiment;
fig. 11 is a schematic structural diagram of an electronic device in one embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a processor (CPU) includes a core 1 and a core 2, which run 2 independent threads 1 and 2 respectively, and are used for processing different protocols of a packet, so that a utilization rate of CPU performance 1+1 ═ 2 can be achieved, for example, the core 1 processes a two-layer packet header (MAC packet header) of the packet, the core 2 processes a three-layer packet header (IP packet header) of the packet, a service flow needs to process two layers first and then three layers, the core 1 processes only the two-layer packet header, and the core 2 processes only the three-layer packet header. The software architecture flow gives consideration to multi-core CPU concurrency, and meanwhile, business association does not exist between different kernels.
As shown in fig. 2, after a service packet of a network port is received, the service packet is stored in a memory and processed by a kernel 1, at this time, a cache (cahce) of the kernel 1 is consistent with the content of the packet stored in the memory, and when the kernel 2 processes the packet, the packet memory is not in the cache of the kernel 2, the kernel 2 triggers a page fault, the packet memory needs to be read into the cache of the kernel 2 again, the execution time of the kernel 2 is greatly increased in the whole process, and the concurrency rate of the packet is finally slowed down.
Based on this, embodiments of the present invention provide a method, an electronic device, and a storage medium for processing a packet in a 5G network multi-core, which are used to solve the problem of poor performance of a processor during multi-core processing in the prior art, and specifically, the following embodiments are described to first describe the method for processing a packet in a 5G network multi-core in the embodiments of the present invention.
As shown in fig. 3, the method for processing a packet in a 5G network with multiple cores provided in the embodiment of the present invention may be applied to a processor, and the method includes, but is not limited to, step S101 to step S103.
Step S101, receiving a service message and determining the description information of the service message.
And step S102, obtaining the address information of the service message according to the description information, and reading the address information into the cache of the first kernel.
Step S103, reading the content of the service message, determining that the service message needs to be processed by the first kernel and the second kernel concurrently, and reading the address information into the cache of the second kernel.
In an embodiment, a method for processing a packet by multiple cores in a 5G network may be applied to a processor, and may receive and process a service packet in the 5G network, where the processor may be a CPU described in the drawings in the foregoing embodiments, the processor is provided with a first core and a second core, the first core may be a core 1 in the foregoing embodiments, and the second core may be a core 2 in the foregoing embodiments, and in the embodiment of the present invention, the processor is provided with two cores as an example, it may be understood that the number of cores of the processor may also be other cores, and this embodiment of the present invention only describes, by taking a processor with two cores as an example, and does not represent a limitation to the present invention.
After the processor works, a service message is received from a network port hardware register, description information of the currently received message is determined, the description information is used for representing information such as characteristics of the service message, the description information can comprise physical address and length information of the service message, address information of the service message can be obtained according to the description information, the address information represents an address of the service message in a memory, the address information is read into a cache of a first kernel, so that the first kernel processes the service message, whether the service message needs to be processed by a second kernel or not is judged, content of the service message is read, the service message needs to be processed by the first kernel and the second kernel concurrently according to the content, and the address information is synchronously read into the cache of the second kernel.
In one embodiment, the processor concurrently processes one message through two cores, thereby improving the utilization rate of the processor. In the embodiment of the invention, each independent kernel, such as the first kernel and the second kernel, has an independent cache mechanism, the process of processing the message is to read or modify data in the memory, the process of reading the memory accesses the cache first, if the cache does not exist, the cache missing exception of the processor is triggered, the memory data needs to be led into the cache, and the process consumes time. After the network port receives the packet, the memory where the packet is located is immediately led into the cache of the second kernel, so that the memory cannot be temporarily led in during processing, and the processing efficiency is obviously improved.
It should be noted that, in the embodiment of the present invention, address information of one service packet is obtained at the same time, the first kernel processes the two-layer packet header of the packet, and the second kernel processes the three-layer packet header of the packet, and the packets are processed concurrently without conflict.
As shown in fig. 4, the above method step S102 may further include, but is not limited to, step S201 to step S203.
Step S201, obtaining the physical address of the service packet according to the description information.
Step S202, a virtual address corresponding to the service message is obtained according to the physical address.
Step S203, determining to obtain address information according to the virtual address, and reading the address information into the cache of the first kernel.
In an embodiment, a virtual address of a service packet is used as address information, specifically, a processor obtains a physical address where the service packet is currently located according to description information, obtains a virtual address corresponding to the service packet according to the physical address, determines to obtain address information according to the virtual address, for example, the virtual address is used as the address information, and reads the address information into a cache of a first kernel, so that the cache of the first kernel is consistent with a memory.
As shown in fig. 5, the description information includes length information of the service packet, and step S203 of the method may further include, but is not limited to, step S301 to step S304.
Step S301, the cache of the first kernel is invalidated.
Step S302, address information is determined and obtained according to the virtual address, and the address information is determined to be the initial address of the cache of the first kernel.
Step S303, determining the length information as the length of the cache of the first kernel.
Step S304, triggering a cache and memory synchronization mechanism inside the processor, and reading the address information and the length information into the cache of the first core.
In an embodiment, the size of any processing core is limited, after a system applied by a processor runs for a long time, a cache is easily full, and then new data is imported into the cache, and the original cache must be cleaned, otherwise, the performance of the processor is affected, in the embodiment of the present invention, when the processor processes a service message, the first core does not need to process other services, and therefore, the first core is used as the cache of the first core, it can be understood that, when the first core also processes other services at the same time, the processor can also invalidate the cache which runs for a long time and is not used, the invalidated cache is not necessarily a network interface message, but is the cache which is not used for the longest time, the cache which needs to be processed is reserved, and no specific limitation is made to this, and accordingly, the processor uses a virtual address as address information according to a virtual address of the service message, and uses the virtual address as a starting address of the cache of the first core, the description information in the embodiment of the present invention further includes length information of the service packet, and then the processor determines that the length information is the length of the cache in the first core, so that the first core processes the service packet, and triggers a cache and memory synchronization mechanism inside the processor to read the address information and the length information into the cache of the first core.
In an embodiment of the present invention, the length of the service packet determines the length to be imported into the cache, and in the embodiment of the present invention, the description information not only needs to provide the physical address of the service packet, but also provides the length of the service packet as length information, so as to facilitate subsequent processing.
It should be noted that triggering the cache and memory synchronization mechanism inside the processor is an internal hardware function of the processor, and when a certain section of memory is cached to be invalidated, software accesses the address to automatically trigger the synchronization of the hardware cache and the memory.
In the embodiment of the invention, each kernel has own cache, the service message can be processed by the first kernel, whether the second kernel is needed to process or not needs to be judged, if the second kernel is needed to process, the message needs to be imported into the caches of the first kernel and the second kernel, otherwise, only the cache of the first kernel needs to be imported.
As shown in fig. 6, the description information includes length information of the service packet, and the step S103 of the method may further include, but is not limited to, step S401 to step S404.
Step S401, the cache of the second kernel is invalidated.
Step S402, determining the address information as the starting address of the cache of the second core.
Step S403, determining the length information as the length of the cache of the second core.
Step S404, reading the address information and the length information into the cache of the second core.
In an embodiment, after it is determined that the service packet needs to be processed by the second core, the processor may invalidate the cache of the second core, determine that the address information is an initial address of the cache of the second core, determine that the length information is the length of the cache of the second core, read the address information and the length information into the cache of the second core, and keep the cache of the second core consistent with the memory and consistent with the cache of the first core, so as to concurrently process the same packet, reduce the processor execution time introduced by cache inconsistency between cores, and greatly improve the packet processing efficiency.
In the embodiment of the present invention, it may be determined according to a service model whether a service packet needs to be concurrently processed by a first kernel and a second kernel, that is, whether a second kernel needs to process the service packet is determined, for example, a two-layer packet header, that is, an MAC packet header, is processed by the first kernel, a three-layer packet header, that is, an IP packet header, is processed by the second kernel, after a network port driver receives a service agent packet, it is determined that the service packet is an IP packet, and a source/destination IP meets a service requirement, and then the service packet needs to be processed by the second kernel, and if it is determined that a source IP of the service packet is 10.8.8.123, it is determined that the second kernel needs to process the service packet.
In an embodiment of the present invention, the length of the service packet determines the length to be imported into the cache, and in the embodiment of the present invention, the description information not only needs to provide the physical address of the service packet, but also provides the length of the service packet as length information, so as to facilitate subsequent processing.
As shown in fig. 7, the above method step S402 may further include, but is not limited to, steps S501 to S503.
Step S501, obtaining the physical address of the service message according to the description information.
Step S502, obtaining a virtual address corresponding to the service message according to the physical address.
Step S503, determining to obtain address information according to the virtual address, and determining that the address information is the initial address of the cache of the second kernel.
In an embodiment, a virtual address of a service packet is used as address information, specifically, a processor obtains a physical address where the service packet is currently located according to description information, obtains a virtual address corresponding to the service packet according to the physical address, determines to obtain address information according to the virtual address, for example, the virtual address is used as address information, and determines that the address information is an initial address of a cache of a second core, in an embodiment, the processor also reads the address information into the cache of a first core to make the cache of the first core consistent with a memory, so that the caches of the first core and the second core are consistent with the memory, it can be understood that the description information in the embodiment of the present invention includes the physical address where the service packet is located, and a virtual address of the service packet in the memory can be obtained according to the physical address, so as to serve as the initial address of the cache of the second core, so that the second core processes the service message.
As shown in fig. 8, the above method step S404 may further include, but is not limited to, step S601 to step S603.
Step S601, obtaining the storage time cached in the second kernel.
Step S602, obtaining a preset time threshold, and determining that the cache with the storage time greater than the preset time threshold in the second core is a target cache.
Step S603, by internal cache management of the processor, removing the target cache from the second core, and reading the address information and the length information into the cache of the second core after removal.
In an embodiment, the size of any processing core is limited, after a system applied by a processor runs for a long time, a cache is easily full, and then new data needs to be imported into the cache, and the original cache needs to be cleaned, otherwise, the performance of the processor is affected, in the embodiment of the invention, when the processor processes a service message, the cache of a second core needs to be cleaned, the storage time of the cache in the second core is obtained, a preset time threshold is obtained, the preset time threshold can be set according to actual needs, the cache with the storage time larger than the preset time threshold in the second core is determined as a target cache, the target cache is a cache/memory which is not used for the longest time, the target cache is removed from the second core through internal cache management of the processor, and address information and length information are read into the cache of the removed second core, and eliminating the target cache.
It should be noted that, in the embodiments of the present invention, the target cache is removed through an internal cache management algorithm of the processor, which may include a Least Recently Used algorithm (LRU), a Random algorithm (Random), a First In First Out (FIFO) or a Round Robin algorithm (Round Robin), which is not limited herein.
As shown in fig. 9, before step S101 of the method, steps S701 to S704 may be further included, but are not limited to.
Step S701, acquiring an initialization setting instruction of the processor, and setting a packet receiving thread according to the initialization setting instruction, so that the processor receives the service packet.
Step S702 is to create a first service processing thread of the first kernel, and to associate the first service processing thread to the first kernel, where the first service processing thread is used to process a service packet.
Step S703, a second service processing thread of the second kernel is created, and the second service processing thread is associated with the second kernel, where the second service processing thread is used for processing the service packet.
Step S704, the service packet is associated with the first kernel for execution.
In an embodiment, the processor may further perform an initialization operation before acquiring the service packet, the processor may acquire an initialization setting instruction, and set the portal driver packet receiving thread of the processor according to the initialization setting instruction, so that the processor receives the service message and then creates service processing threads in the cores respectively, including creating a first service processing thread of the first core, and the first service processing thread is compatible to the first kernel, the first service processing thread is used for processing the service message, and creates a second business processing thread of the second kernel and affinites the second business processing thread to the second kernel, the second service processing thread is used for processing the service message and making the service message be compatible with the first kernel for execution, that is, the thread corresponding to the service packet may run on this kernel, and may not run on other kernels. The service message is compatible on the first kernel, so that the service message is prevented from being switched and operated in different processor kernels, and the processing efficiency is improved.
As shown in fig. 10, after step S103 of the above method, steps S801 to S802 may be further included, but not limited thereto.
In step S801, a memory pointer corresponding to the processor is obtained.
Step S802, the address information corresponding to the memory pointer is transmitted to the first service processing thread and the second service processing thread, so that the first kernel and the second kernel concurrently process the service packet.
In an embodiment, after a service packet needs to be concurrently processed by a first kernel and a second kernel, a processor transmits address information of a pointer where the service packet is located to the first service processing thread and the second service processing thread, and the service packet is enabled to be concurrently processed, that is, two kernels of the processor process the same service packet and obtain address information of one service packet at the same time, the first kernel processes a two-layer packet header of the packet, and the second kernel processes a three-layer packet header of the packet, and the packets do not conflict with each other.
In the following, an embodiment of a specific application scenario of the present invention is described:
the embodiment of the invention provides a method for processing a message by multiple cores in a 5G network, which reduces the execution time of a processor introduced by cache inconsistency and greatly improves the message processing efficiency. As shown in fig. 2, after the core 1 receives a message from the network port, it determines that the message needs to be processed by the core 2, and then the page table and the content of the memory block where the message is located are cached in the core 2, and meanwhile, the page table and the content of the processed message are removed from the cache, so that when the core 2 processes the current message, the message already ensures the consistency of the cache of the memory, and the missing page fault cannot be triggered to greatly increase the processing time, wherein:
the system initialization of the processor is divided into the following steps:
1. setting an Ethernet port driving packet receiving thread EthRxTask and affinity kernel 1(affinity), wherein the message is only executed on the kernel 1;
2. creating a service processing thread App1RxTask of the kernel 1 and making the kernel 1 compatible;
3. create the kernel 2 business process thread App2RxTask and affinity to kernel 2.
The network port driving packet receiving thread EthRxTask is as follows:
1. determining a physical address packet PHYAddr and a length size of a currently received message from a network port hardware register;
2. acquiring a virtual address packetVirAddr of the message according to the packetPHYADdr;
3. the method comprises the steps of (invalidate) invalidating a cache of an inner core 1, triggering a cache and a memory synchronization mechanism in a CPU (central processing unit) when an initial address is packetVirAddr and the length is size, and forcibly reading memory data into the cache to keep the cache and the memory consistent;
4. reading the message content, judging whether the kernel 2 is required to carry out concurrent processing, if so, entering the next step, otherwise, transmitting the packetVirAddr to App1RxTask, and returning to the step 1 in the current section;
5. invalidate (invalidate) the cache of kernel 2, the starting address is packetVirAddr, the length is size;
6. the CPU internal cache management algorithm is used for eliminating the cache/memory which is not used for the longest time;
7. transmitting the pointer packetVirAddr in which the message is positioned to App1RxTask and App2RxTask, and performing concurrent processing on the pointers;
8. returning to the step 1.
The above embodiment is only a case of one scenario and is not meant to be a limitation of the embodiment of the present invention.
Referring to fig. 11, fig. 11 is a schematic block diagram of an electronic device according to an embodiment of the present invention.
As shown in fig. 11, the electronic device 100 includes a processor 101 and a memory 102, and the processor 101 and the memory 102 are connected by a bus 103, such as an I2C (Inter-integrated Circuit) bus.
In particular, the processor 101 is used to provide computing and control capabilities, supporting the operation of the entire electronic device. The Processor 101 may be a Central Processing Unit (CPU), and the Processor 101 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, etc. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Specifically, the Memory 102 may be a Flash chip, a Read-Only Memory (ROM) magnetic disk, an optical disk, a usb disk, or a removable hard disk.
Those skilled in the art will appreciate that the architecture shown in fig. 11 is merely a block diagram of some of the structures associated with an embodiment of the present invention and does not constitute a limitation on the electronic device to which an embodiment of the present invention may be applied, and that a particular server may include more or less components than those shown, or some of the components may be combined, or have a different arrangement of components.
The processor is configured to run a computer program stored in the memory, and when executing the computer program, implement any one of the methods for processing a packet in a 5G network multi-core provided by the embodiments of the present invention.
In an embodiment, the processor is configured to run a computer program stored in the memory.
It should be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the electronic device described above may refer to a corresponding process in the foregoing method embodiment for processing a packet in a 5G network multiple core of the electronic device, and details are not described here again.
An embodiment of the present invention further provides a storage medium for a computer-readable storage, where the storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the steps of the method for processing a packet by using a 5G network multi-core for a server according to any one of the descriptions of the present invention, and/or the steps of the method for processing a packet by using a 5G network multi-core for an electronic device according to any one of the descriptions of the present invention.
The storage medium may be an internal storage unit of the electronic device described in the foregoing embodiment, for example, a hard disk or a memory of the electronic device. The storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the electronic device.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware embodiment, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
It should be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items and includes such combinations. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments. While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for processing a message by multiple cores in a 5G network is applied to a processor, wherein the processor comprises a first core and a second core, and the method comprises the following steps:
receiving a service message and determining description information of the service message;
obtaining address information of the service message according to the description information, and reading the address information into a cache of the first kernel;
reading the content of the service message, determining that the service message needs to be processed by the first kernel and the second kernel concurrently, and reading the address information into the cache of the second kernel.
2. The method according to claim 1, wherein the obtaining address information of the service packet according to the description information and reading the address information into the cache of the first core comprises:
obtaining the physical address of the service message according to the description information;
obtaining a virtual address corresponding to the service message according to the physical address;
and determining to obtain the address information according to the virtual address, and reading the address information into a cache of the first kernel.
3. The method according to claim 2, wherein the description information includes length information of the service packet, and the determining, according to the virtual address, to obtain the address information and read the address information into the cache of the first core includes:
invalidating the cache of the first core;
determining to obtain the address information according to the virtual address, and determining that the address information is an initial address of the cache of the first kernel;
determining the length information as the length of the cache of the first kernel;
and triggering a cache and memory synchronization mechanism inside the processor, and reading the address information and the length information into the cache of the first kernel.
4. The method according to claim 1, wherein the description information includes length information of the service packet, and the reading the address information into the cache of the second core includes:
invalidating the cache of the second core;
determining that the address information is a starting address of the cache of the second core;
determining the length information as the length of the cache of the second kernel;
and reading the address information and the length information into a cache of the second kernel.
5. The method according to claim 4, wherein the determining that the address information is a starting address of the cache of the second core comprises:
obtaining the physical address of the service message according to the description information;
obtaining a virtual address corresponding to the service message according to the physical address;
and determining to obtain the address information according to the virtual address, and determining that the address information is the initial address of the cache of the second kernel.
6. The method according to claim 4, wherein reading the address information and the length information into the cache of the second core comprises:
acquiring the storage time cached in the second kernel;
acquiring a preset time threshold, and determining the cache with the storage time larger than the preset time threshold in the second kernel as a target cache;
and eliminating the target cache in the second kernel through internal cache management of the processor, and reading the address information and the length information into the cache of the second kernel after elimination.
7. The method according to claim 1, wherein before receiving the service packet and determining the description information of the service packet, the method further comprises:
acquiring an initialization setting instruction of the processor, and setting a network port driving packet receiving thread of the processor according to the initialization setting instruction so that the processor receives the service message;
creating a first service processing thread of the first kernel, and making the first service processing thread compatible with the first kernel, wherein the first service processing thread is used for processing the service message;
creating a second service processing thread of the second kernel, and making the second service processing thread compatible with the second kernel, wherein the second service processing thread is used for processing the service message;
and the service message is attached to the first kernel for execution.
8. The method according to claim 7, wherein after the reading of the address information into the cache of the second core, the method further comprises:
acquiring a memory pointer corresponding to the processor;
and transmitting the address information corresponding to the memory pointer to the first service processing thread and the second service processing thread so that the first kernel and the second kernel can concurrently process the service message.
9. An electronic device, comprising: memory, processor and computer program stored in the memory and executable on the processor, characterized in that the processor implements the method for processing messages in a 5G network multi-core according to any one of claims 1 to 8 when executing the computer program.
10. A computer-readable storage medium storing computer-executable instructions for performing the method for processing packets in a 5G network multi-core according to any one of claims 1 to 8.
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| CN202210195908.7A CN114579478A (en) | 2022-03-01 | 2022-03-01 | Method for processing message in 5G network multi-core, electronic equipment and storage medium |
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